Claims
- 1. A method for integrating a peripheral into an integrated circuit comprising:
selecting a first existing design for the peripheral with a first interface to a first communications bus and the first communications bus; selecting a second existing design with a second communications bus with a second interface to a computer communications bus; coupling the first and second existing designs together; and integrating the first and second existing designs into the integrated circuit.
- 2. The method of claim 1, wherein the coupling step couples the first and the second communications buses.
- 3. The method of claim 1, wherein the first and second communications buses are compatible communications buses.
- 4. The method of claim 3, wherein the first and second communications bus is a Universal Serial Bus (USB) compliant bus.
- 5. The method of claim 4, wherein the first and second interfaces are modified to support bit-parallel communications.
- 6. The method of claim 3, wherein the first and second communications bus is an International Electrical and Electronics Engineers (IEEE) 1394 compliant bus.
- 7. The method of claim 3, wherein the first and second communications bus is Small Computer System Interface (SCSI) compliant bus.
- 8. The method of claim 1, wherein the first existing design is an existing design for the peripheral, previously created and tested.
- 9. The method of claim 1, wherein the second existing design is an existing design for a communications bus interface to a computer previously created and tested.
- 10. An integrated circuit comprising:
a first pre-existing design comprising:
a peripheral; a first interface coupled to the peripheral, the first interface containing circuitry to translate signals produced by the peripheral in a first protocol into a second protocol; a first communications bus coupled to the first pre-existing design, the first communications bus to carry signals to and from the first pre-existing design; a second pre-existing design coupled to the first communications bus, the second pre-existing design comprising:
a second interface coupled to the first communications bus, the second interface containing circuitry to translate signals carried by the first communications bus in a third protocol into a fourth protocol; and a second communications bus coupled to the second interface, to carry signals to and from the second interface.
- 11. The integrated circuit of claim 10, wherein a communications bus comprises a set of electrically conductive lines, a set of signaling protocols, and a bus controller, wherein the first communications bus is a set of electrically conductive lines, and wherein the first and second interfaces simulate the presence of the first communications bus on the set of electrically conductive lines.
- 12. The integrated circuit of claim 11, wherein to the integrated peripheral and second communications bus, the set of electrically conductive lines appear to be the first communications bus.
- 13. The integrated circuit of claim 11, wherein the first communications bus is an Universal Serial Bus (USB) and signals are transmitted in a parallel fashion.
- 14. The integrated circuit of claim 11, wherein signals transported on the first communications bus is transported using a signaling protocol of the first communications bus.
- 15. The integrated circuit of claim 10, wherein the integrated circuit placed onto a circuit board inside the computer.
- 16. The integrated circuit of claim 10, wherein the integrated circuit is part of a larger integrated circuit that is placed onto a circuit board inside a computer.
- 17. The integrated circuit of claim 10, wherein the first interface is coupled to the peripheral via a wireless communications link.
- 18. The integrated circuit of claim 17, wherein the wireless communications link is a Bluetooth communications link.
- 19. A computer comprising:
a processor; a memory coupled to the processor; a peripheral communications bus coupled to the processor, the peripheral communications bus permitting the processor to exchange information with peripherals attached to the peripheral communications bus; an integrated peripheral coupled to the peripheral communications bus, the integrated peripheral comprising:
a first pre-existing design comprising:
a functional unit to perform the function of the integrated peripheral; a first interface coupled to the integrated peripheral, the first interface containing circuitry to translate signals produced by the integrated peripheral in a first protocol into a second protocol; a first communications bus coupled to the first pre-existing design, the first communications bus to carry signals to and from the first pre-existing design; and a second pre-existing design coupled to the first communications bus, the second pre-existing design comprising a second interface coupled to the first communications bus and the peripheral communications bus, the second interface containing circuitry to translate signals carried by the first communications bus in a third protocol that is compatible with the peripheral communications bus.
- 20. The computer of claim 19, wherein the integrated peripheral is an integrated circuit located on a common circuit board with the processor.
- 21. The computer of claim 19, wherein the integrated peripheral is an integrated circuit located on a first circuit board that is attached to a second circuit board that contains the processor.
- 22. The computer of claim 21, wherein the first circuit board is external to a housing containing the second circuit board, and wherein the first and second circuit boards are attached via a cable.
Parent Case Info
[0001] This application claims priority to a provisional application entitled “Wireless PCI Single Chip Solution,” serial No. 60/335,693, filed Oct. 10, 2001. The provisional application is incorporated herein by reference.
Provisional Applications (1)
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Number |
Date |
Country |
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60335693 |
Oct 2001 |
US |