Claims
- 1. A simulator for a design under test, comprising:
a host workstation, comprising:
a user interface; and a software clock facility; and a hardware acceleration box adapted to contain the design under test, comprising:
a simulation control module, comprising:
a clock generator adapted to generate a design clock signal; and a state machine adapted to manage one or more design clock signals; wherein the simulation control module is implemented in hardware, and wherein the simulation control module is adapted to simulate the design under test for a plurality of design clock cycles without intervention from the host workstation.
- 2. The simulator of claim 1, wherein the simulation control module further comprises an oversampler circuit.
- 3. The simulator of claim 1, wherein the simulation control module further comprises a done circuit.
- 4. The simulator of claim 1, wherein the simulation control module further comprises a min circuit.
- 5. The simulator of claim 1, wherein the simulation control module further comprises an abort condition tree.
- 6. The simulator of claim 5, wherein the abort condition tree is adapted to detect an abort condition occurring by processing a plurality of abort conditions from the design under test.
- 7. The simulator of claim 6, wherein the simulation control module is adapted to abort the simulation and return control to the host workstation upon detection of an abort condition.
- 8. The simulator of claim 1, wherein the hardware acceleration box further comprises bypass logic adapted to bypass the simulation control module and to provide a clock signal from the host workstation to the design under test.
- 9. The simulator of claim 8, wherein the bypass logic is adapted to toggle clock phase shifts without intervention from the host workstation.
- 10. The simulator of claim 1, wherein the host workstation further comprises a simulation control module layer adapted to hide the functionality of the simulation control module from the host workstation.
- 11. The simulator of claim 1, wherein the state machine comprises:
an idle state; a running state; and an aborted state.
- 12. The simulator of claim 11, wherein the running state comprises an oversampling state
- 13. The simulator of claim 12, wherein the running state further comprises an abort pending state.
- 14. The simulator of claim 11, wherein the state machine further comprises an abort running state.
- 15. The simulator of claim 1, wherein the simulation control module comprises a plurality of clock generators, each adapted to generate an asynchronous design clock signal.
- 16. The simulator of claim 1, wherein the simulation control module is adapted to simulate only design clock phases having a design clock edge.
- 17. The simulator of claim 1, wherein the simulation control module is adapted to allow intervention by the host workstation only upon generation of an abort condition.
RELATED APPLICATION INFORMATION
[0001] This application claims the benefit of US Provisional Application No. 60/323,586, filed on Sep. 19, 2001, titled “Simulation Control Module and Hardware Clock Facility”.
Provisional Applications (1)
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Number |
Date |
Country |
|
60323586 |
Sep 2001 |
US |