SIMULATION METHOD AND SIMULATION PROGRAM

Abstract

There is a need for keeping the amount of data to be saved and a simulation process time almost constant irrespectively of a hierarchical level of a hierarchical circuit to be simulated. This simulation method includes a first process and a second process. The first process saves result data obtained from simulating an interface node between higher-level and lower-level hierarchies in accordance with a result of simulation using hierarchical circuit data hierarchized for multiple hierarchies. The second process uses result data saved by the first process to reproduce internal node data not saved by the first process. Result data for the interface node between hierarchies indirectly determines a value for the internal node. Result data to be saved is data concerning the interface node between hierarchies. The amount of saved data and the time needed for the second process are independent of a hierarchical level or a higher-level or lower-level hierarchy.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a conceptual diagram showing the concept as the basis for a simulation method according to the invention together with an example of result output division;

FIG. 2 is a principle diagram further showing the concept of the simulation method according to the invention;

FIG. 3 is a principle diagram showing the principle of the simulation method according to the invention in terms of a hierarchical structure of hierarchical circuit data;

FIG. 4 is an explanatory diagram exemplifying a state where a circuit under simulation is subject to a partial circuit modification or an element parameter modification;

FIG. 5 is an explanatory diagram exemplifying a method of providing a simulation result reflecting a partial circuit modification or an element parameter modification, if any;

FIG. 6 is a principle diagram showing the principle of the simulation method for solving a partial modification in FIG. 5 in terms of the hierarchical structure of hierarchical circuit data;

FIG. 7 is a conceptual diagram showing the concept of parallel processing of an on-the-fly simulation;

FIG. 8 is a principle diagram showing a parallel process for a simulation similarly to the on-the-fly simulation for a partial area due to a circuit modification or the like;

FIG. 9 is a system diagram exemplifying a data processing system for implementing the simulation method according to the invention;

FIG. 10 is a flowchart showing a circuit simulation process of a circuit simulator in FIG. 9;

FIG. 11 is a flowchart showing control over displaying a simulation result by result display control means and partial circuit simulation control means in FIG. 9;

FIG. 12 is a system diagram exemplifying details of result display control means that includes the partial circuit simulation control means and the result display control means in FIG. 9 and has an on-the-fly simulation function;

FIG. 13 is an explanatory diagram exemplifying a hierarchical structure of circuit data having a dependent voltage source where the value of the voltage of one block depends on the current or voltage of branches or nodes of other blocks (either interface or internal to the block);

FIG. 14 is a schematic explanatory diagram showing relationship between a hierarchical structure and a hierarchical level for circuit blocks in FIG. 13;

FIG. 15 is an explanatory diagram exemplifying information stored in a circuit block for each hierarchy in hierarchical circuit data;

FIG. 16 is an explanatory diagram showing data modes for a circuit block including only lower-level blocks;

FIG. 17 is an explanatory diagram showing data modes for a circuit block including a lower-level block and an element;

FIG. 18 is an explanatory diagram showing data modes for a circuit block including only elements;

FIG. 19 is an explanatory diagram exemplifying a general data mode of hierarchized circuit block information and hierarchical levels for an entire circuit under simulation;

FIG. 20 is an information format diagram showing node information extracted from the circuit block information in the data mode as exemplified in FIG. 19;

FIG. 21 is a data structure explanatory diagram exemplifying hierarchized circuit block information and hierarchical levels for the entire hierarchical circuit under simulation as exemplified in FIG. 13;

FIG. 22 is an explanatory diagram showing node names with hierarchical information indicative of node information about all externally and internally connected nodes extracted from the circuit block information in FIG. 21;

FIG. 23 is a control flowchart showing a result output node extraction process;

FIG. 24 exemplifies dependency in which result data from an internal node directly influences values of a current source and a voltage source;

FIG. 25 is a conceptual diagram showing that the on-the-fly simulation generates a simulation result for a node with hierarchical information in the circuit of FIG. 13;

FIG. 26 is a conceptual diagram showing that the on-the-fly simulation generates a simulation result for an internal node when there is a lower level hierarchical block;

FIG. 27 is a conceptual diagram showing that the on-the-fly simulation generates a simulation result for an internal node when there is a lower level hierarchical block;

FIG. 28 is an outlined system diagram showing an example of obtaining the proper result output node data from the circuit simulator;

FIG. 29 is an explanatory diagram exemplifying a mode where there is a possibility of voltage source loop formation if the standard voltage source assignment to interface nodes is used for the second process;

FIG. 30 is a circuit diagram exemplifying a case where a partial circuit in the circuit area of FIG. 29 forms a voltage source loop;

FIG. 31 is a circuit diagram exemplifying a circuit state that prevents the formation of a voltage source loop during the on-the-fly simulation for the circuit area of FIG. 29;

FIG. 32 is a circuit diagram exemplifying a method of finding electric current information about a higher-level interface node for which a voltage source loop should be suppressed;

FIG. 33 is a circuit diagram exemplifying another circuit state where the internal partial circuit is connected to another internal circuit other than the higher-level interface node and there is a possibility of voltage source loop formation if the standard voltage source assignment to interface nodes is used for the second process;

FIG. 34 is a circuit diagram showing a case of floating all higher-level interface nodes as a solution for the case in FIG. 33;

FIG. 35 is a circuit diagram showing a case of supplying electric current information as input/output information for all the higher-level interface nodes when the on-the-fly simulation in FIG. 33 is performed to verify electric currents flowing through voltage sources of the partial circuit;

FIG. 36 is a circuit diagram showing a case of performing the on-the-fly simulation by removing a partial circuit VLC when the on-the-fly simulation need not verify an electric current flowing through all elements in the partial circuit;

FIG. 37 is a circuit diagram exemplifying a circuit state where voltage loop formation is possible during the on-the-fly simulation when the partial circuit is not connected to a ground potential;

FIG. 38 is a circuit diagram showing a state of forming voltage source loops by supplying voltage source information for all higher-level interface nodes in FIG. 37;

FIG. 39 is a circuit diagram showing a solution for suppressing generation of the voltage source loop in FIG. 38 when current flow data is required;

FIG. 40 is a circuit diagram exemplifying a circuit state where voltage loop formation is possible during the on-the-fly simulation in consideration for a ground potential not connected to a partial circuit, but with the partial circuit also connected to another internal circuit;

FIG. 41 is a circuit diagram showing a specific solution for the state in FIG. 40, i.e., supplying one lower-level interface node with voltage source information and supplying the partial circuit with one potential reference instead of the ground potential, where current flow data is not required;

FIG. 42 is a circuit diagram showing a solution for performing the simulation to verify an electric current flowing through the voltage source of the partial circuit in FIG. 41;

FIG. 43 is a circuit diagram showing a mode of performing the on-the-fly simulation for the partial circuit VLC using data stored in a lower-level interface node interfaced with a low hierarchy;

FIG. 44 is a circuit diagram showing a state of supplying voltage source data as simulation result data prestored in the lower-level interface node in FIG. 43;

FIG. 45 is a circuit diagram showing a state of forming a voltage source loop when the partial circuit is configured to include one of the voltage source and an inductor or to include at least two connected elements such as the voltage source and the inductor and, in this case, has a serial circuit of the voltage source and the inductor;

FIG. 46 is a circuit diagram exemplifying a circuit state preventing the formation of voltage loops during the on-the-fly simulation in FIG. 45 where internal current flow data is required;

FIG. 47 is a circuit diagram exemplifying a method of finding electric current information about the lower-level interface nodes;

FIG. 48 is a circuit diagram exemplifying a circuit state where voltage loop formation is possible during the on-the-fly simulation when the circuit configuration consists of the partial circuit connected to another internal circuit other than the lower-level interface node;

FIG. 49 is a circuit diagram showing a case of floating all higher-level interface nodes as a solution for the case in FIG. 48 where internal current flow is not required;

FIG. 50 is a circuit diagram showing a case of supplying electric current information as input/output information for all the lower-level interface nodes when the on-the-fly simulation in FIG. 49 is performed to verify an electric current flowing through a voltage source of the partial circuit;

FIG. 51 is a circuit diagram showing a case of performing the on-the-fly simulation by removing a partial circuit when the on-the-fly simulation need not verify an electric current flowing through all elements in the partial circuit;

FIG. 52 is a circuit diagram exemplifying a circuit state where voltage loop formation is possible during the on-the-fly simulation when considering a partial circuit not connected to a ground potential;

FIG. 53 is a circuit diagram showing a state of forming voltage source loops by supplying voltage source information for all higher-level interface nodes in FIG. 52;

FIG. 54 is a circuit diagram showing a solution for suppressing generation of the voltage source loop in FIG. 53;

FIG. 55 is a circuit diagram exemplifying a circuit state where voltage loop formation is possible during the on-the-fly simulation when considering a ground potential not connected to a partial circuit, but with the partial circuit connected to another circuit;

FIG. 56 is a circuit diagram showing a specific solution for the state in FIG. 55, i.e., supplying one higher-level interface node with voltage source information and supplying the partial circuit with one potential reference instead of the ground potential, and where current flow information is not required; and

FIG. 57 is a circuit diagram showing a solution for performing the simulation to verify an electric current flowing through the voltage source of the partial circuit in FIG. 56.

Claims

1. A simulation method comprising: a first process for saving result data obtained from simulating an interface node between higher-level and lower-level hierarchies in accordance with a result of simulation using hierarchical circuit data hierarchized for a plurality of hierarchies; anda second process for using result data saved by the first process to reproduce internal node data not saved by the first process.

2. The simulation method according to claim 1, wherein a simulation in the second process is performed using a same initial condition as for a simulation in the first process.

3. The simulation method according to claim 2, wherein the first process also saves simulation result data of an internal node different from an interface node between higher-level and lower-level hierarchies when the simulation result data determines a value of a voltage source or a current source in another hierarchy.

4. The simulation method according to claim 1, wherein a hierarchical circuit having an internal node as an object of the second process has a partial circuit including one of elements such as a voltage source and an inductor or at least two connected elements such as a voltage source and an inductor and have one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy,wherein the partial circuit is connected to a ground potential, andwherein the second process then supplies electric current information as input/output information to the specific node.

5. The simulation method according to claim 1, wherein a hierarchical circuit having an internal node as an object of the second process has a partial circuit including one voltage source or at least two connected voltage sources, one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy, and another circuit for connection to the partial circuit,wherein the partial circuit is connected to a ground potential, andwherein the second process then supplies electric current information as input/output information to the specific node.

6. The simulation method according to claim 1, wherein a hierarchical circuit having an internal node as an object of the second process has a partial circuit including one voltage source or two or more connected voltage sources, one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy, and another circuit for connection to the partial circuit,wherein the partial circuit is connected to a ground potential,wherein the second process ignores electric current flowing through voltage sources of the partial circuit, andwherein all the specific nodes are then floated.

7. The simulation method according to claim 1, wherein a hierarchical circuit having an internal node as an object of the second process has a partial circuit including one of elements such as a voltage source and an inductor or at least two connected elements such as a voltage source and an inductor and have one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy,wherein the partial circuit is connected to a ground potential,wherein the second process ignores electric current flowing through all elements of the partial circuit, andwherein the partial circuit is then deleted.

8. The simulation method according to claim 1, wherein a hierarchical circuit having an internal node as an object of the second process has a partial circuit including one of elements such as a voltage source and an inductor or at least two connected elements such as a voltage source and an inductor and have two or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy,wherein the partial circuit is not connected to a ground potential, andwherein the second process then supplies voltage source information as input/output information to one of the two or more specific nodes and supplies current source information as input/output information to the remaining specific nodes.

9. The simulation method according to claim 1, wherein a hierarchical circuit having an internal node as an object of the second process has a partial circuit including one voltage source or at least two connected voltage sources, two or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy, and another circuit for connection to the partial circuit,wherein the partial circuit is not connected to a ground potential, andwherein the second process then supplies voltage source information as input/output information to one of the two or more specific nodes and supplies current source information as input/output information to the remaining specific nodes.

10. The simulation method according to claim 1, wherein a hierarchical circuit having an internal node as an object of the second process has a partial circuit including one voltage source or two or more connected voltage sources, two or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy, and another circuit for connection to the partial circuit,wherein the partial circuit is not connected to a ground potential,wherein the second process ignores electric current flowing through voltage sources of the partial circuit, andwherein the second process then supplies voltage source information as input/output information to one specific node and floats the remaining specific nodes.

11. The simulation method according to claim 1, wherein a hierarchical circuit having an internal node as an object of the second process has a partial circuit including one of elements such as a voltage source and an inductor or at least two connected elements such as a voltage source and an inductor and have one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy,wherein the partial circuit is not connected to a ground potential,wherein the second process ignores electric current flowing through all elements of the partial circuit, andwherein the partial circuit is then deleted.

12. A simulation method comprising: an extraction process for extracting a circuit node in a specified hierarchy from hierarchical circuit data;a simulation execution process for executing a circuit simulation using a circuit node extracted by the extraction process as a result output node;a save process for saving result data that is obtained by the simulation execution process for a result output node and relates to an interface node between higher-level and lower-level hierarchies; anda simulation re-execution process for using the saved result data concerning an interface node between a specified hierarchy and a hierarchy one level higher or lower and obtaining simulation result data for a circuit node in the specified hierarchy.

13. The simulation method according to claim 12, wherein the save process saves simulation result data for an internal node different from an interface node between higher-level and lower-level hierarchies when the simulation result data determines a value for a voltage source or current source in another hierarchy, andwherein the save process saves simulation result data for an element in the hierarchy when the simulation result data determines a value for a voltage source or current source in another hierarchy.

14. The simulation method according to claim 13, wherein the simulation re-execution process performs a simulation under a same initial condition as for a simulation by the simulation execution process.

15. The simulation method according to claim 14, further comprising: a display process for displaying result data saved by the save process in response to an instruction to display a simulation result or displaying a simulation result obtained by the simulation re-execution process.

16. The simulation method according to claim 15, wherein the extraction process registers a circuit node identifiable at a specified hierarchical level each time the extraction process changes a hierarchical level to a lower one while keeping track of a series of reference to a lower-level hierarchy in hierarchical circuit data, andwherein this process is performed for all series of reference in an object under simulation.

17. A simulation method comprising: a simulation execution process for performing a circuit simulation using a circuit node for a hierarchical circuit data in a specified hierarchy as a result output node;a save process for saving result data that is obtained by the simulation execution process for a result output node and relates to an interface node between higher-level and lower-level hierarchies;a first display process for displaying result data retrieved from those saved by the save process as a result of the simulation execution process;a simulation re-execution process for using the saved result data concerning an interface node between a specified hierarchy and a hierarchy one level higher or lower and obtaining simulation result data for a circuit node in the specified hierarchy; anda second display process for displaying result data from the simulation re-execution process.

18. The simulation method according to claim 17, wherein the save process saves simulation result data for an internal node different from an interface node between higher-level and lower-level hierarchies when the simulation result data determines a value for a voltage source or current source in another hierarchy, andwherein the save process saves simulation result data for an element in the hierarchy when the simulation result data determines a value for a voltage source or current source in another hierarchy.

19. The simulation method according to claim 18, wherein the simulation re-execution process performs a simulation under an initial condition equivalent to that for a simulation by the simulation execution process.

20. A simulation method comprising: a simulation execution process for performing a circuit simulation using a circuit node for a hierarchical circuit data in a specified hierarchy as a result output node;a save process for saving result data that is obtained by the simulation execution process for a result output node and relates to an interface node between higher-level and lower-level hierarchies; anda simulation re-execution process for performing a circuit simulation for a circuit node reflecting modification of the hierarchical circuit data, when modified, using the saved result data concerning an interface node between the circuit node and an interfaced hierarchy one level higher or lower.

21. The simulation method according to claim 20, wherein the simulation re-execution process parallel performs a circuit simulation for the modification reflecting circuit nodes whose signal paths are independent of each other.

22. A simulation method comprising: a first process for extracting a result output point in a specified higher-level hierarchy from an object under simulation;a second process for simulating an extracted result output point;a third process for saving result data that is obtained by the simulation execution process for a result output node and relates to an interface node between higher-level and lower-level hierarchies; anda fourth process for using the saved result data concerning an interface node between a specified hierarchy and a hierarchy one level higher or lower and simulating a circuit node in the specified hierarchy so as to obtain simulation result data under an initial condition equivalent to that for a simulation by the second process.

23. The simulation method according to claim 22, wherein the save process saves simulation result data for an internal node different from an interface node between higher-level and lower-level hierarchies when the simulation result data determines a value for a voltage source or current source in another hierarchy, andwherein the save process saves simulation result data for an element in the hierarchy when the simulation result data determines a value for a voltage source or current source in another hierarchy.

24. The simulation method according to claim 12, wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one of elements such as a voltage source and an inductor or at least two connected elements such as a voltage source and an inductor and have one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy,wherein the partial circuit is supposed to be connected to a ground potential, andwherein the second process then supplies electric current information as input/output information to the specific node.

25. The simulation method according to claim 12, wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one voltage source or at least two connected voltage sources, one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy, and another circuit for connection to the partial circuit,wherein the partial circuit is supposed to be connected to a ground potential, andwherein the second process then supplies electric current information as input/output information to the specific node.

26. The simulation method according to claim 12, wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one voltage source or two or more connected voltage sources, one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy, and another circuit for connection to the partial circuit,wherein the partial circuit is supposed to be connected to a ground potential,wherein the second process is supposed to ignore an electric current flowing through a voltage source of the partial circuit, andwherein all the specific nodes are then floated.

27. The simulation method according to claim 12, wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one of elements such as a voltage source and an inductor or at least two connected elements such as a voltage source and an inductor and have one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy,wherein the partial circuit is supposed to be connected to a ground potential,wherein the second process is supposed to ignore an electric current flowing through all elements of the partial circuit, andwherein the partial circuit is then deleted.

28. The simulation method according to claim 12, wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one of elements such as a voltage source and an inductor or at least two connected elements such as a voltage source and an inductor and have two or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy,wherein the partial circuit is supposed to be not connected to a ground potential, andwherein the second process then supplies voltage source information as input/output information to one of the two or more specific nodes and supplies current source information as input/output information to the remaining specific nodes.

29. The simulation method according to claim 12, wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one voltage source or at least two connected voltage sources, two or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy, and another circuit for connection to the partial circuit,wherein the partial circuit is supposed to be not connected to a ground potential, andwherein the second process then supplies voltage source information as input/output information to one of the two or more specific nodes and supplies current source information as input/output information to the remaining specific nodes.

30. The simulation method according to claim 12, wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one voltage source or two or more connected voltage sources, two or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy, and another circuit for connection to the partial circuit,wherein the partial circuit is supposed to be not connected to a ground potential,wherein the second process is supposed to ignore an electric current flowing through a voltage source of the partial circuit, andwherein the second process then supplies voltage source information as input/output information to one specific node and floats the remaining specific nodes.

31. The simulation method according to claim 12, 17, or 20, wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one of elements such as a voltage source and an inductor or at least two connected elements such as a voltage source and an inductor and have one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy,wherein the partial circuit is supposed to be not connected to a ground potential,wherein the second process is supposed to ignore an electric current flowing through all elements of the partial circuit, andwherein the partial circuit is then deleted.

32. A simulation program executed by a computer so as to perform a data process for supporting circuit simulation, the data process comprising: a first process for saving simulation result data concerning an interface node between higher-level and lower-level hierarchies out of a result of simulation using hierarchical circuit data hierarchized for a plurality of hierarchies; anda second process for using result data saved by the first process to reproduce internal node data not saved by the first process.

33. A simulation program executed by a computer so as to perform a data process for supporting circuit simulation, the data process comprising: an extraction process for extracting a circuit node in a specified hierarchy from hierarchical circuit data;a simulation execution process for executing a circuit simulation using a circuit node extracted by the extraction process as a result output node;a save process for saving result data that relates to an interface node between higher-level and lower-level hierarchies and is obtained by the simulation execution process for a result output node; anda simulation re-execution process for using the saved result data concerning an interface node between a specified hierarchy and a hierarchy one level higher or lower and obtaining simulation result data for a circuit node in the specified hierarchy.

34. A simulation program executed by a computer so as to perform a data process for supporting circuit simulation, the data process comprising: a simulation execution process for performing a circuit simulation using a circuit node for a hierarchical circuit data in a specified hierarchy as a result output node;a save process for saving result data that relates to an interface node between higher-level and lower-level hierarchies and is obtained by the simulation execution process for a result output node;a first display process for displaying result data retrieved from those saved by the save process as a result of the simulation execution process;a simulation re-execution process for using the saved result data concerning an interface node between a specified hierarchy and a hierarchy one level higher or lower and obtaining simulation result data for a circuit node in the specified hierarchy; anda second display process for displaying result data from the simulation re-execution process.

35. A simulation program executed by a computer so as to perform a data process for supporting circuit simulation, the data process comprising: a first process for extracting a result output point in a specified higher-level hierarchy from an object under simulation;a second process for simulating an extracted result output point;a third process for saving result data that relates to an interface node between higher-level and lower-level hierarchies and is obtained by the simulation execution process for a result output node; anda fourth process for using the saved result data concerning an interface node between a specified hierarchy and a hierarchy one level higher or lower and simulating a circuit node in the specified hierarchy so as to obtain simulation result data under an initial condition equivalent to that for a simulation by the second process.

36. The simulation method according to claim 17, wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one of elements such as a voltage source and an inductor or at least two connected elements such as a voltage source and an inductor and have one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy,wherein the partial circuit is supposed to be connected to a ground potential, andwherein the second process then supplies electric current information as input/output information to the specific node.

37. The simulation method according to claim 20, wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one of elements such as a voltage source and an inductor or at least two connected elements such as a voltage source and an inductor and have one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy,wherein the partial circuit is supposed to be connected to a ground potential, andwherein the second process then supplies electric current information as input/output information to the specific node.

38. The simulation method according to claim 17, wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one voltage source or at least two connected voltage sources, one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy, and another circuit for connection to the partial circuit,wherein the partial circuit is supposed to be connected to a ground potential, andwherein the second process then supplies electric current information as input/output information to the specific node.

39. The simulation method according to claim 20, wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one voltage source or at least two connected voltage sources, one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy, and another circuit for connection to the partial circuit,wherein the partial circuit is supposed to be connected to a ground potential, andwherein the second process then supplies electric current information as input/output information to the specific node.

40. The simulation method according to claim 17, wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one voltage source or two or more connected voltage sources, one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy, and another circuit for connection to the partial circuit,wherein the partial circuit is supposed to be connected to a ground potential,wherein the second process is supposed to ignore an electric current flowing through a voltage source of the partial circuit, andwherein all the specific nodes are then floated.

41. The simulation method according to claim 20, wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one voltage source or two or more connected voltage sources, one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy, and another circuit for connection to the partial circuit,wherein the partial circuit is supposed to be connected to a ground potential,wherein the second process is supposed to ignore an electric current flowing through a voltage source of the partial circuit, andwherein all the specific nodes are then floated.

42. The simulation method according to claim 17, wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one of elements such as a voltage source and an inductor or at least two connected elements such as a voltage source and an inductor and have one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy,wherein the partial circuit is supposed to be connected to a ground potential,wherein the second process is supposed to ignore an electric current flowing through all elements of the partial circuit, andwherein the partial circuit is then deleted.

43. The simulation method according to claim 20, wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one of elements such as a voltage source and an inductor or at least two connected elements such as a voltage source and an inductor and have one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy,wherein the partial circuit is supposed to be connected to a ground potential,wherein the second process is supposed to ignore an electric current flowing through all elements of the partial circuit, andwherein the partial circuit is then deleted.

44. The simulation method according to claim 17, wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one of elements such as a voltage source and an inductor or at least two connected elements such as a voltage source and an inductor and have two or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy,wherein the partial circuit is supposed to be not connected to a ground potential, andwherein the second process then supplies voltage source information as input/output information to one of the two or more specific nodes and supplies current source information as input/output information to the remaining specific nodes.

45. The simulation method according to claim 20, wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one of elements such as a voltage source and an inductor or at least two connected elements such as a voltage source and an inductor and have two or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy,wherein the partial circuit is supposed to be not connected to a ground potential, andwherein the second process then supplies voltage source information as input/output information to one of the two or more specific nodes and supplies current source information as input/output information to the remaining specific nodes.

46. The simulation method according to claim 17, wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one voltage source or at least two connected voltage sources, two or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy, and another circuit for connection to the partial circuit,wherein the partial circuit is supposed to be not connected to a ground potential, andwherein the second process then supplies voltage source information as input/output information to one of the two or more specific nodes and supplies current source information as input/output information to the remaining specific nodes.

47. The simulation method according to claim 20, wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one voltage source or at least two connected voltage sources, two or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy, and another circuit for connection to the partial circuit,wherein the partial circuit is supposed to be not connected to a ground potential, andwherein the second process then supplies voltage source information as input/output information to one of the two or more specific nodes and supplies current source information as input/output information to the remaining specific nodes.

48. The simulation method according to claim 17, wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one voltage source or two or more connected voltage sources, two or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy, and another circuit for connection to the partial circuit,wherein the partial circuit is supposed to be not connected to a ground potential,wherein the second process is supposed to ignore an electric current flowing through a voltage source of the partial circuit, andwherein the second process then supplies voltage source information as input/output information to one specific node and floats the remaining specific nodes.

49. The simulation method according to claim 20, wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one voltage source or two or more connected voltage sources, two or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy, and another circuit for connection to the partial circuit,wherein the partial circuit is supposed to be not connected to a ground potential,wherein the second process is supposed to ignore an electric current flowing through a voltage source of the partial circuit, andwherein the second process then supplies voltage source information as input/output information to one specific node and floats the remaining specific nodes.

50. The simulation method according to claim 17, wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one of elements such as a voltage source and an inductor or at least two connected elements such as a voltage source and an inductor and have one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy,wherein the partial circuit is supposed to be not connected to a ground potential,wherein the second process is supposed to ignore an electric current flowing through all elements of the partial circuit, andwherein the partial circuit is then deleted.

51. The simulation method according to claim 20, wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one of elements such as a voltage source and an inductor or at least two connected elements such as a voltage source and an inductor and have one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy,wherein the partial circuit is supposed to be not connected to a ground potential,wherein the second process is supposed to ignore an electric current flowing through all elements of the partial circuit, andwherein the partial circuit is then deleted.