This disclosure relates generally to wireless receivers and, more particularly, to simultaneous accommodation of a low power signal and an interfering signal in a Radio Frequency (RF) receiver.
A Radio Frequency (RF) receiver (e.g., a Global Positioning System (GPS) receiver) may receive an input signal including a desired signal component and an interfering signal component. The interfering signal component may have a higher power level compared to the desired signal component. The RF receiver may not be capable of processing the interfering signal component simultaneously with the low level desired signal component due to limited bandwidth and/or dynamic range thereof. Moreover, an Analog-to-Digital Converter (ADC) circuit of the RF receiver may not convert the low power desired signal component properly due to a resolution limitation thereof.
A method, a circuit and/or a system of simultaneous accommodation of a low power signal and an interfering signal in a Radio Frequency (RF) receiver are disclosed.
In one aspect, a method includes providing a highly linear front end in a Radio Frequency (RF) receiver, implementing a high Effective Number of Bits (ENOB) Analog to Digital Converter (ADC) circuit in the RF receiver, and sampling, through the high ENOB ADC circuit, at a frequency having harmonics that do not coincide with a desired signal component of an input signal of the RF receiver to eliminate spurs within a data bandwidth of the RF receiver. The input signal includes the desired signal component and an interference signal component. The interference signal component has a higher power level than the desired signal component. The method also includes simultaneously accommodating the desired signal component and the interference signal component in the RF receiver based on an increased dynamic range of the RF receiver and the high ENOB ADC circuit provided through the highly linear front end and the high ENOB ADC circuit.
In another aspect, a method includes providing an RF receiver having dynamic range enough to simultaneously accommodate a desired signal component of an input signal and an interference signal component thereof. The interference signal component has a power level higher than that of the desired signal component. The RF receiver has a double superheterodyne configuration that includes an RF mixer and an image reject mixer. The method also includes selecting an image frequency of the image reject mixer to coincide with a frequency of the interference signal component to enable cancellation thereof through the image reject mixer while having a capability to receive the desired signal component.
In yet another aspect, a method includes implementing a high ENOB ADC circuit in an RF receiver having a double superheterodyne configuration including an RF mixer and an image reject mixer, and utilizing an output of a VCO to generate a local oscillator reference signal to the image reject mixer. The method also includes providing a clock signal to the high ENOB ADC circuit divided down in frequency from the output of the VCO providing the local oscillator reference signal to the image reject mixer to reduce a jitter thereof.
Further, in another aspect, an integrated circuit (IC) chip includes a high band channel receiver configured to receive a Global Positioning System (GPS) carrier signal L1 carrying a standard positioning code along with navigational data, and a low band channel receiver configured to receive a GPS carrier signal L2 carrying a precision positioning code. Each of the high band channel receiver and the low band channel receiver is capable of receiving L1 and L2 respectively with precision and mitigating ionospheric effects from L1 and L2 respectively. L1 has a higher frequency than L2.
The each of the high band channel receiver and the low band channel receiver includes a highly linear front end, and a high ENOB ADC circuit. A sampling frequency of the high ENOB ADC circuit has harmonics that do not coincide with a desired signal component of each of L1 and L2 to eliminate spurs within a data bandwidth of the each of the high band channel receiver and the low band channel receiver. The each of L1 and L2 additionally includes an interference signal component having a power level higher than that of the desired signal component.
The each of the high band channel receiver and the low band channel receiver is configured to simultaneously accommodate the desired signal component and the interference signal component of the each of L1 and L2 based on an increased dynamic range of the each of the high band channel receiver and the low band channel receiver and the high ENOB ADC circuit provided through the highly linear front end and the high ENOB ADC circuit.
Further, in yet another aspect, an in-band cancellation system includes an RF receiver, and a channel emulator to emulate a channel between a transmitter of an input signal and the RF receiver. The input signal includes an undesired in-band signal component and a desired signal component, and the channel emulator has a sampled version of the undesired in-band signal component fed as an input thereto. The in-band cancellation system also includes an adaptive filter having parameters capable of being varied based on the input signal being fed as a reference input thereto to vary a frequency of a correlated reference signal filtered therethrough. The correlated reference signal is generated based on a correlation between the input signal and the undesired in-band signal component. The filtered signal from the adaptive filter is configured to be subtracted from an output of the channel emulator to remove the in-band signal component from the input signal.
Still further, in yet another aspect, a method includes mixing an input signal including a desired signal component and an interference signal component close in frequency to the desired signal component down to an Intermediate Frequency (IF) through an RF receiver to reduce an interference bandwidth to account for during image rejection. The method also includes folding the interference signal component and the desired signal component during the image rejection through an image reject mixer of the RF receiver such that the interference signal component is out-of-band with respect to the desired signal component.
Furthermore, in yet another aspect, a wireless system includes a wireless transmitter, and a wireless RF receiver configured to receive an input signal from the wireless transmitter. The input signal includes a desired signal component and an interference signal component. The interference signal component has a power level higher than that of the desired signal component. The wireless RF receiver includes a highly linear front end; and a high ENOB ADC circuit. A sampling frequency of the high ENOB ADC circuit has harmonics that do not coincide with the desired signal component to eliminate spurs within a data bandwidth of the wireless RF receiver.
The wireless RF receiver is configured to simultaneously accommodate the desired signal component and the interference signal component based on an increased dynamic range of the wireless RF receiver and the high ENOB ADC circuit provided through the highly linear front end and the high ENOB ADC circuit.
The methods and systems disclosed herein may be implemented in any means for achieving various aspects, and may be executed in a form of a machine-readable medium embodying a set of instructions that, when executed by a machine, cause the machine to perform any of the operations disclosed herein.
Other features will be apparent from the accompanying drawings and from the detailed description that follows.
Example embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:
Other features of the present embodiments will be apparent from the accompanying drawings and from the disclosure of the various embodiments.
A method, a circuit and/or a system of simultaneous accommodation of a low power signal and an interfering signal in a Radio Frequency (RF) receiver are disclosed. In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various embodiments. It will be evident, however to one skilled in the art that the various embodiments may be practiced without these specific details.
In one or more embodiments, each of high frequency band signal 106A and low frequency band signal 106B may have a desired signal component 104, along with an interference signal component 102. In one or more embodiments, interference signal component 102 may be an unwanted signal having a high power level, and desired signal component 104 may be a wanted signal having a power level lower than that of interference signal component 102. In an example scenario, interference signal component 102 may be at least 60 dB higher than desired signal component 104.
In one example embodiment, split-band receiver 100 may accommodate input signal 106 (A,B) carrying desired signal component 104 and interference signal component 102 simultaneously with minimized distortion to convert an analog input signal 106 (A,B) into digital data. In the scenario of interference signal component 102 being at least 60 dB higher than desired signal component 104, split-band receiver 100 (or, individual receivers thereof) may have at least 60 dB of dynamic range to accommodate both interference signal component 102 and desired signal component 104.
In one or more embodiments, image reject mixer 202 (A,B) may serve to reject interference signal component 102, thereby eliminating image noise from the unwanted sideband (or, interference signal component 102) that can pollute the noise figure of split-band receiver 100. In one or more embodiments, each of high band channel receiver 108A and low band channel receiver 108B may include an IF Variable Gain Amplifier (IF VGA 220 (A,B)) at the input (IF component side) of image reject mixer 202 (A,B) to amplify the IF component to a desired level. In one or more embodiments, the output of image reject mixer 202 (A,B) may also be amplified to an optimum level through a baseband VGA 222 (A,B). In one or more embodiments, an anti-alias Low Pass Filter (LPF) 210 (A,B) coupled to the output of image reject mixer 202 (A,B) (or, output of baseband VGA 222 (A,B)) may restrict the bandwidth of the output signal to approximately satisfy the Nyquist-Shannon sampling theorem during conversion thereof from a continuous time space into a discrete time space through an Analog-to-Digital Converter (ADC) circuit 216 (A,B).
In one or more embodiments, an AGC circuit 204 (A,B) may be located in a feedback path of the image rejection to adjust the gain of IF VGA 220 (A,B) and/or baseband VGA 222 (A,B) to an appropriate level. In other words, the output of LPF 210 (A,B) may be coupled to an input of AGC circuit 204 (A,B), whose output is then applied to IF VGA 220 (A,B).
In one or more embodiments, LO generator circuit 270 may provide clock signal(s) to RF mixer 208 (A,B), image reject mixer 202 (A,B) and/or ADC circuit 216 (A,B). In one or more embodiments, the clock signal to ADC circuit 216 (A,B) may be divided down in frequency from a higher frequency output of a Voltage Controlled Oscillator (VCO) utilized in LO generator circuit 270. Thus, in one or more embodiments, ADC clock 302 may have a lower jitter compared to the clock signal(s) to image reject mixer 202 (A,B) and/or RF mixer 208 (A,B).
VCO 318 may have lower phase noise at desired frequencies compared to the reference TCXO 312, especially at higher frequency offsets, and, therefore, a frequency divided output of VCO 318 (or, ADC clock 302) may have lower jitter compared to an output of VCO 318. Thus, in one or more embodiments, VCO 318 may be utilized in conjunction with the high resolution ADC circuit 216 (A,B) to supply LO 218 to image reject mixer 202 (A,B). Also, in one or more embodiments, the higher frequency of VCO 318 may also be divided down in frequency (e.g., through frequency divider 316) to serve as ADC clock 302 (or, ADC clock signal). Now, because the high resolution ADC circuit 216 (A,B) is utilized in conjunction therewith, the clock jitter requirement is more stringent, thereby providing for ADC clock 302 with very low jitter.
The frequencies input to image reject mixer 202 (A,B) may be split into two branches at node A, and mixed (e.g., through mixer 402 (A,B)) with quadrature phases of LO 218 to obtain sinusoidal components at nodes B and C. Thus, neglecting the high frequency components that can be filtered, the signal at each of nodes B and C may include desired signal component 104 along with interference signal component 102. The signal at node B may further be phase shifted by 90 degrees through a 90 degree phase shifter 404 (e.g., based on a passive RC polyphase network), and the output of the phase shifting (e.g., signal at node D) may be combined with the signal at node C at combiner 406. The output of combiner 406 may have interference signal component 102 canceled out, and desired signal component 104 added in phase.
In one or more embodiments, split-band receiver 100 (or, high band channel receiver 108A, low band channel receiver 108B) may especially be useful in the case of interference signal component 102 being close in frequency to desired signal component 104. Here, in one or more embodiments, the interference bandwidth may be small when interference signal component 102 is mixed down to the IF along with desired signal component 104, thereby enabling for a smaller bandwidth to account for during image rejection through image reject mixer 202 (A,B). In one or more embodiments, image reject mixer 202 (A,B) may fold interference signal component 102 and desired signal component 104 such interference signal component 102 is out-of-band with respect to desired signal component 104.
The concepts discussed above may be utilized to implement active wireless signal cancellation to protect Global Positioning System (GPS) receivers. As discussed above, in one or more embodiments, the dynamic range of split-band receiver 100 may accommodate both desired signal component 104 and interference signal component 102 at the same time. In one or more embodiments, the high dynamic range split-band receiver 100 and ADC circuit 216 (A,B) may allow for low level desired signals and high level interfering signals to be processed at the same time. In
Even if image reject mixer 202 (A,B) does not provide for complete cancellation of interference signal component 102, the output level of interference signal component 102 may be reduced by 40 dB in an example embodiment by placing the potential interferer (or, interference signal component 102) at the image frequency location of image reject mixer 202 (A,B).
Exemplary embodiments also serve as a basis for in-band wireless cancellation consisting of sampling an interference source as an input and filtering the sampled signal to emulate and subsequently remove the incurred interference on the received victim signal. Here, the sampled noise signal may be acquired from a noise sampler that taps into the interference source. The cancellation involves feeding the sampled interference source through an emulated coupling channel. The chip architecture therefor may include an active bandpass filter, a Vector Modulator (VM) and a controller. The active bandpass filter may sample the interfering signal that falls within a GPS receiver band. The VM may provide phase shift and attenuation to tune out the sampled interference at an injection point.
In one or more embodiments, ADC circuit 216 (A,B) may have a high resolution (e.g., 12 bit) to ensure that low level desired signals and high level unwanted interference signals are processed at the same time. In one or more embodiments, interference signal component 102 may be suppressed by utilizing knowledge of occurrence thereof. In other words, through knowing exactly where interference is going to occur, interference signal component 102 may be aligned with the image frequency location of image reject mixer 202 (A,B).
It is obvious that filters may be utilized to filter unwanted components of the mixing processes and other processes disclosed herein. Omission of one or more filters at appropriate positions in
In one or more embodiments, split-band receiver 100 discussed with regard to
In one or more embodiments, the high dynamic range of split-band receiver 100 may be achieved by implementing ADC circuit 216 (A,B) in a high gain/low-noise system (e.g., split-band receiver 100) with other circuitry. In one or more example embodiments, ADC circuit 216 (A,B) may be sampling at a frequency having harmonics thereof that do not interfere with high frequency band signal 106A (or, channel) and low frequency band signal 106B (or, channel). Thus, by design, spurs may be absent within a data bandwidth of split-band receiver 100 (or, high band channel receiver 108A, low band channel receiver 108B). As discussed above, ADC circuit 216 (A,B) may have high resolution enough to accommodate desired signals and interference signals simultaneously. In order for ADC circuit 216 (A,B) to function properly, electronics in split-band receiver 100 (or, high band channel receiver 108A, low band channel receiver 108B) may need to be linear.
In one example embodiment, as discussed above, through the utilization of a highly linear front end of split-band receiver 100 (or, high band channel receiver 108A, low band channel receiver 108B) and a high ENOB ADC circuit 216 (A,B), the entire receiver chain of split-band receiver 100 may have over 60 dB of dynamic range. In embodiments related to reduced power applications not requiring high dynamic range, a 3 bit ADC may be used instead of the 12 bit ADC example mentioned above.
In one or more embodiments, input signal 106 may include desired signal component 104 and interference signal component 102. In one or more embodiments, interference signal component 102 may have a higher power level than desired signal component 104. In one or more embodiments, operation 708 may then include simultaneously accommodating desired signal component 104 and interference signal component 102 in the RF receiver based on an increased dynamic range of the RF receiver and the high ENOB ADC circuit provided through the highly linear front end and the high ENOB ADC circuit.
In one or more embodiments, operation 804 may then include selecting an image frequency of image reject mixer 202 (A,B) to coincide with a frequency of interference signal component 102 to enable cancellation thereof through image reject mixer 202 (A,B) while having a capability to receive desired signal component 104.
In one or more embodiments, operation 906 may then include providing a clock signal to the high ENOB ADC circuit divided down in frequency from the output of VCO 318 providing the local oscillator reference signal to image reject mixer 202 (A,B) to reduce a jitter thereof.
Although the present embodiments has been described with reference to specific example embodiments, it will be evident that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the various embodiments. For example, the various devices, modules, analyzers, generators, etc. described herein may be enabled and operated using hardware circuitry (e.g., CMOS based logic circuitry), firmware, software and/or any combination of hardware, firmware, and/or software (e.g., embodied in a machine readable medium).
In addition, it will be appreciated that the various operations, processes, and methods disclosed herein may be embodied in a machine-readable medium and/or a machine accessible medium compatible with a data processing system (e.g., a computer system), and may be performed in any order (e.g., including using means for achieving the various operations). Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.
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20140030981 A1 | Jan 2014 | US |