Simultaneous multi-threading control monitor

Information

  • Patent Grant
  • 7559061
  • Patent Number
    7,559,061
  • Date Filed
    Sunday, March 16, 2008
    17 years ago
  • Date Issued
    Tuesday, July 7, 2009
    15 years ago
Abstract
One example would provide for maximum throughput thus increasing capacity during times when only low and medium priority work is running while allowing for the shorter turn around times required by critical work. Moreover, it creates a “SMT Control Monitor” (SCM) which would examine the type of work running on the machine. This monitor would turn ON/OFF SMT feature, and suspend/resume job threads as the work load demanded. This idea is different than other SMT control disclosures because it incorporates information from the batch system. This additional information will be used to better manage the state of SMT and the job threads.
Description
BACKGROUND OF THE INVENTION

Simultaneous multithreading is a processor design that combines hardware multithreading with superscalar processor technology to allow multiple threads to issue instructions each cycle. Unlike other hardware multithreaded architectures, in which only a single hardware context (i.e., thread) is active on any given cycle, SMT permits all thread contexts to simultaneously compete for and share processor resources. Unlike conventional superscalar processors, which suffer from a lack of per-thread instruction-level parallelism, simultaneous multithreading uses multiple threads to compensate for low single-thread. The performance consequence is significantly higher instruction throughput and program speedups on a variety of workloads


The IBM/R6000 Power 5 and 6 architectures support running multiple threads on a single processor. This is possible because of the “Simultaneous Multi-Threading” (SMT) processor design. SMT enables several process threads to coexist on a single physical processor at one time. This technology maximizes the use of otherwise unused processor cycles increasing the overall work throughput (TPT) of the processor.


SUMMARY OF THE INVENTION

One embodiment would provide for maximum throughput thus increasing capacity during times when only low and medium priority work is running while allowing for the shorter turn around times required by critical work. While this idea targets the IBM/R6000 Power 5 and 6 architectures, it could be easily extended to other multi-threading architectures provided the target architecture has a mechanism for dynamically disabling and enabling multi-threading on the system.


One embodiment is to create a “SMT Control Monitor” (SCM) which would examine the type of work running on the machine. This monitor would turn ON/OFF SMT feature, and suspend/resume job threads as the work load demanded. This idea is different than other SMT control disclosures because it incorporates information from the batch system. This additional information will be used to better manage the state of SMT and the job threads.





BRIEF DESCRIPTION OF THE DRAWINGS


FIG. 1 is a chart average number of jobs competed within 24 hours on a 2 way Power 5 system



FIG. 2 is a chart showing the average TAT for the jobs competed on a 2way Power 5 system



FIG. 3 shows how the SCM would control the batch job threads





DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

To maximize the use of SMT, it is desirable to fully saturate the available threads. This is done by turning SMT ON, and scheduling multiple threads for each physical processor. This increases the total number of jobs completed over time at the expense of the individual job turn around time (TAT). A solution is needed to ensure the time sensitive critical work gets the shortest possible turn around time while still increasing the overall capacity by enabling SMT.


The chart in FIG. 1 shows the average number of jobs competed within 24 hours on a 2 way Power 5 system. The first bar shows SMT OFF, and running 2 job threads and the second shows SMT ON, and running 4 job threads. This shows turning on SMT increased the capacity by 35%.


The chart in FIG. 2 shows the average TAT for the jobs competed on a 2way Power 5 system. The first bar shows SMT OFF, and running 2 job threads and the second shows SMT ON, and running 4 job threads. Turning on SMT increased the elapsed time needed to run jobs by 48%.



FIG. 3 shows how the SCM would control the batch job threads for the jobs running on the machine. When it detects the presence of threads running under a high priority job queue (300), SMT would be turned off (305), and the suspendable job threads suspended (310) back to a processor load equal to the number of physical processors. When the high priority job threads are not present, SMT would be turned back on, and the suspendable job threads would be resumed (320) bringing the processor load back up. The processor load is defined as the number of threads allowed to be active at any point in time.


Table 1, shows how systems would be configured to run multiple low priority suspendable threads (usually 2) for each physical processor and either 1 non-suspendable med or 1 high priority job thread for each processor. This table shows a maximum processor load of 4 with SMT turned on and a processor load of 2 with SMT turned off.









TABLE 1







Power5—2 physical processors












Job Queues
Threads
Desired Load
Desired Load



(by priority)
Configured
w/SMT OFF
w/SMT ON







Low
4
2—note 2
4



Med
2—note 1
2
4



High
2—note 1
2
NA—note 3







note 1: the total number of combined med and high priority threads should never exceed the number of physical processors, in this case 2.



note 2: 2 of the low priority threads would be suspended.



note 3: SMT would not be on, when high priority job threads are present.






Table 2 shows how the different job queues would control SMT and react to one another. Unless a high priority job is present, the low and med priority job queues would normally run with SMT on and maintain high processor loads. The presence of a high priority queue would cause SMT to be turned off, and the processor load levels dropped to a level equal to the number of physical processors. Low priority jobs would be suspended back to the processor load levels indicated for SMT off.













TABLE 2







Job Queues
SMT State
Suspendable









Low
on unless high present
yes



Med
on unless high present
no



High
off
no










In summary the combination of toggling SMT and suspending and resuming job threads maximizes both throughput and turn around time as demanded by the jobs active on the machine. This idea allows for a higher level of throughput efficiency/capacity while still accommodating the critical work demands for shorter turn around times because it understands the importance of the work being preformed on the system.


An embodiment of the invention is a method for maximizing throughput and minimizing job turn-around-time in a multi-processing multi-threading system, the system comprises of one or more physical processors, dynamically enabling and disabling simultaneous multi-threading control. The method is comprised of the following steps:

    • The system monitors priority of all jobs executing, in which a first job among the jobs is a job executing on the one or more physical processors of the multi-processing multi-threading system and low priority job type is suspendable, medium priority job type is unsuspendable, and high priority job type is unsuspendable and has a higher priority than that of the medium priority job type.
    • If the first type is the high priority job type, then the system turns off the simultaneous multi-threading control of the multi-processing multi-threading system and suspends excess low priority suspendable jobs. The number of the excess low priority suspendable jobs is total number of the one or more physical processors, less total number of unsuspendable jobs, minus one.
    • Otherwise, the system turns on the simultaneous multi-threading control of the multi-processing multi-threading system and the resumption of low priority suspendable jobs.


A system, apparatus, or device comprising one of the following items is an example of the invention: multiprocessor, processor, multi-thread, jobs, prioritizing module, applying the method mentioned above, for the purpose of multithreading and management.


Any variations of the above teaching are also intended to be covered by this patent application.

Claims
  • 1. A method for maximizing throughput and minimizing job turn-around-time in a multi-processing multi-threading system, said system comprising one or more physical processors, said system dynamically enabling and disabling simultaneous multi-threading control in the one or more physical processors, said method comprising: monitoring priority of all jobs executing, wherein a first job among said all jobs is a job executing on said one or more physical processors of said multi-processing multi-threading system;wherein low priority job type is suspendable;wherein medium priority job type is unsuspendable;wherein high priority job type is unsuspendable and has a higher priority than that of said medium priority job type;if said first job is said high priority job type: setting said simultaneous multi-threading control of said multi-processing multi-threading system as off-state, limiting total number of said medium priority job type and said high priority job type to the number of said one or more physical processors, andsuspending a number of low priority suspendable jobs,wherein the total number of high priority job, medium priority job and low priority jobs are not greater than the number of said one or more physical processors;else: setting said simultaneous multi-threading control of said multi-processing multi-threading system as on-state,limiting total number of said medium priority job type and said high priority job type to the number of said one or more physical processors, andallowing execution of additional low priority suspendable jobs simultaneously with said medium priority jobs and said high priority jobs.
US Referenced Citations (18)
Number Name Date Kind
4901230 Chen et al. Feb 1990 A
6076157 Borkenhagen et al. Jun 2000 A
6651158 Burns et al. Nov 2003 B2
7155600 Burky et al. Dec 2006 B2
7254697 Bishop et al. Aug 2007 B2
20040215932 Burky et al. Oct 2004 A1
20040215939 Armstrong et al. Oct 2004 A1
20040216113 Armstrong et al. Oct 2004 A1
20040216120 Burky et al. Oct 2004 A1
20050223199 Grochowski et al. Oct 2005 A1
20060085368 Moilanen et al. Apr 2006 A1
20060136915 Aingaran et al. Jun 2006 A1
20060184768 Bishop et al. Aug 2006 A1
20060242389 Browning et al. Oct 2006 A1
20070200227 Licht et al. Aug 2007 A1
20080134180 Floyd Jun 2008 A1
20080177682 Moilanen et al. Jul 2008 A1
20080263325 Kudva et al. Oct 2008 A1
Foreign Referenced Citations (3)
Number Date Country
1029269 Sep 2003 EP
WO00146827 Jun 2001 WO
WO2006083543 Aug 2006 WO