Bursky, Dave, "Combination DRAM-SRAM Removes Secondary Caches.," Electronic Design, V40, N2, P39(4). |
Gwennap, Linley and Scherer, Alisa, "IC Manufacturing Drives CPU Performance; Don't Be Misled . . . ," Microprocessor Report, V7, N7; P 15(5). |
Levison, Jacob and Kuroda, Ichiro, "An Asynchronous Communication Protocol for Internode Connections in a Scalable Processor Array," VLSI Signal Processing VI, 1993. |
Tredennick, Nick, "Computer Science and the Microprocessor: The Battle for the Desktop," Dr. Dobb's Journal, V18, N6, P18(6). |
RAMTRON Application Note, "Applying the Enhanced DRAM to 386/486DX Computers," R1 040192, pp1-12. |
Lenoski, Daniel, et al., "The Stanford Dash Multiprocessor", Computer, Mar. 1992. |
Koza, John, Genetic Programming, MIT Press, Cambridge, MA 1993, pp. 94-101 and 173. |
Nowatzyk, A. and Parkin, M., "The S3.MP Interconnect System & TIC Chip", Proceedings of IEEE Computer Society Hot Interconnect Symposium, Stanford Univ., 1993. |
"Wolverines: Standard Cell Placement on a Network of Workstations,"S. Mohan and Pinaki Mazumder, IEEE Transactions on Computer-Aided Design . . . , vol. 12, No. 9, Sep. 1993. |
"Algorithms for VLSI Physical Design Automation, " Naveed A. Sherwani, Western Michigan University, .COPYRGT.1993. |
"KSRI," Kendall Square Research Techinical Summary, .COPYRGT.1992. |
Sechen, Carl and Sangiovanni-Vincentelli, Alberto, "Timberwolf 3.2: A New Standard Cell Placement and Global Routing Package", IEEE 23rd Design Automation Conference, 1986, Paper 26.1. |
Shahookar, Skushro and Mazumder, Pinaki, "A Genetic Approach to Standard Cell Placement Using Metagenetic Parameter Optimization", IEEE Transactions on Computer Aided Design, vol. 9, No. 5, May 1990. |