Single-ended input to differential-ended output low noise amplifier

Abstract

A single-ended input to differential-ended output amplifier circuit comprises an amplifier for amplifying an input signal into an amplified signal comprises an input for receiving the input signal; and a first input and a single-ended input to differential-ended output conversion circuit to convert the amplified signal to a differential signal pair, comprising a first transistor for receiving the amplified signal having a first gate coupled to the first output, a first first terminal coupled to a second output, and a first second terminal coupled to a first node; a second transistor having a second gate, a second first terminal coupled to a third input, and a second second terminal coupled to the first node; a second capacitor coupled between the second output and the second gate; a first and a second resistors and the voltage source; and a current source coupled between the first node and a ground.

Description

BRIEF DESCRIPTION OF DRAWINGS

The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1 is a conventional single-ended input to differential-ended output amplifier circuit.

FIG. 2 is a conventional single-ended input to differential-ended output amplifier circuit.

FIG. 3A is a conventional single-ended input to differential-ended output amplifier circuit.

FIG. 3B is conventional differential amplifier pair circuit with grounded negative terminal.

FIG. 4A is a single-ended input to differential-ended output amplifier circuit according to an embodiment of the invention.

FIG. 4B is a single-ended to differential-ended conversion circuit according to an embodiment of the invention.

FIG. 5 is a circuit of single-ended input to single-ended output cascade low-noise amplifier according to an embodiment of the invention.

Claims

1. A single-ended input to differential-ended output amplifier circuit, comprising: an amplifier for amplifying an input signal into an amplified signal, comprising: an input end for receiving the input signal; anda first output end; anda single-ended input to differential-ended output conversion circuit to convert the amplified signal to a differential signal pair, comprising: a first transistor for receiving the amplified signal having a first gate coupled to the first output end, a first first terminal coupled to a second output end, and a first second terminal coupled to a first node;a second transistor having a second gate, a second first terminal coupled to a third input, and a second second terminal coupled to the first node;a second capacitor coupled between the second output and the second gate;a first resistor coupled between the second output and a voltage source;a second resistor coupled between the third output and the voltage source; anda current source coupled between the first node and a ground.

2. The single-ended input to differential-ended output amplifier circuit as claimed in claim 1, further comprising an antenna for receiving the input signal.

3. The single-ended input to differential-ended output amplifier circuit as claimed in claim 2, wherein the antenna is a single-ended antenna.

4. The single-ended input to differential-ended output amplifier circuit as claimed in claim 1, wherein the input signal is a radio frequency signal.

5. The single-ended input to differential-ended output amplifier circuit as claimed in claim 1, further comprising a first capacitor coupled between the first output and the single-ended input to differential-ended output conversion circuit.

6. The single-ended input to differential-ended output amplifier circuit as claimed in claim 1, wherein the amplifier is a single-ended input to single-ended output amplifier.

7. The single-ended input to differential-ended output amplifier circuit as claimed in claim 6, wherein the amplifier is a low noise amplifier.

8. The single-ended input to differential-ended output amplifier circuit as claimed in claim 7, wherein the amplifier is a cascade amplifier.

9. The single-ended input to differential-ended output amplifier circuit as claimed in claim 8, wherein the amplifier comprises: a first inductor coupled to the input end;a fifth capacitor coupled between the first inductor and a second node;a second inductor coupled between the voltage source and the first output end;a third transistor having a third gate coupled to the second node, a third first terminal coupled to the first output, and a third second terminal; anda third inductor coupled between the third second terminal and the ground.

10. The single-ended input to differential-ended output amplifier circuit as claimed in claim 9, wherein the amplifier further comprises a fourth transistor coupled between the first output end and the third first terminal of the third transistor, and a fourth gate coupled to the voltage source.

11. The single-ended input to differential-ended output amplifier circuit as claimed in claim 9, wherein the amplifier further comprises a bias source to provide a bias to the second node.

12. The single-ended input to differential-ended output amplifier circuit as claimed in claim 11, wherein the amplifier further comprises a third resistor coupled between the bias source and the second node.

13. The single-ended input to differential-ended output amplifier circuit as claimed in claim 1, wherein the output signal at the second output end and the third output end is a low noise figure and high gain signal.

14. The single-ended input to differential-ended output amplifier circuit as claimed in claim 1, wherein the second output end and the third output end is coupled to a first signal input terminal of an image-rejection mixer and a second signal input terminal, respectively.

15. The single-ended input to differential-ended output amplifier circuit as claimed in claim 14, further comprising: a third capacitor coupled between the second output end and the first signal input terminal; anda fourth capacitor coupled between the third output end and the second signal input terminal.

16. A signal processing circuit, comprising: an amplifier for amplifying an amplified signal into an input signal, comprising: an input end for receiving the input signal; anda first output end;a single-ended input to differential-ended output conversion circuit for amplifying the amplified signal into a differential signal pair, comprising: a first transistor for receiving the amplified signal having a first gate coupled to the first input end, a first first terminal coupled to a second output end, and a first second terminal coupled to a first node;a second transistor having a second gate, a second first terminal coupled to a third output end, and a second second terminal coupled to the first node;a second capacitor coupled between the second output end and the second gate;a first resistor coupled between the second output end and a voltage source;a second resistor coupled between the third output end and the voltage source; anda current source coupled between the first node and a ground; and an image-rejection mixer, comprising:a first signal input terminal coupled to the second output end; anda second signal input terminal coupled to the third output end.

17. The signal processing circuit as claimed in claim 16, further comprising an antenna for receiving the input signal.

18. The signal processing circuit as claimed in claim 17, wherein the antenna is a single-ended antenna.

19. The signal processing circuit as claimed in claim 16, wherein the input signal is a radio frequency signal.

20. The signal processing circuit as claimed in claim 16, further comprising a first capacitor coupled between the first output end and the single-ended input to differential-ended output conversion circuit.

21. The signal processing circuit as claimed in claim 16, wherein the amplifier is a single-ended input to single-ended output amplifier.

22. The signal processing circuit as claimed in claim 21, wherein the amplifier is a low noise amplifier.

23. The signal processing circuit as claimed in claim 22, wherein the amplifier is a cascade amplifier.

24. The signal processing circuit as claimed in claim 23, wherein the amplifier comprising: a first inductor coupled to the input end;a fifth capacitor coupled between the first inductor and a second node;a second inductor coupled between the voltage source and the first output end;a third transistor having a third gate coupled to the second node, a third first terminal coupled to the first output end, and a third second terminal; anda third inductor coupled between the third second terminal and the ground.

25. The signal processing circuit as claimed in claim 24, wherein the amplifier further comprises a fourth transistor coupled between the first output end and the third first terminal of the third transistor, and a fourth gate coupled to the voltage source.

26. The signal processing circuit as claimed in claim 24, wherein the amplifier further comprises a bias source to provide a bias to the second node.

27. The signal processing circuit as claimed in claim 26, wherein the amplifier further comprises a third resistor coupled between the bias source and the second node.

28. The signal processing circuit as claimed in claim 16, wherein the output signal at the second output end and the third output end is a low noise figure and high gain signal.

29. The signal processing circuit as claimed in claim 24, further comprising: a third capacitor coupled between the second output end and the first signal input terminal; anda fourth capacitor coupled between the third output end and the second signal input terminal.