The present disclosure relates to data processing, and more specifically, to methods, systems and computer program products for single-hop two-phase transaction resolution.
Distributed Transaction Processing Monitor products (TPMs) are implemented using different software architectures to suit the services provided as well as the execution platforms. In process-based TPMs, transactions use operating system processes to run a logical unit of work (LUW). An LUW includes a sequence of operations that are acted upon as a single group that is collectively committed or rolled back (i.e., undone) together.
It is a common scenario to have a transaction span across multiple TPMs connected through traditional proprietary protocols. A TPM can act as a transaction coordinator and use a two-phase commit process to ensure data consistency with the recoverable resources associated with the transaction. When there is more than one TPM involved in an LUW, the TPM that initiates the transaction assumes the responsibility of a coordinator and the other TPMs act as participants. The coordinating TPM usually controls the final resolution of a transaction that spans across multiple TPMs and resource managers connected to participant TPMs.
As the number of transactional processing systems involved in an LUW increases, the time taken for transaction resolution and transaction recovery will increase. Every TPM usually treats the requester TPM as the coordinator in a synchronously processed transaction. When the TPM coordinator issues a PREPARE, COMMIT, or ROLLBACK operation command during transaction resolution, every TPM involved in the LUW has to prepare for transaction resolution with its participants. Transaction participants can be either a resource manager or any other interconnected TPM. Similarly, if any intermediate TPM fails or crashes in a chain of TPMs, recovery should happen at every TPM involved in the LUW. A crash in an intermediate TPM handling a transaction can even result in some further TPMs waiting for its coordinator response indefinitely.
In accordance with an embodiment, a method for single-hop two-phase transaction resolution is provided. The method may include determining, by a coordinator transaction processing monitor, a transaction coordinator identifier associated with a transaction that spans a plurality of transaction processing monitors distributed between a plurality of transaction processing systems. The coordinator transaction processing monitor attaches the transaction coordinator identifier as part of a transaction request of an application flow of the transaction. The transaction request from the coordinator transaction processing monitor is transmitted to a next transaction processing monitor to sequentially propagate through the transaction processing monitors. A response from the next transaction processing monitor is received. The response includes a transaction resolution endpoint identifier for each of the transaction processing monitors participating in the transaction. A plurality of transaction resolution calls of a transaction resolution flow of the transaction is sent in parallel from the coordinator transaction processing monitor to the transaction processing monitors participating in the transaction as identified based on the transaction resolution endpoint identifier of each of the transaction processing monitors participating in the transaction.
In another embodiment, a system may include a memory having computer readable instructions and a processor for executing the computer readable instructions. The computer readable instructions can include determining, by a coordinator transaction processing monitor, a transaction coordinator identifier associated with a transaction that spans a plurality of transaction processing monitors distributed between a plurality of transaction processing systems. The computer readable instructions can also include attaching, by the coordinator transaction processing monitor, the transaction coordinator identifier as part of a transaction request of an application flow of the transaction and transmitting the transaction request from the coordinator transaction processing monitor to a next transaction processing monitor to sequentially propagate through the transaction processing monitors. A response can be received from the next transaction processing monitor. The response can include a transaction resolution endpoint identifier for each of the transaction processing monitors participating in the transaction. The computer readable instructions can further include sending a plurality of transaction resolution calls of a transaction resolution flow of the transaction in parallel from the coordinator transaction processing monitor to the transaction processing monitors participating in the transaction as identified based on the transaction resolution endpoint identifier of each of the transaction processing monitors participating in the transaction.
In another embodiment, a computer program product may include a computer readable storage medium having program instructions embodied therewith. The program instructions executable by a processor to cause the processor to perform determining, by a coordinator transaction processing monitor, a transaction coordinator identifier associated with a transaction that spans a plurality of transaction processing monitors distributed between a plurality of transaction processing systems. The coordinator transaction processing monitor attaches the transaction coordinator identifier as part of a transaction request of an application flow of the transaction. The transaction request from the coordinator transaction processing monitor is transmitted to a next transaction processing monitor to sequentially propagate through the transaction processing monitors. A response from the next transaction processing monitor is received. The response includes a transaction resolution endpoint identifier for each of the transaction processing monitors participating in the transaction. A plurality of transaction resolution calls of a transaction resolution flow of the transaction is sent in parallel from the coordinator transaction processing monitor to the transaction processing monitors participating in the transaction as identified based on the transaction resolution endpoint identifier of each of the transaction processing monitors participating in the transaction.
The forgoing and other features, and advantages of the disclosure are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
In accordance with exemplary embodiments of the disclosure, methods, systems and computer program products for single-hop two-phase transaction resolution are provided. The systems and methods described herein are directed to reducing the complexity of transaction resolution by reorganizing a synchronization point flow pattern in a network of serially interconnected transaction processing monitors (TPMs) spanning across multiple levels. A transaction recovery resolution flow can be sped up in case of a TPM participant failure in a network of interconnected TPMs. The methods and systems described herein can also track all the participating TPMs during transaction execution and dynamically arrive at the transaction resolution flow.
In a transaction that is spans across multiple TPMs, the transaction execution may include of two types of flows across TPMs. The first type of flow is an application request flow, and the second type of flow is a transaction resolution flow. In the methods and systems described herein, during the application request flow, the coordinator TPM associates its information with a transaction coordinator identifier, such as a coordinator indication flag, as a part of the transaction request (e.g., within a transaction request payload) when it routes the request to the next TPM. Branch TPMs that participate in the transaction can each attach transaction resolution endpoint details including a transaction identifier (XID) branch ID used for dynamic registrations as part of a response, for instance, in a response payload. Preceding TPMs can read the transaction resolution endpoint details including the XID branch ID used for dynamic extended architecture (XA) registrations from all subsequent TPMs, and each participating TPM attaches the information in its response payload to its preceding TPM. This flow continues until the response reaches back to the TPM coordinator. In embodiments, the TPM coordinator collects information about all the TPM participants involved in the transaction, which may not be known to the TPM coordinator prior to transmitting the application request flow. Using this data, the TPM coordinator directly contacts the participating TPMs in parallel for the transaction resolution flow. Though the participating TPMs exist at multiple levels in different transaction branches of a global transaction, the TPM coordinator can treat all the TPMs as its direct participant TPM and send the transaction resolution calls in parallel to all the TPMs using the transaction resolution endpoint details and XID branch ID collected from the response payload during application flow. This method enables quicker transaction resolution compared to traditional transactional resolution and thereby improves networked system performance.
In some embodiments, the technical advantages for the systems and methods described herein include the knowledge of the TPM coordinator of all the TPMs involved in the global transaction, which helps the TPM coordinator facilitate a more efficient transaction resolution. The TPM coordinator's centralized transaction resolution reduces the possibility of transactions getting stuck indefinitely when a TPM goes down during resolution. The TPM coordinator can send the resolution calls in parallel to all participating TPMs. The resolution happens quicker compared to traditional methods, and resources are released sooner. The TPM coordinator may recognize participant failures much earlier, which enables it to process transaction resolution procedures to other TPM participants involved in the transaction.
In exemplary embodiments, the processing system 100 includes a graphics-processing unit 130. Graphics processing unit 130 is a specialized electronic circuit designed to manipulate and alter memory to accelerate the creation of images in a frame buffer intended for output to a display. In general, graphics-processing unit 130 is very efficient at manipulating computer graphics and image processing, and has a highly parallel structure that makes it more effective than general-purpose CPUs for algorithms where processing of large blocks of data is done in parallel.
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The transaction coordinator identifier can include a transaction coordinator endpoint address and a coordinator indication flag. The transaction resolution endpoint identifier of each of the TPMs 205B-F participating in the transaction can include a branch identifier that is unique to one of the TPMs 205B-F. The transaction resolution endpoint identifier of each of the TPMs 205B-F participating in the transaction can include a transaction resolution endpoint address. The response can include a global transaction identifier shared by all of the TPMs 205B-F participating in the transaction. An endpoint address of fewer than all of the TPMs 205B-F participating in the transaction may be known by the coordinator TPM 205A prior to transmitting the transaction request during the application flow of the transaction.
The coordinator TPM 205A can determine a next coordinated operation to be performed by each of the TPMs 205B-F participating in the transaction based on the response. A commit operation can be issued from the coordinator TPM 205A in parallel to all of the TPMs 205B-F participating in the transaction based on determining that all of the TPMs 205B-F participating in the transaction are ready to commit as depicted in the example of
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
The present invention may be a system, a method, and/or a computer program product at any possible technical detail level of integration. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention.
The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.
Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network. The network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. A network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device.
Computer readable program instructions for carrying out operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuitry, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++, or the like, and procedural programming languages, such as the “C” programming language or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention.
Aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions.
These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks.
The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the Figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.