Protocol analyzers are used to monitor and analyze the traffic across an optical network, as well as to troubleshoot and debug the components within the optical network. Most protocol analyzers developed and installed today have optical communication interfaces that are designed for a single optical communication standard. However, many different optical communication standards exist for optical networks, and within each standard may be several different data rates and wavelengths of light used.
Therefore, what is needed is an optical communication interface that is capable of operating across multiple optical communication standards, and multiple data rates.
Table 1 is a table of selected optical interface standards, their raw bit rates, and associated clock frequencies:
In the present application, the following terms are used with the indicated definition. A frequency Y is a “harmonic” of a frequency X when Y is a integral multiple of X. For example, 250 KiloHertz (KHz) is a harmonic of 50 KHz, because 5*(50 KHz)=250 KHz. A frequency Y is a “binary harmonic” of a frequency X when Y=X*2N, where N is a positive integer. For example, 200 MegaHertz (MHz) is a binary harmonic of 50 MHz, because 200 MHz=(50 MHz)*22.
The CDR block 10 utilizes a phase-locked-loop (PLL) (not shown) to recover the embedded clock (which runs at the same frequency as the raw bit rate) from the electrical signal 8, and generates a LOCK signal once it has successfully recovered the embedded clock. The LOCK signal is an output from the PLL circuit within a CDR indicating that it has phase-locked the raw bit rate of the incoming signal to a harmonic of the applied reference frequency, as modified by its internal divisors. This LOCK signal represents the first level (physical layer) of optical signal standards identification. Beyond this LOCK signal all interfaces in the industry include verification from the media access layer (MAC layer) where special symbols, bit patterns, or a framing pulses specific to each standard, are used to further identify a communication standard before the data can be used. The CDR block 10 should be capable of clock and data recovery across multiple standards. One example of a suitable CDR block 10 is the VSC8142 Multi-Rate Transceiver, offered by Vitesse Semiconductor Corporation. Other satisfactory CDR blocks are commercially available.
The PLL in the CDR block 10 requires a reference frequency (REF_FREQ), operating at the same (or close to the same) frequency as the embedded clock it needs to recover. It should be noted that the reference frequency does not have to be exactly the same as the embedded clock for the PLL to lock to the incoming data signal. Some margin of error is allowed—the exact amount of error tolerated will depend on the actual CDR block 10 used. Generally, a reference frequency that is within +/−100 parts per million of the embedded clock is sufficient. For example, the REF_FREQ for Gigabit Ethernet 2× should be 2.5 Gigahertz, +/−250 Kilohertz (KHz). A frequency selector 14 receives the signal SD from the optical receiver 4, the LOCK signal from the CDR block 10, and provides REF_FREQ to the CDR block 10.
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The controller 16 (described in more detail below) receives the signal SD from the optical receiver 4 and the signal LOCK from the CDR block 10 as input. The controller 16 generates a signal FREQ_SELECT to control a mux 20, which selects one of the N primary frequency sources (F1-Fn) to provide as input 22 to the frequency synthesizer 18. The controller 16 also generates an optional signal DATA_RATE, which is passed to the CDR block 10 and selects the data rate used within a selected communication standard. Finally, the signal SYNTH_SELECT from the controller 16 controls the factor by which the frequency synthesizer 18 multiplies its input 22 to get the REF_FREQ.
The frequency synthesizer 18 takes the selected primary frequency source 22 as input, scales it by a factor controlled by SYNTH_SELECT, and produces a REF_FREQ with low jitter. A suitable frequency synthesizer 18 is the ICS843001-22, offered by Integrated Circuit Systems, Inc. Other satisfactory frequency synthesizers are commercially available.
Further multiplication of the signal REF_FREQ may be performed internally by the CDR block 10 to accommodate multiple data rates within a standard. The internal multiplication factor is controlled by the optional signal DATA_RATE provided by the frequency selector 14. Alternatively, if the primary frequency sources F1-Fn are chosen to generate the desired final signal REF_FREQ without any further mathematical manipulation, the frequency synthesizer 18 and the signal DATA_RATE can be omitted from the frequency selector 14.
There are many different optical communication standards in existence, all operating at different bit rates and requiring different reference frequencies for clock recovery to be performed properly. Table 1 below is a table of selected optical communication standards, the coding schemes used, their raw bit rates, and exemplary primary frequency sources that may be used to generate REF_FREQ.
Each optical communication standard (e.g. Synchronous Optical Network (SONET), Gigabit Ethernet, Fibre Channel, and Fast Ethernet) is associated with a single primary frequency source that will be used to generate REF_FREQ for that standard. Many of these standards have variants that run at different raw bit rates, with optical signals having different wavelengths (820 nm to 1600 nm), and different types of light sources (e.g. light emitting diodes, lasers). Many communication standards have duplicate specifications regarding light sources and wavelengths, and how they are coupled to different optical fiber types (e.g. single-mode fibers and multi-mode fibers).
Generally, each primary frequency source is a crystal oscillator. The frequency of the crystal oscillator is chosen so that the raw bit rate of its associated communication standard is a harmonic of the crystal oscillator's frequency. Typically the raw bit rate of a communication standard is also a binary harmonic of its associated primary frequency source. (However, there are some exceptions, e.g. 10 Gigabit Ethernet which uses a primary frequency source that is 1/528 of its raw bit rate.) For example, in Table 1, SONET/SDH is associated with a primary frequency source of 19.44 MegaHertz (MHz). There are several different bit rates specified within SONET/SDH, all of which are binary harmonics of the primary frequency source: The variant OC-3 has a raw bit rate of 155.52 Megabits/second (Mb/s), which is 23 times the primary frequency source (8*19.44 MHz); OC-12 has a raw bit rate of 622.08 Mb/s, which is 25 times the primary frequency source (32*19.44 MHz); and OC-48 has a raw bit rate of 2.48832 Gb/s, which is 27 times the primary frequency source (128*19.44 MHz).
Note that the primary frequency sources shown in Table 1 are exemplary only; there are many other suitable choices for the frequencies of the primary frequency sources F1-Fn, given the various mathematical operations that can be performed on a primary frequency source Fn by the frequency synthesizer 18 to create the desired REF_FREQ, and given the margin of error allowed for the reference frequency. For example, integer multiples of the primary frequency sources listed in Table 1 would also make suitable primary frequency sources.
If the CDR block 10 performs its own internal multiplication to accommodate multiple data rates within a standard, it needs a reference frequency (REF_FREQ) as well as the proper data rate to recover the embedded clock. Without a reference frequency, a PLL becomes much more dependent on the coding scheme used and as such can falsely lock to a date rate that is a binary harmonic of the desired rate, or fail to in distinguish between SONET/SDH OC-48 (2.48832 Gb/s) and Gigabit Ethernet 2× (2.50 Gb/sec). An additional advantage to designing with reference frequencies is the ability to transmit with a specific data rate without having an input signal available to lock to.
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Next, the controller 16 steps through all variations on the selected primary frequency source 22 and REF_FREQ (step 28). For example, if the CDR block 10 scales REF_FREQ internally to accommodate multiple data rates, the controller 16 should step through the possible data rates (via the DATA_RATE signal) for the communication standard associated with the selected primary frequency source 22. Or, if the scaling of the selected primary frequency source 22 is performed by the frequency synthesizer 18, then the controller 16 should step through the possible frequency synthesizer values (via the SYNTH_SELECT signals). It is possible that the controller 16 will need to vary both DATA_RATE and SYNTH_SELECT. The controller 16 should continue trying the variations until either a LOCK signal is received (step 30), or all of the possible variations have been tried (step 32).
If the LOCK signal is received, then the CDR block 10 successfully recovered the embedded data clock using the selected primary frequency source 22, DATA_RATE, and SYNTH_SELECT (step 34). The amount of time the controller 16 should wait for a LOCK signal is dependent upon the type of CDR block 10 used. Generally, the wait time should be longer than the amount of time it takes for the CDR block 10 to generate a LOCK signal.
If no LOCK signal is detected after a reasonable interval, the controller 16 determines if all of the variations have been tried for the selected primary frequency source (step 32). If there are untried variations remaining for the selected primary frequency source, then the controller 16 returns to step 28 and continues trying the remaining variations as long as SIGNAL DETECT (SD) is asserted. If all of the variations have been tried for the selected primary frequency source, then the controller 16 selects the next primary frequency source (step 36) and returns to step 28 to cycle through the variations for the newly selected primary frequency source.
The controller 16 continues in this manner, selecting one primary frequency source from the available primary frequency sources F1 through Fn, and cycling through the variations for the selected primary frequency source, until a LOCK signal is detected.
After the last primary frequency source Fn has been selected, if still no LOCK signal is asserted by the CDR block 10, then the controller 16 selects F1 and starts the whole process over again. The controller 16 continues to loop as long as SIGNAL DETECT (SD) is asserted, through the primary frequency sources F1 through Fn until a LOCK is found.
If the oscillator 44 is a fixed oscillator, then there is no need for the signal OSC_SELECT from the controller 42, since OSC_FREQ is fixed. Since the numeric width of the multipliers and divisors within frequency synthesizers are increasing, OSC_FREQ serves as a single primary frequency source, and the frequency synthesizer 40 performs various multiply and/or divide operations in conjunction with a PLL to produce the desired reference frequency REF_REQ (within the error margin) to recover the embedded clock.
The operation of controller 42 is similar to that of controller 16. Instead of selecting a primary frequency source, the FREQ_SELECT signal controls the frequency synthesizer 40 (and the OSC_SELECT signal, if oscillator 44 is a VCO) to select a reference frequency REF_FREQ for the CDR 10 to recover the embedded clock. The rest of the operation of the controller 42 remains as described for controller 16 in