Implementations of the present disclosure are generally related to the fabrication of semiconductor devices, and in particular, to a single mask set used for interposer wafer fabrication of multiple products.
Electronic devices, such as tablets, computers, copiers, digital cameras, smart phones, control systems and automated teller machines, among others, often employ electronic components such as dies that are connected by various interconnect components. The dies may include memory, logic or other integrated circuit (IC) device.
ICs may be implemented to perform specified functions. Example ICs include mask-programmable ICs, such as general purpose ICs, application specific integrated circuits (ASICs), and the like, and field programmable ICs, such as field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), and the like.
ICs have become more “dense” over time, i.e., more logic features have been implemented in an IC. More recently, Stacked-Silicon Interconnect Technology (“SSIT”) allows for more than one semiconductor die to be placed in a single package. SSIT ICs may be used to address increased demand for having various ICs within a single package. Conventionally, SSIT products are implemented using an interposer that includes an interposer substrate layer with through-silicon-vias (TSVs) and additional metallization layers built on top of the interposer substrate layer. The interposer provides connectivity between the IC dies and the package substrate. However, fabricating the interposer substrate layer with TSVs for the SSIT products is a complex process. This is due to the several fabrication steps necessary to form the interposer substrate layer with the TSVs that include: forming TSVs within the interposer substrate layer, performing backside thinning and chemical vapor deposition (CVD) or chemical mechanical planarization (CMP), and providing thin wafer handling.
Currently, each product adopting SSIT uses a top cell level design database and photomask to fabricate the interposer wafer. Thus, for each different product, there is additional overhead in terms of engineering time and cost spent to develop the interposer wafer for each product.
Implementations of the present disclosure generally relate to a single mask set used for interposer fabrication of multiple products. A method and apparatus are provided which allow fabrication of interposer wafers for multiple devices using a single mask set. Additionally, the method and apparatus allow fabrication of larger, many layered devices, using multiple exposures of a single mask set.
In one implementation, a method for fabricating an interposer wafer is provided. The method generally includes providing at least one mask having printing regions for forming a plurality of interposer designs; selecting an interposer design; and forming the interposer design on a substrate using a plurality lithographic imaging steps. For each lithographic imaging step, at least one portion of the interposer design is printed by exposing at least one of the printing regions while blocking at least one other of the printing regions.
In another implementation, a method for fabricating an interposer wafer is provided. The method generally includes printing, in a first lithographic imaging step, at least one portion of an interposer design by exposing at least one printing region of at least one mask while blocking at least one other printing region. The method also includes printing, in a second lithographic imaging step, at least one additional portion of an interposer design by exposing at least one printing region of the at least one mask while blocking at least one other printing region.
In one implementation, an apparatus for fabricating an interposer wafer is provided. The apparatus generally includes a lithographic imaging system configured to form the interposer on a substrate using at least one mask having printing regions for forming a plurality of interposer designs. The lithographic imaging system includes a processor programmed to: select an interposer design; and form the interposer design on the substrate using a plurality of lithographic imaging steps. For each lithographic imaging step, at least one portion of the interposer design is printed by exposing at least one of the printing regions while blocking at least one other of the printing regions.
So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to implementations, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical implementations of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective implementations.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements of one implementation may be beneficially incorporated in other implementations.
Aspects of the disclosure generally provide techniques and apparatus for fabrication of interposer wafers for multiple devices using a single mask set and for fabrication of larger, many layered devices, using multiple exposures of a single mask set.
Various features are described hereinafter with reference to the figures. It should be noted that the figures are not drawn to scale and that the elements of similar structures or functions are represented by like reference numerals throughout the figures. It should be noted that the figures are only intended to facilitate the description of the features. They are not intended as an exhaustive description of the claimed disclosure or as a limitation on the scope of the claimed disclosure. In addition, an illustrated implementation need not have all the aspects or advantages shown. An aspect or an advantage described in conjunction with a particular implementation is not necessarily limited to that implementation and can be practiced in any other implementation even if not so illustrated.
Before describing exemplary implementations illustratively depicted in the several figures, a general introduction is provided to further understanding.
With the above general understanding borne in mind, various implementations for an interposer, as well as methodology for creating same, are generally described below. An interposer may be created using multistep imaging by effectively dividing the interposer into image slices (“slices”) and lithographically stitching the slices together. Such multistep imaging may use a single mask for creating an interposer. By lithographic imaging using a mask with features, corresponding to more than one device, for lithographically stitching or interconnecting circuit slices of an interposer, multiple slices of a single mask may be imaged to create interposers for multiple devices.
An Example Silicon Stack Interconnect Technology (SSIT) Product
Silicon stacked interconnect technology (SSIT) involves packaging multiple integrated circuit (IC) dies into a single package that includes an interposer and a package substrate. Utilizing SSIT expands IC products, such as and including FPGA products and other types of products, into higher density, lower power, greater functionality, and application specific platform solutions with low cost and fast-to-market advantages.
The integrated chip package 110 includes a plurality of IC dies 114 (e.g., IC dies 114(1) and 114(2) are shown by example) connected optionally by a silicon-through-via (TSV) interposer 112 (also referred to as “interposer 112”) to a package substrate 122. The chip package 110 may also have an overmold covering the IC dies 114 (not shown). The interposer 112 includes circuitry (not shown) for electrically connecting the IC dies 114 to circuitry (not shown) of the package substrate 122. The circuitry of the interposer 112 may optionally include transistors. Package bumps 132, also known as “C4 bumps,” are utilized to provide an electrical connection between the circuitry of the interposer 112 and the circuitry of the package substrate 122. The package substrate 122 may be mounted and connected to a printed circuit board (PCB) 136, utilizing solder balls 134, wire bonding or other suitable technique. The PCB 136 can be mounted in the interior of a housing 102 of the electronic device 100.
The IC dies 114 are mounted to one or more surfaces of the interposer 112, or alternatively, to the package substrate 122. The IC dies 114 may be programmable logic devices, such as FPGAs, memory devices, optical devices, processors or other IC logic structures. In the example depicted in
The electrical components of integrated chip package 110, such as the IC dies 114, communicate via traces formed on electrical interconnect components. The interconnect components having the traces can include one or more of the PCB 136, the package substrate 122 and interposer 112, among others components.
As mentioned, currently, each product adopting SSIT (e.g., similar to electronic device 100) uses a top cell level design database and photomask to fabricate the interposer wafer (e.g., similar to interposer 112). Thus, for each different product, there is additional overhead in terms of engineering time and cost spent to develop the interposer wafer for each product.
Example Single Mask Set Used for Interposer Fabrication of Multiple Products
Techniques are provided herein for utilizing lithography stepper's blade shuttering function and stitching of exposed different blocks on the wafer to enable use of a single mask to fabricate interposer wafers for multiple products. Using a single mask set of multiple products, as opposed to a different mask set for each product, may result in reduced engineering time and cost spent to develop interposer wafers of new products with similar architectures. In addition, the techniques provided herein may enable fabrication of interposer wafers with larger sizes and larger products, such as field programmable gate arrays (FPGAs).
Photolithography is a process used in microfabrication to pattern parts of a thin film or the bulk of a substrate. It uses light to transfer a geometric pattern from a photomask to a light-sensitive chemical “photoresist”, or simply “resist,” on the substrate. A series of chemical treatments then either engraves the exposure pattern into, or enables deposition of a new material in the desired pattern upon, the material underneath the photo resist. A photomask is an opaque plate with holes or transparencies that allow light to shine through in a defined pattern. Lithographic photomasks can be transparent fused silica blanks covered with a pattern defined with a chrome metal-absorbing film.
A set of photomasks, each defining a pattern layer in integrated circuit (IC) fabrication, is fed into a photolithography stepper or scanner, and individually selected for exposure. In photolithography for the mass production of IC devices (e.g., such as IC dies 114), a photomask may be referred to as a photoreticle or simply reticle.
A stepper is a device used in the manufacture of ICs that is similar in operation to a slide projector or a photographic enlarger. The stepper has a set of blades that mask off all but the selected region on the reticle. So a single reticle might have different items on it. The stepper's blades are used to define what gets exposed when the light shines through the reticle. As used in steppers and scanners, the reticle commonly contains only one layer of the chip. The pattern can be projected and shrunk by four or five times onto the wafer surface. To achieve complete wafer coverage, the wafer is repeatedly “stepped” from position to position under the optical column until full exposure is achieved. Elements of the circuit to be created on the IC are reproduced in a pattern of transparent and opaque areas on the surface of the photomask or reticle.
Using a technique called “stitching” and “pattern overlay,” writing fields can be titled and patterns can be aligned to previously made ones by the stepper. As mentioned above, the stepper blade function the stitching techniques may be used to enable use of single mask for fabrication of multiple devices. It should be understood that an interposer, such as interposer 112, may have alignment marks places in scribe lanes. The alignment marks can be used to measure registration between two print images.
The first device and the second device may share a similar architecture. For example, top slice 202 may be the same as top slice 302, bottom slice 206 may be the same as bottom slice 308, and center slice 204 may be the same as center slice 304 and/or center slice 306. It should be noted that interposers for other devices may have any number of slices.
Conventionally, in order to fabricate the interposer wafer 200 for the first device and the interposer wafer 300 for the second device, at least two mask sets and two design databases are used, one for each different device. However, techniques and apparatus are provided herein for fabricating interposer wafers for multiple devices using only a single mask and design database.
First printing region 402 includes an image for lithographic imaging (“printing”) of a first circuit portion (e.g., a top slice), which in this exemplary implementation includes a circuit module 414 and conductive lines 416 coupled thereto. Second printing region 404 includes an image for lithographic imaging of a second circuit portion (e.g., a center slice), which in this exemplary implementation includes a circuit module 418 and conductive lines 420 and 422 coupled thereto. Third printing region 406 includes an image for lithographic imaging of a third circuit portion (e.g., a bottom slice), which in this exemplary implementation includes a circuit module 424 and conductive lines 426 coupled thereto.
Conductive lines 416 and 420 may be used to interconnect the first circuit portion and the second circuit portion and conductive lines 422 and 426 may be used to interconnect the second circuit portion and the third circuit portion. Along those lines, first printing region 402 may be for a first slice of an interposer, second printing region 404 may be for a second slice of an interposer, and third printing region 406 may be for a third slice of an interposer, where such first slice, second slice, and third slice may be interconnected to one another. Thus, first printing region 402, second printing region 404, and third printing region 406 may each be laid out so as to repetitively print those regions for interconnecting pairs of such regions. For this exemplary implementation, die seals may be located around the perimeters of first printing region 402, second printing region 404, and third printing region 406. However, it should be understood that even though only three printing regions are illustratively depicted, in other implementations more than three printing regions may be used. Furthermore, in other implementations more than three circuit portions may be used for providing an interposer. In other words, even though an interposer is shown as being created using three slices, in other implementations, more than three slices may be used.
In aspects, the mask 400 may be used to fabricate interposer wafers for multiple devices. For example, the mask 400 may be used to fabricate either interposer wafer 200 for the first device or interposer wafer 300 for the second device. For example,
In aspects, the imaging steps of
In aspects, the images may alternately be printed along a row onto substrate 800 while shuttering the other image. It should be understood that in a lithographic scanner, a scanner may have continuous or approximately continuous movement in a first direction for imaging while a mask is continuously or approximately continuously moved in a second direction opposite to such first direction. Along those lines, a row of images may be printed onto a resist layer on the substrate 800. In aspects, all of a first image may be printed in a row onto a resist layer on substrate 800 prior to printing any of the other images. In aspects, even though the above description was in terms of a lithographic scanner, it should be understood that other types of lithographic equipment may be used.
At 904, for the first imaging step, the top portion of an interposer design may be printed by exposing the top printing region. For example, first printing region 402 may be exposed to print images 802 substrate 800, for example to form first circuit portions on the wafer. In aspects, the printing may be repeated on the wafer, for example across a row or starting another row, with care taken to leave space for printing the bottom portion.
At 906, for a second imaging step, the top and bottom printing regions may be blocked. At 908, the center portion of interposer design may be printed by exposing the center printing region. For example, the second printing region 404 may be exposed to print the image 804 on substrate 800, for example to form the second circuit portion on the wafer. In aspects, image 804 may be stitched just below image 802.
At 910, for a third imaging step, the top and center printing regions may be blocked. At 912, the bottom portion of interposer design may be printed by exposing the bottom printing region. For example, the third printing region 406 may be exposed to print the image 806 on substrate 800, for example to form the third circuit portion on the wafer. In aspects, image 806 may be stitched just below image 804. Thus, the example lithographic imaging operations 900 may form images on the interposer wafer 200 as shown in
The above description of
In aspects, the imaging steps of
In aspects, any number of second circuit portions (center portions) could be imaged using second printing region 404. In aspects, this may allow for interposer wafer fabrication for devices, for example FPGAs, of very large size.
In aspects, the images may alternately be printed along a row onto substrate 1400 while shuttering the other image. In aspects, a row of images may printed onto a resist layer on the substrate 1400. In aspects, all of a first image may be printed in a row onto a resist layer on substrate 1400 prior to printing any of the other images. In aspects, even though the above description was in terms of a lithographic scanner, it should be understood that other types of lithographic equipment may be used.
At 1504, for the first imaging step, the top portion of an interposer design may be printed by exposing the top printing region. For example, first printing region 402 may be exposed to print image 1402 on substrate 1400, for example to form the first circuit portion on the wafer. In aspects, the printing may be repeated on the wafer, for example across a row or starting another row, with care taken to leave space for printing the bottom portion.
At 1506, for a second imaging step, the top printing region and bottom printing region may be blocked. At 1508, a center portion of the interposer design may be printed by exposing the center printing region. For example, second printing region 404 may be exposed to print image 1404 on substrate 1400, for example to form the second circuit portion on the wafer.
In aspects, the second imaging step may be repeated any number of times in order to print a desired number of second circuit portions on the wafer. For example, the second imaging step may be performed at least a second time in order to print image 1406 on substrate 1400, for example to form another second circuit portion on the wafer.
In aspects, for each lithographic imaging step, features (e.g., conductors or die seal ring) of at least one portion of the interposer design are interconnected with features of at least one other portion of the interposer design.
At 1510, for a third imaging step, the top printing region and center printing region may be blocked. At 1512, a bottom portion of the interposer design may be printed by exposing the bottom printing region. For example, third printing region 406 may be exposed to print image 1408 on substrate 1400, for example to form the third circuit portion on the wafer. Thus, the example operations 1500 may form images on the interposer wafer 300 as shown in
As mentioned above, a single mask may be used to fabricate an interposer of variable size based on the number of center slice exposures, according to an example implementation. For example, mask 400 with three slices may be used. By exposing additional center slices and stitching the center slices between a top slice and a bottom slice, a desired number of second circuit portions may be printed for fabrication of an FPGA of desired size.
In some aspects, the fabricated interposer may be a passive interposer or an active interposer. In some aspects, the foregoing techniques may also apply to 3D interposer stacking schemes.
While the foregoing describes exemplary implementations, other and further implementations in accordance with the one or more aspects may be devised without departing from the scope thereof, which is determined by the claims that follow and equivalents thereof. Claims listing steps do not imply any order of the steps. Trademarks are the property of their respective owners.
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