Si/SiGe optoelectronic integrated circuits

Abstract

An integrated optoelectronic circuit and process for making is described incorporating a photodetector and a MODFET on a chip. The chip contains a single-crystal semiconductor substrate, a buffer layer of SiGe graded in composition, a relaxed SiGe layer, a quantum well layer, an undoped SiGe spacer layer and a doped SiGe supply layer. The photodetector may be a metal-semiconductor-metal (MSM) or a p-i-n device. The detector may be integrated with an nor p-type MODFET, or both in a CMOS configuration, and the MODFET can incorporate a Schottky or insulating gate. The invention overcomes the problem of producing Si-manufacturing-compatible monolithic high-speed optoelectronic circuits for 850 nm operation by using epixially-grown Si/SiGe heterostructure layers.

Description

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] This invention relates to semiconductors and more particularly to integrated optoelectronic receiver devices and circuits incorporating photodetectors and MODFETs formed with SiGe layers.

[0004] 2. Description of the Prior Art

[0005] The advent of fiber-optic communications technology has increased the demand for high-speed optoelectronic devices and circuits that operate with data rates of greater than 1 Gbit/sec. In particular, a growing market exists for local area networks and short-haul optical connections that operate at wavelengths of λ=850 nm. It would be desirable to fabricate these circuits monolithically due to the lower cost of production and performance advantages over discrete components. It would also be desirable to fabricate such circuits entirely in a silicon-based technology due to the reduced cost arising from their compatibility with existing Si-based technologies including CMOS logic circuits.

[0006] In the prior art, GaAs has been the previous choice for monolithically integrated optical receivers operating at λ=850 nm. This is due to the favorable intrinsic-material properties of GaAs; the absorption length for 850 nm-radiation in GaAs is α−1=1 μm, and the electron mobility in GaAs is roughly 8500 cm2/Vs at room temperature. J. S. Wang et al., IEEE Phot. Tech. Lett. 5, 316 (1993) demonstrated the fabrication of high-speed integrated photoreceiver circuits composed of GaAs metal-semiconductor-metal (MSM) photodiodes and MESFETs with −3 dB bandwidths as high as 11 GHz at λ=850 nm. Further improvement of GaAs-based receiver performance has been obtained using GaAs MSM photodetectors integrated with AlGaAs/GaAs modulation-doped field effect transistors (MODFETs). V. Hurm et al., Electron. Lett. 29, 9 (1993) demonstrated photoreceiver circuits of this type with −3 dB bandwidths as high as 14 GHz at λ=850 nm.

[0007] In order to replace GaAs, an integrated Si-based technology must have comparable performance to GaAs and a relatively low-cost process. However, the intrinsic material properties of Si are much less favorable compared to GaAs. The absorption length in Si for 850 nm-radiation is α−1 =20μm, which is over an order of magnitude longer than in GaAs. Therefore, for a Si photodetector to have high responsivity it must have a thick absorbing region making the detector very slow, and for high speed the absorbing region should be very thin resulting in an extremely poor responsivity. For instance, Y. S. He et al., Electron. Lett. 29, 9 (1993) demonstrated the operation of a lateral p-i-n photodiode integrated with a Si NMOS technology with a responsivity of 0.48 A/W at λ=870 nm, but with a −3 dB bandwidth of only 900 MHz. Moreover, these results were only made possible by using ultra-high purity Si, and an extremely large bias voltage of 30 V. On the other hand, M. Y. Liu et al., Appl. Phys. Lett. 65, 887 (1994) demonstrated operation of a Si on insulator (SOI) MSM photodiode with an absorbing region thickness of only 0.1 μm that had a bandwidth over 100 GHz, but a severely-degraded responsivity at λ=780 nm of 0.0057 A/W. Improvements in the bandwidth/responsivity tradeoff of Si photodiodes are possible, for instance, in U.S. Pat. No. 5,589,704 which was issued on Dec. 31, 1996 to B. F. Levine, the responsivity of an MSM detector was shown to increase by a factor of close to 4 by roughening the surface of a Si epi-layer grown on an SOI wafer. However such a technique is limited to use with SOI substrates, and may not be suitable for practical applications due to the complexities of the roughening process. Si photodetectors are further hindered by the fact that the electron mobility in Si/SiO2 inversion layers is several times lower than GaAs at room temperature, and the frequency performance and gain of Si NMOS devices is considerably poorer compared to GaAs MESFETs.

[0008] In U.S. Pat. No. 5,525,828 which was issued on Jun. 11, 1996 to E. Bassous et al., it was noted that the speed and/or responsivity of Si MSM photodetectors could be increased by adding a certain percentage of Ge to the absorbing layer. Increasing the percent Ge-composition of SixGex alloy decreases the absorption length, and increases the electron and hole mobilities thereby leading to potentially faster devices.

[0009] It has also been shown that field-effect transistors fabricated on Si/Sil-xGex layer structures offer considerable advantages over bulk Si transistors. For n-channel MODFETs incorporating tensile-strained Si/Sil-xGex quantum wells, frequency performance is considerably better than Si MOSFETs for a given gate length device. Similar performance advantages can be obtained in p-channel MODFETs fabricated on compressive-strained Sil-yGey/Sil-xGex quantum wells. For instance, M. Arafa et al., IEEE Electron. Dev. Lett. 17, 586 (1996) obtained unity current-gain cutoff frequencies of 70 GHz for 0.1 μm gate length p-channel transistors fabricated on compressive-strained Si0.7Ge0.3/Si0.3Ge0.7 heterostructures. In U.S. Pat. No. 5,659,187 which was issued on Aug. 19, 1997 to F. K. Legoues and B. S. Meyerson, it was shown that a low-defect density layer of relaxed Sil-xGex, with arbitrary Ge composition can be grown on a lattice-mismatched substrate using an intermediate graded-composition buffer layer where strain has been relieved in the buffer layer or below via activation of modified Frank Read sources which is a mechanism to generate new dislocations. This work demonstrated the practicality of producing devices and circuits using Si/SiGe heterostructures grown on a SiGe graded composition buffer layer on Si substrates. Finally, U.S. Pat. No. 5,534,713 which was issued on Jul. 9, 1996 to K. Ismail and F. Stern showed that complementary logic circuits could be fabricated using high-mobility electron and hole channels fabricated in strained Si/SiGe layers grown on relaxed SiGe buffer layers.

[0010] Despite the apparent advantages of SiGe technology over bulk Si for photodetectors, MODFETs, and CMOS logic circuits, the concept of combining these devices to form integrated photoreceiver circuits has not been suggested, nor has a clear method for monolithically integrating these structures in such a way as to allow high-frequency operation and low cost Si manufacturing been suggested.

[0011] It is an object of the present invention to provide a simple means of monolithically integrating a photodetector with high speed and responsivity with a microwave transistor on a Si substrate in such a way as to allow high frequency performance better than Si and comparable to that achievable in GaAs.

[0012] It is a fuirther object of this invention to provide a method for fabricating an optoelectronic integrated circuit using a process that is fuilly compatible with standard Si processing.

[0013] It is still a fuirther object of this invention to provide a means for monolithically integrating a high-speed photoreceiver circuit with a practical CMOS logic manufacturing technology.

SUMMARY OF THE INVENTION

[0014] A design and method of fabricating an optoelectronic integrated circuit (OEIC) on a Si substrate is presented. This is achieved by using a high-quality, Si/SiGe heterostructure grown on a Si substrate to monolithically integrate a high-speed and responsivity SiGe photodetector and a modulation-doped field effect transistor on the same wafer. A typical layer structure consists of a Si substrate, a graded Ge-content Sil-xGex buffer layer, a thick, undoped relaxed Sil-yGey buffer layer, a Si quantum well, a Sil-yGey undoped offset layer, a doped Sil-yGey supply layer, and optionally a Si surface layer may be incorporated. A MODFET can be fabricated on the layer structure using mesa isolation, and by defining source, drain and gate electrodes, while an MSM photodetector can be created on the etched surface by depositing interdigitated Schottky electrodes on the surface of an exposed buffer layer. The electrodes are configured in such a way that the application of a voltage between adjacent electrodes creates an electric field that penetrates into the underlying layers. Light or radiant energy incident from the surface creates free carriers in the buffer layer that travel to the electrodes, creating a current signal that is proportional to the power of the incident light. By using a bias resistor in series with the photodetector, a voltage is created which can be coupled to the gate of the MODFET, which, when connected to an appropriate load, amplifies the original optical signal.

[0015] The key aspect of this invention is that the Sil-yGey buffer layer not only acts as a pseudosubstrate for the subsequent growth of a MODFET layer structure with carrier mobility greater than bulk Si, but also as a sensitive absorbing medium —— with much greater sensitivity to infrared radiation bulk Si — for a high-speed photodetector, thus providing a dual advantage over bulk Si integrated device structures. Specifically, the absorption coefficient for bulk Si at λ=850 nm is α−1=20 μm, but for Sil-xGex with x=0.25, α−1=8 μm, an improvement by a factor of 2.5. This improvement can be enhanced by increasing the Ge composition of the Sil-xGex alloy; for x=0.75, α−1=5 μm, which is a factor of 4 times greater than in bulk Si. The increased absorption leads to more photogenerated carriers for a given material thickness, and can allow the absorption layer thickness to be decreased, therefore decreasing the transit time of the carriers, and increasing the speed of the detector. The photodetector speed is further improved by using SiGe alloys because both the electron and hole mobilities are increased compared to bulk Si. At the same time, strained-layer structures grown on the relaxed SiGe buffer layers have greatly improved mobility compared to bulk Si structures, mainly due to the band splitting caused by the strain. The electron mobility in modulation-doped, tensile-strained Si quantum wells grown epitaxially on relaxed Sil-yGey buffer layers can be a factor of 3 higher than standard Si/SiO2 inversion layers. Similarly, the hole mobility in compressive-strained Sil-z,Gez quantum wells grown on relaxed Si or Sil-yGey buffer layers, where z >y, similarly show considerable improvement over Si/SiO2 inversion layers. These improvements enable the fabrication of both n- and p-channel FETs that operate at higher frequencies, and have higher gain at a given frequency than Si MOSFET devices with the same gate length.

[0016] The present invention provides a design and method of fabricating a SiGe photodetector with improved speed and responsivity compared to bulk Si on the same substrate as a MODFET device that has improved gain and frequency performance compared to bulk Si, and performance comparable to that of GaAs, and thus providing a method of fabricating integrated photodetector circuits that are greatly improved over bulk Si, and comparable to those achievable in GaAs.

[0017] The invention further provides a means of optimizing the detector by varying the properties of the substrate material, by tailoring the Ge-composition in SiGe and the strain in the epitaxial layer structure, by varying the electrode materials, and by varying the photodetector and Si/SiGe MODFET designs. In this way, the invention is applicable to wavelengths other than λ=850 nm, depending upon the photodetection mechanism, Ge-content and strain of the layers.

[0018] The invention fuirther provides a means of monolithically integrating a high-speed photodetector and a high-mobility transistor (MOSFET or MODFET) using a Si-manufacturing process incorporating SiGe epitaxial layers.

[0019] The invention further provides a means of monolithically integrating a high-speed photodetector and MODFET technology with a manufacturable CMOS logic process, enabling an entire optical/analog/digital subsystem to be fabricated monolithically on a chip.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] These and other features, objects, and advantages of the present invention will become apparent upon consideration of the following detailed description of the invention when read in conjunction with the drawing in which:

[0021] FIGS. 1A-1E are cross-sectional diagrams of the fabrication sequence of one embodiment of the invention where a metal-semiconductor-metal (MSM) photodetector and an n-channel modulation-doped field effect transistor (MODFET) are integrated using an epitaxially-grown Si/SiGe heterostructure.

[0022] FIG. 2 is a circuit diagram of a simple photoreceiver circuit.

[0023] FIG. 3 is a cross-sectional diagram of a second embodiment of the invention, where an n-channel Si/SiGe MODFET is integrated with a SiGe MSM photodetector with planar, deep trench isolation.

[0024] FIG. 4A is a cross-sectional diagram of a third embodiment of the invention where the absorbing layer is composed of a symmetrically-strained superlattice, and FIG. 4B is an energy-band diagram of the absorbing layer in FIG. 4A.

[0025] FIG. 5 is a cross-sectional diagram of a fourth embodiment of the invention where an MSM photodetector and a p-channel MODFET are integrated using an epitaxially-grown Si/SiGe heterostructure.

[0026] FIG. 6A is a cross-sectional diagram of a fifth embodiment of the invention where the positively (negatively) biased electrode of the MSM photodetector is composed of a material with high Schottky barrier for holes (electrons). FIG. 6B is a cross-sectional diagram of a sixth embodiment of the invention where the negatively biased photodetector electrode is composed of a material with high Schottky barrier for electrons, and the positively biased electrode is composed of an n-type Ohmic contact. FIG. 6C is a cross-sectional diagram of a seventh embodiment of the invention where the positively (negatively) biased photodetector electrode is composed of an n-type (p-type) Ohmic contact.

[0027] FIG. 7A is a cross-sectional diagram of an eighth embodiment of the invention where the substrate is an SOI wafer. FIG. 7B is a cross-sectional diagram of a ninth embodiment of the invention where the substrate is a heavily-doped n- or p-type Si wafer. FIG. 7C shows a cross-sectional diagram of a tenth embodiment of the invention where the substrate has a heavily-doped implanted region located directly underneath the MSM photodetector.

[0028] FIG. 8A shows a cross-sectional view along the line 8A-8A of FIG. 8B. FIG. 8B shows a top view of a SiGe MSM photodetector. FIG. 8C is a graph of the normalized photoresponse versus frequency of the SiGe MSM photodetector shown in FIGS. 8A and 8B.

[0029] FIG. 9 is a graph of current gain and of maximum available gain plotted versus frequency for an n-channel Si/SiGe MODFET.

[0030] FIG. 10 is a cross-sectional diagram of a eleventh embodiment of the invention where a vertical p-i-n photodetector and an n-channel MODFET are integrated using an epitaxially-grown Si/SiGe heterostructure.

[0031] FIG. 11 is a cross-sectional diagram of a twelfth embodiment of the invention where an MSM photodetector and an n-channel modulation-doped MOSFET are integrated using a standard self-aligned poly-gate, salicide process.

[0032] FIG. 12 is a cross-sectional diagram of a thirteenth embodiment of the invention where an MSM photodetector and a strained Si n-MOSFET are integrated using a planar fabrication process.

[0033] FIG. 13 is a cross-sectional diagram of a fourteenth embodiment of the invention where an MSM photodetector is integrated with both an n-channel and a p-channel MODFET using an epitaxially-grown Si/SiGe heterostructure.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] FIGS. 1A-1E show the fabrication sequence for one embodiment of the invention where an n-channel, Si/SiGe modulation-doped field effect transistor (MODFET) 15 is integrated with a SiGe metal-semiconductor-metal (MSM) photodetector. A typical layer structure is shown in FIG. 1A. The layers are epitaxially grown on a Si substrate 1 using a high-precision epitaxy technique such as molecular beam epitaxy, rapid thermal cheimcal vapor deposition, or ultra high vacuum chemical vapor deposition (UHV-CVD). Substrate 1 may also be SiGe, Ge, GaAs, SiC, SOS and SOI. Suitable adjustments will be required to accomodate a different substrate lattice constant compared to Si. The following description is directed to a Si substrate. For a description of how to grow epitaxial Si and Sil-xGex layers by UHV-CVD, reference is made to U.S. Pat. No. 5,298,452 which was issued on Mar. 29, 1994 to B. S. Meyerson which is incorporated herein by reference. For Sil-xGex layers, GeH4 is added to Si-containing gas such as SiH4 or Si2H6 in the UHV-CVD reactor. Ge is incorporated into the crystal lattice in place of Si during formation of the layer in the amount or proportion of x. Layer 2 comprises a Sil-xGex buffer layer that has a thickness in the range from 0.2 to 1.5 μm, with a preferred value of about 0.5 μm, and has a percent Ge composition that is increased from x=0 (in a continuous or stepwise fashion) to a value in the range from x=0.10 to 1.0 with a preferred value of x=0.25. Layer 2 serves to relax the strain caused by the lattice mismatch between layer 2 of graded Ge composition Sil-xGex and Si substrate 1. Ge has a lattice spacing of 1.04 times the lattice spacing of Si. Thus for a relaxed top surface of buffer layer 2 where x equals 0.25, the lattice spacing of the unit cell along each axis in the top surface is about 1.01 times the lattice spacing of the unit cell of Si along each axis. For a description of how to grow relaxed low defect top surfaces of Sil-xGex layers, reference is made to U.S. Pat. No. 5,659,187 which was issued on Aug. 19, 1997 to F. K. Legoues and B. S. Meyerson which is incorporated herein by reference. After the graded region of layer 2, a 0.25 to about 10 μm thick, undoped or not-intentionally doped layer 3 of Sil-yGey is grown, where the Ge composition, typically y =0.25, is in the range from y =0.10 to 1.0. Layer 3 acts as the absorbing medium for radiant energy as well as a relaxed, device quality pseudosubstrate for growth of subsequent layers. The background impurities in layer 3 should be low enough to allow penetration of the electric field from the surface electrodes into the entire layer.

[0035] In one embodiment, the subsequent layers are a Si quantum well layer 4, a Sil-yGey undoped or not-intentionally doped offset layer 5, a doped Sil-yGey supply layer 6 and optionally a Si layer 7. By an undoped layer, it is meant a not-intentionally doped layer which may have a background dopant concentration so low as to not substantially affect the fuinction of the layer. The Ge composition of layers 5 and 6 are in the range of y=0.1 to 1.0 and y is preferably the same as the composition of layer 3. A quantum well for electrons is formed in Si layer 4 due to the conduction band splitting arising from the tensile strain in Si layer 4. The isolation for MODFET 15 is achieved by forming an etched mesa region, thereby exposing the surface 8 of Sil-yGey buffer layer 3 in the etched regions, as shown in FIG. 1B. Next, in FIG. 1C, ntype implanted regions 9 are formed to facilitate making low-resistance contacts to the Si quantum well layer 4. The source and drain metallization 10 can then be deposited as depicted in FIG. 1D, followed by the gate metallization 12 shown in FIG. 1E.

[0036] The MSM photodetector is created by depositing interdigitated Schottky electrodes 11 on the exposed surface 8 of buffer layer 3. To simplify the fabrication process, it is possible for MSM electrodes 11 to be defined in the same lithographic step as the Ohmic metallization 10, as depicted in FIG. 1D. MSM electrodes 11 are configured in such a way such that a bias applied between adjacent electrodes, as shown in FIG. 1E, creates an electric field that penetrates into the underlying absorbing layer 3. Light or radiant 14 energy incident from or passing through surface 8 creates free carriers, electrons 15 and holes 16, in layer 3 that travel to electrodes 11, creating a current signal that is proportional to the power of the incident light.

[0037] FIG. 2 depicts the manner in which the devices shown in FIG. I are connected to form a simple photoreceiver circuit 17. A bias voltage, Vdiode, is applied to the positive MSM electrode, while the negative electrode is connected to the gate of depletion-mode transistor 18, and to a bias resistor 19, Rbias, which is connected to a negative supply voltage, −Vss. The transistor source is connected to ground, while the drain is connected to a load resistor 20, Rload, which is connected to the supply voltage, Vdd. In this configuration, the photocurrent induced by the incident light creates a voltage across the bias resistor 19 which is input to the gate of the transistor 18, thereby modulating the transistor current, and creating an amplified signal at the output lead 21, Vout. Resistors 19 and 20 may be formed and interconnected on the chip with the photodetector 22 and transistor 18 which is well known in the art. Other optoelectronic circuits may be formed which for example use more transistors to optimize the circuit to the application.

[0038] FIG. 3 shows another embodiment of the invention that is the same as that shown in FIG. 1E, except that the MSM photodetector is surrounded by a deep isolation trench 23 that extends from the surface 8 of the relaxed buffer layer 3 down into the substrate 1. Isolation trench 23 serves to confine the carriers that are generated in Sil-yGey buffer layer 3 from diffusing laterally outside the region directly beneath the detector geometry. The trench also serves to isolate slow carriers generated outside the high-field region directly beneath the detector geometry from being collected by the surface electrodes 11, thereby leading to improved high-frequency performance. Furthermore, deep isolation trench 23 can be planarized by filling with a dielectric material 24. The trench can readily be incorporated into the fabrication scheme shown in FIGS. 1A-1E, by etching deep isolation trench 23 before the mesa isolation in FIG. 1B, then filling the trench with dielectric material 24, followed by a planarization step. The subsequent fabrication steps can then be performed as depicted in FIG. 1B-1E.

[0039] FIG. 4A shows another embodiment of the invention that is the same as that shown in FIG. 1E, except that the relaxed buffer layer 38, over layer 2, is composed of a symmetrically strained superlattice instead of a constant-composition alloy Sil-yGey. The superlattice consists of alternating layers of Sil-xGex, 35, and Sil-zGez, 36, where x <y <z, and have Ge-compositions such that the average composition in buffer layer 38 is equal to y where y is in the range from 0.1 to 0.9, with a preferred value of 0.25. The tensile strain in Sil-xGex layer 35, and the compressive strain in Sil-zGez layer 36 enhances the absorption of radiation by reducing the effective band gap of buffer layer 38. To ensure that the photogenerated carriers are not trapped in the potential wells formed by strained layers 35 and 36, the Ge composition of buffer layer 38 can be graded in a continuous fashion, to produce a smooth, rather than abrupt, potential profile. This situation is shown schematically in FIG. 4B, where the conduction and valence band edges, shown by curves 41 and 42, of alternating strained layers 35 and 36 are plotted along with the conduction and valence band edges, shown by curves 43 and 44, of a constant composition layer. The average band gap of the symmetric superlattice Eg2, shown by arrow 45, is reduced compared to that of the constant composition layer, Eg1, shown by arrow 46, leading to greater photoabsorption in the symmetric superlattice. The operation of the MODFET 15 structure shown in FIG. 4A is not affected by the symmetric superlattice because no net strain i% built up in layer 38. Therefore, after the growth of the superlattice 38, only a thin, constant-composition Sil-yGey layer 37, needs to be deposited before growing the MODFET 15 layers 4-7. For layer 37, y is in the range from 0.1 to 0.9, and is preferably equal to the average Ge-composition of layer 38.

[0040] Another embodiment of the invention is shown in FIG. 5, where a SiGe MSM photodetector is integrated with a p-channel MODFET 47. This configuration consists of a graded buffer layer 2 followed by a constant composition Sil-yGey absorbing layer 3, similar to that of FIGS. 1A-1E. These layers are followed by a layer structure for a p-channel MODFET 47, consisting of a Sil-wGew, doped layer 48, where w <y, an undoped Sil-yGy layer 49, a compressive-strained Sil-zGez quantum well layer 50, where z <y, an undoped Sil-yGey layer 51, and optionally a thin Si layer 52. The Ge percentages for this embodiment can vary from y=0.1 to 0.9, w=0 to 0.5, and z=0.5 to 1.0. This embodiment could be particularly useful because of high Ge-content buffer layer 3 produces very efficient optical absorbtion, yet is also ideal for producing very high hole mobilities in p-channel MODFETs due to the compressive strain in the Sil-zGez quantum well layer 50, particularly for the case of a pure-Ge channel where the mobility is not degraded by alloy scattering. MODFET 47 can be fabricated similar to the n-type device process shown in FIGS. 1A-1E, where a mesa etch is used to isolate MODFET 47 and expose the surface 8 of photodetector absorbing layer 3. Next, p-type implanted regions 83 are formed to create low-resistance contacts to the Sil-zGez quantum well layer 50. The source and drain metallization 54 can then be deposited, followed by the gate metallization 56. The embodiment in FIG. 5 could also be fabricated with a reduced number of fabrication steps by defining the MSM electrodes 55 in the same lithographic step as the gate metallization 56 for MODFET 47.

[0041] As the Ge content of the buffer layers is increased, the band gap shrinks, leading to larger dark currents for the photodiode. A method of reducing the dark current without a dramatic increase in process complexity is to use different materials for alternate electrodes of the photodetector. FIG. 6A shows one embodiment of the invention, where the positively-biased electrodes 60 of the MSM photodiode have a high Schottky barrier height for holes, and the negatively-biased electrodes 61 have a high Schottky barrier height for electrons. To simplify the fabrication process, it is possible for the positively-biased (negatively-biased) electrodes 60 (61) to be defined in the same lithographic step as the Ohmic (gate) metallization, 10 (12). Possible candidates for the positively-biased MSM electrodes and Ohmic contact material are Er, W, Ti, Ni and Co, while the negatively-biased MSM electrodes and gate material might be Pt or Ir.

[0042] FIG. 6B shows another embodiment of the invention where negatively biased photodiode electrode 61 is composed of a material with high Schottky barrier for electrons, such as Pt or Ir, and the positively biased electrode is composed of n-type doped region 63, and electrode 64 which makes an Ohmic contact to region 63. As in FIG. 6A, the fabrication process can be simplified by fabricating n-type doped region 63 and positively-biased electrode 64 at the same time as MODFET 15 source-drain implant 9, and Ohmic metallization 10, and negatively-biased electrode 61 at the same time as MODFET gate metallization 12.

[0043] FIG. 6C shows another embodiment of the invention where the photodiode consists of a lateral p-i-n geometry, and where the positively-biased photodiode:.electrode is composed of n-type doped region 63, and electrode 64 which makes an Ohmic contact to region 63, and the negatively-biased photodiode electrode is composed of p-type doped region 65, and an electrode 66 which makes an Ohmic contact to region 65.

[0044] The photodetector performance can be optimized by varying the properties of the substrate. For instance, FIG. 7A shows a structure similar to FIG. 1E, where the substrate is an SOI wafer 70 and consists of a thick Si substrate 71, a SiO2 layer 72, and a roughly 200 nm-thick Si layer 73. Without degrading MODFET 15 performance, SiO2 layer 72 can improve the performance of the SiGe MSM photodetector by preventing slow carriers generated in Si substrate 71 below SiO2 layer 72 from reaching the MSM surface electrodes 11, thereby increasing the detector speed. The amount of light reflected back into buffer layer 3 can be maximized by adjusting the thickness of SiO2 layer 72 to equal odd integer multiples of λ/4n, where λ is the wavelength of the incident light, and n is the refractive index of SiO2.

[0045] Similarly, as shown in FIG. 7B, the substrate could consist of a heavily doped (>1018 cm3) Si wafer 74 that causes photogenerated carriers in the layer to recombine before they can reach surface electrodes 11. The heavily-doped substrate 74 also acts to prevent the electric field produced by MSM interdigitated electrodes 11 from penetrating into substrate 74, thereby increasing the electric field strength in undoped SiGe absorbing layer 3, and subsequently increasing the detector speed.

[0046] As shown in FIG. 7C, the substrate capacitance can be reduced compared to the embodiment shown in FIG. 7B by selectively doping substrate 1 only in region 75 underneath MSM interdigitated electrodes 11. Selectively-doped region 75 can easily be formed before the growth of the Si/SiGe epi-layers using ion implantation, and then later aligned to MSM interdigitated electrodes 11.

[0047] FIG. 8C, curve 77, is a graph of the frequency response of the SiGe MSM photodetector comprising a Si0.75Ge0.25 absorbing layer at a thickness of 2.8 μm depicted in the cross-sectional and top-view diagrams of FIGS. 8A and 8B. In FIG. 8C, the ordinate represents normalized photoresponse (dB) and the abscissa represents frequency (Hz). This device had a dc responsivity of 0.1 A/W, and displayed a −3 dB (−6 dB) bandwidth of 0.95 GHz (2.7 GHz), at λ=850 nm, for a bias voltage of +5 V. To our knowledge, this is the highest bandwidth achieved to date for a crystalline SiGe MSM photodetector for an incident radiation of λ=850 nm.

[0048] FIG. 9 shows the frequency response of an n-channel MODFET fabricated very similar to MODFET 15 shown in FIG. 1E. In FIG. 9, curve 78 shows the current gain versus frequency of the n-channel MODFET and curve 79 shows the maximum available gain versus frequency. In FIG. 9, the left ordinate represents current gain (dB), and the right ordinate represents maximum available gain (dB), and the abscissa represents frequency. The device shows a unity-gain cutoff frequency of 31 GHz, for a gate length of 0.7 μm, performance which is far superior to bulk Si MOSFETs of the same gate length. These results shown by curve 77 in FIGS. 8C and by curves 78 and 79 in FIG. 9 on the individual components of the integrated circuit indicate the viability of the present invention, particularly given the straightforward method of integration described herein.

[0049] The selectively-doped substrate configuration shown in FIG. 7C can also be modified to integrate a vertical p-i-n photodetector 80 with an n- or p-channel MODFET 15. One such embodiment is shown in FIG. 10, where p-i-n photodetector 80 and an n-channel MODFET 15 are fabricated using an n-type modulation-doped heterostructure, as described in FIG. 1E. In this embodiment, the p-i-n photodetector 80 is created when an n-type implanted region 80 and top contact 81 are aligned to a heavily-doped p-type region 82 created before the growth of the Si/SiGe epi-layers 2 and 3. The bottom contact 83 is made by etching down to and into substrate 1 as shown in FIG. 10. The embodiment in FIG. 10 has the advantage that the n-channel, modulation-doped regions 4-7 do not need to be etched away to make top contact 81 of the p-i-n detector 80, because this contact already needs to be doped n-type. This embodiment can also be used with a buffer layer 38 consisting of a symmetric superlattice as described in FIG. 4. MODFET 15 shown in this embodiment is an n-channel device. For integration with a p-channel MODFET, the doping and polarity of the p-i-n contacts 80-83 can be reversed. The p-i-n configuration has the advantage that the carriers are always generated in a high-field region, and the distance the photogenerated carriers have to travel is reduced because detector electrodes 81 and 83 are on both the top and bottom of absorbing region 3.

[0050] FIG. 11 shows how an MSM photodiode 85 and MODFET 86 can be integrated using a fabrication scheme similar to that of a standard Si MOSFET or CMOS process. In the preferred embodiment, the layer structure is the same as that used in FIG. 1A. The MODFET 86 can be fabricated by depositing a thin gate oxide layer 90 followed by an undoped poly-silicon layer that is patterned and etched to define the gate electrode 91. Next an ion implant is performed to define n-type source and drain regions 92 where poly-silicon gate electrode 91 is used as a self-aligned implant mask. Next, a mesa isolation etch is performed which exposes the surface 8 of the buffer layer 3 in the etched regions. Next an insulating layer 93, such as silicon nitride, is deposited and then etched to form sidewall spacer regions 94. Finally, a self-aligned silicide (salicide) process is performed, where metal is deposited, heated to form metal-silicide or metal-germanosilicide contacts 95 to n-type source and drain regions 92 and the unreacted metal selectively etched away. The main feature of this embodiment is that the MSM photodetector 85 can be fabricated at the same time as MODFET 86 source and drain contacts 95 using the salicide process, by patterning windows in insulating layer 93 above SiGe buffer layer 3 to form metal-silicide or metal-germanosilicide photodetector electrodes 96 in openings of insulating layer 93.

[0051] FIG. 12 shows another embodiment of the invention where a SiGe MSM 97 and a strained-Si n-channel MOSFET 98 are integrated using a planar processing scheme. For this structure, the layer structure consists of the same graded Silre layer 2 and constant composition, Sil-yGey buffer layer 3 grown on Si substrate 1 as shown in FIG. 1E. On top of buffer layer 3 is grown a tensile-strained Si layer 100, as shown in FIG. 12. In the preferred embodiment, the MOSFET 98 is fabricated by depositing or growing a thin gate oxide layer 101, followed by an undoped poly-silicon layer, which is patterned and etched to define the gate electrode 102. Next an optional p-well implant 103, is performed for threshold voltage control, and an ion implant is performed to define n-type source and drain regions 104, where poly-silicon gate electrode 102 is used as a self-aligned implant mask. Next, trench isolation regions 105, are formed and filled with dielectric material 106, and a second insulating layer 107, such as silicon nitride, is deposited and etched to form sidewall spacer regions 108. Finally, a self-aligned silicide (salicide) process is performed, where metal is deposited, heated to form metal-silicide, or metal-germanosilicide contacts 109 on n-type source and drain regions 104, and the unreacted metal selectively etched away. The MSM photodetector 97 is fabricated using the same salicide process used to create the MOSFET 98 source and drain regions, by patterning windows in insulating layer 107 above SiGe buffer layer 3 to form metal-silicide or metal-germanosilicide photodetector electrodes 110 in the openings of insulating layer 107. This embodiment has the advantage of utilizing a planar processing scheme, because Si layer 100 is not etched away. Because Si layer 100 is only ˜10 nm thick, it has little effect on the photoabsorption, and can act as a stable surface material for formation of MSM electrodes 110.

[0052] FIG. 13 shows another embodiment of the invention where MSM photodetector 85 is integrated with both a p-channel and an n-channel Si/SiGe MOSFET, 139 and 140, using an epitaxal multi-layer structure. The layer structure consists of a Si substrate 1, a graded Si1-xGex layer 2 and constant composition Sil-yGey buffer layer 3 as described in FIG. 1A. In the preferred embodiment, on top of Sil-yGey buffer layer 3 are grown an n-type doped Sil-yGey supply layer 120, an undoped Si,yGey offset layer 121, a tensile-strained Si quantum well layer 122, which acts as the electron channel for the NMOS device, another un4oped Sil-yGey offset layer 123, a compressive-strained Sil-zGez layer 124, where z >y, which acts as the hole channel for the PMOS device, an undoped Sil-yGey offset layer 125, and an undoped Si layer 126. In this embodiment, the Ge-percentages of layers 120, 121, 123 and 125 is in the range y=0.1 to 0.9, with a preferred value of y=0.25. The Ge-percentage of layer 124 is in the range z =0.3 to 1.0, and preferably has a value where z-y is greater than 0.2. Next a thin gate oxide layer 127, is grown or deposited, followed by a p-type doped poly-silicon layer. The CMOS circuit can be fabricated by etching the poly-silicon to form the gates of the n- and p-type CMOS devices 128, which then act as implant masks for formation of p-type doped region 129, and n-type doped region 130. Doped regions 129 and 130 form contacts to the buried quantum well channel layers 124 and 122, respectively. Next, trench isolation regions 131, are formed and filled with dielectric material 132, for planarization. At this point, an etch is performed to expose the surface 8 of Sil-yGey buffer layer 3, and a blanket insulating layer 134, such as silicon nitride, is deposited. Windows for forming the photodiode electrodes are patterned and etched at the same time as nitride sidewall regions 135 are formed. Finally, a salicide step is performed, as described in FIG. 11, to create the MSM electrodes 136, as well as the source and drain contacts 137 and 138 of the PMOS and NMOS devices, respectively. The embodiment shown in FIG. 13 is a versatile configuration where not only PMOS device 139 or NMOS device 140 can be combined with MSM photodetector 85 to act as part of a photoreceiver amplifier circuit, but PMOS device 139 and NMOS device 140 can be combined and used to form a CMOS logic circuit. Therefore, the embodiment in FIG. 13 can potentially be used to fabricate a high-speed photoreceiver circuit on the same chip as a high-speed, low-power CMOS technology, for future “system-on-a-chip” applications.

[0053] In the Figures, like references are used for functions corresponding to the apparatus of one or more earlier Figures.

[0054] While there has been described and illustrated a integrated optoelectronic receiver device containing a photodetector and MODFET having SiGe layers with one or more Si or SiGe layers under strain, it will be apparent to those skilled in the art that modifications and variations are possible without deviating from the broad scope of the invention which shall be limited solely by the scope of the claims appended hereto.

Claims

1. A semiconductor structure comprising a single crystal semiconductor substrate, a Sil-xGex buffer layer graded from x =0 to y where y is in the range from 0.1 to 1.0, a layer of relaxed Sil-yGey having a thickness in the range from 0.25 μm to 10 μm, a quantum well layer, an undoped Sil-yGey spacer layer, and a doped Sil-yGey supply layer, wherein said layer of relaxed Sil-yGey may function as the absorbing region of a photodetector, said quantum well layer may function as the conducting channel of a field-effect transistor, and said spacer layer may function to separate dopants in said supply layer from said conducting channel.

2. The semiconductor structure of claim 1 further including spaced apart drain and source regions extending to said quantum well layer and a Schottky gate contact to control charge in said conducting channel to form a MODFET.

3. The semiconductor structure of claim 1 wherein portions of said quantum well layer, said undoped Sil-yGey spacer layer and said doped Sil-yGey supply layer are removed to expose said relaxed Sil-yGey layer wherein electrodes are formed on said exposed relaxed Sil-yGey layer to form a photodetector.

4. The semiconductor structure of claim 1 wherein said quantum well layer is under tensile strain.

5. The semiconductor structure of claim 1 wherein said quantum well layer consists of Si.

6. The semiconductor structure of claim 3 wherein said electrodes include two or more interdigitated Schottky electrodes.

7. The semiconductor structure of claim 1 wherein y is in the range from 0.2-0.35.

8. The semiconductor structure of claim 3 further including a trench extending through said exposed relaxed Sil-yGey layer surface and surrounding said photodetector.

9. The semiconductor structure of claim 8 wherein said trench is filled with material including dielectric material.

10. The semiconductor structure of claim 1 further including a layer of Si over said doped Sil-yGey supply layer.

11. The semiconductor structure of claim 1 wherein said doped Sil-yGey supply layer is n-type.

12. The semiconductor structure of claim 6 wherein positively-biased electrodes of said photodetector provide Schottky contacts with barrier height for holes that is greater than than half the band gap of said exposed relaxed Sil-yGey layer, and negatively-biased electrodes of said photodetector provide Schottky contacts with barrier height for electrons that is greater than half the band gap of said exposed relaxed Sil-yGey layer.

13. The semiconductor structure of claim 6 wherein negatively-biased electrodes of said photodetector provide Schottky contacts with barrier height for electrons that is greater than half the band gap of said exposed relaxed Sil-yGey layer, and positively-biased electrodes of said photodetector form Ohmic contact to an n-type doped region.

14. The semiconductor structure of claim 6 wherein negatively-biased electrodes of said photodetector form Ohmic contacts to a p-type doped region and said positively-biased electrodes of said photodetector form an Ohmic contact to an n-type doped region.

15. The semiconductor structure of claim 1 wherein said substrate is heavily-doped greater than 1018 atoms/cm3.

16. The semiconductor structure of claim 1 wherein said substrate is an SOI substrate comprising a thick Si layer, a SiO2 layer, and a Si overlayer.

17. The semiconductor structure of claim 3 wherein said substrate is lightly-doped Si, and the region of said substrate underneath said photodetector is heavily-doped greater than 1018 atoms/cm3.

18. The semiconductor structure of claim 3 wherein said photodetector absorbing region is bordered by deep trenches extending from said photodetector surface down to said Si substrate, and filled with a dielectric material, so as to prevent photogenerated carriers generated in said Sil-yGey buffer layer from diffusing lateraly past said deep trenches.

19. The semiconductor structure of claim 1 further including spaced apart drain and source regions extending to said quantum well layer, a gate dielectric layer above said supply layer between said drain and source and a gate electrode above said dielectric layer to form a MOSFET.

20. The semiconductor structure of claim I further including first and second spaced apart doped regions, one above the other, with a portion of said relaxed Sil-yGey layer there between to form a photodetector and an Ohmic contact to said respective first and second doped regions for applying a potential there between.

21. The semiconductor structure of claim 20 further including a trench extending into said exposed relaxed Sil-yGey layer to provide a barrier to electrical charge.

22. The semiconductor structure of claim 20 wherein said first doped region includes a region of said quantum well layer, said undoped Sil-yGey spacer layer and said doped Sil-yGey supply layer.

23. The semiconductor structure of claim 20 wherein said second doped region includes a region of said substrate.

24. A semiconductor structure comprising a single crystal substrate, a Sil-xGex buffer layer graded from x =O to x =y, wherey is in the range from 0.1 to 0.9, a constant composition layer of relaxed Sil-yGey having a thickness in the range from 0.25 μm to 10 μm, a p-type doped Sil-wGew supply layer, where w <y, an undoped Sil-yGey spacer layer, a Sil-zGez quantum well layer, where z >y, and an additional undoped Sil-yGey spacer layer, wherein said constant composition layer of relaxed Sil-yGey may function as the absorbing region of a photodetector, and said Sil-zGez quantum well layer may function as the conducting channel of a field-effect transistor.

25. The semiconductor structure of claim 24 further including spaced apart drain and source regions extending to said quantum well layer and a Schottky gate contact to control charge in said conducting channel to form a MODFET.

26. The semiconductor structure of claim 25 wherein portions of said p-type doped Sil-zGew supply layer, said undoped Sil-yGey spacer layer, said Sil-zGez quantum well layer, said additional undoped Sil-yGey spacer layer are removed to expose said relaxed Sil-yGey layer and wherein electrodes are formed on said exposed relaxed Sil-yGey layer to form a photodetector.

27. A semiconductor structure comprising a single crystal semiconductor substrate, a Sil-xGex buffer layer graded from x =O to y in the range from 0.1 to 0.9, followed by a plurality of layers forming a symmetrically-strained superlattice and consisting of alternating layers of Sil-wGew and Sil-zGez, where w <y <z, and having corresponding individual thicknesses such that the average Ge-composition of the layer is y, and having a total thickness in the range from 0.25 μm to 10 μm, and additionally a thin Sil-yGey layer, a quantum well layer, an undoped Sil-yGey spacer layer, and an n-type doped Sil-yGey supply layer, wherein said symmetric superlattice may function as the absorbing region of a photodetector, and said quantum well layer may function as the conducting channel of a field-effect transistor.

28. The semiconductor structure of claim 27, wherein said transistor comprises trench or mesa-defined isolation regions, source and drain electrodes and a Schottky gate contact, and said photodetector includes two or more interdigitated Schottky electrodes deposited onto the etch-exposed surface of said thin Sil-yGey layer.

29. A semiconductor structure comprising a substrate selected from the group consisting of Si and SOI, a Sil-xGex buffer layer graded from x =O to x =y, where y is in the range from 0.1 to 1.0, a constant composition layer of relaxed Sil-yGey, of thickness 0.25 μm to 10 μm a thin Si surface layer, and a thin gate dielectric, wherein said constant composition layer of relaxed Sil-yGey acts as the absorbing region of a photodetector, and said Si surface layer acts as the conducting channel of a field-effect transistor.

30. The semiconductor structure of claim 29, wherein said transistor comprises a trench or mesa-defined isolation regions, source and drain electrodes and a polysilicon or metal gate contact, and the photodetector consists of two or more Schottky electrodes formed on the surface of the top Si layer.

31. The semiconductor structure of claim 29 wherein the transistor source and drain contacts and the photodetector Schottky electrodes include one of metal-silicide and metal-germanosilicide.

32. A semiconductor structure comprising a single crystal semiconductor substrate, a Sil-xGex buffer layer graded from x =O to y where y is in the range from 0.1 to 0.9, a layer of relaxed Sil-yGey having a thickness in the range from 0.25 μm to 10 μm, an n-type doped Sil-yGey supply layer, a first undoped Sil-yGey layer, a second undoped Sil-yGey offset layer, a second quantum well layer, a third undoped Sil-yGey offset layer, an undoped Si layer, a gate dielectric and a gate electrode layer wherein said layer of relaxed Sil-yGey may function as the absorbing region of a photodetector, and said first quantum well layer may act as an electron channel for an n-MOSFET, and said second quantum well layer acts as a hole channel for a p-MOS FET.

33. The semiconductor structure of claim 32 wherein said n-MOSFET comprises trench or mesa-defined isolation regions, spaced apart source and drain regions extending to said first quantum well layer and a first gate electrode to control charge in said first quantum well layer, and said p-MOSFET comprises trench or mesa-defined isolation regions, spaced apart source and drain regions extending to said second quantum well layer and a second gate electrode to control charge in said second quantum well layer.

34. The semiconductor structure of claim 33 wherein portions of said n-type doped Sil-yGey supply layer, said first undoped Sil-yGey layer, said second undoped Sil-yGey offset layer, said second quantum well layer, said third undoped Sil-yGey offset layer, said undoped Si layer, said gate dielectric layer and said gate electrode layer are removed to expose said relaxed Sil-yGey layer wherein electrodes are formed on said exposed relaxed Sil-yGey layer to form a photodetector.

35. A method for forming a semiconductor structure comprising the steps of: selecting a single crystal semiconductor substrate, forming a Sil-xGex buffer layer graded from x =O to y in the range from 0.1 to 1.0, forming a layer of relaxed Sil-yGey having a thickness in the range from 0.25 μm to 10 μm forming a quantum well layer, forming an undoped Sil-yGey spacer layer, and forming a doped Sil-yGey supply layer.

36. The method of claim 35 further including the steps of forming spaced apart drain and source regions extending to said quantum well layer and forming a Schottky gate contact to control charge in said conducting channel to form a MODFET.

37. The method of claim 35 further including the steps of removing portions of said quantum well layer, said undoped Sil-yGey spacer layer and said doped Sil-yGey supply layer to expose said relaxed Sil-yGey layer and forming electrodes on said exposed relaxed Sil-yGey layer to form a photodetector.

38. The method of claim 37 further including the step of forming a trench extending into said exposed relaxed Sil-yGey layer to provide a barrier to electrical charge.

39. The method of claim 37 further including the step of doping said substrate underneath said photodetector greater than 1018 atoms/cm3.

40. The method of claim 35 further including the steps of forming spaced apart drain and source regions extending to said quantum well layer, forming a gate dielectric layer above said supply layer between said drain and source and forming a gate electrode above said dielectric layer to form a MOSFET.

41. The method of claim 35 further including the steps of forming first and second spaced apart doped regions, one above the other with a portion of said relaxed Sil-yGey layer there between to form a photodetector and forming an Ohmic contact to said respective first and second doped regions for applying a potential therebetween.

42. The method of claim 41 further including the step of forming a trench extending through said exposed relaxed Sil-yGey layer to provide a barrier to electrical charge.

43. The method of claim 41 wherein said step of forming said second doped region includes the step of doping said substrate.

44. A method of forming a semiconductor structure comprising the steps of: selecting a single crystal substrate, forming a Sil-xGex buffer layer graded from x =O to x =y where y is in the range from 0.1 to 0.9, forming a constant composition layer of relaxed Sil-yGey having a thickness in the range from 0.25 μm to 10 μm, forming a p-type doped Sil-zGez supply layer, where w is greater than y, forming an undoped Sil-yGey spacer layer, forming a Sil-zGez quantum well layer, where z is greater than y, and forming an additional undoped Sil-yGey spacer layer, wherein said constant composition layer of relaxed Sil-yGey may function as the absorbing region of a photodetector, and said Sil-zGez quantum well layer may function as the conducting channel of a field effect transistor.

45. The method of claim 44 further including the step of forming spaced apart drain and source regions extending to said, quantum well layer and a forming a Schottky contact to control charge in said conducting channel to form a MODFET.

46. The method of claim 44 further including the steps of removing portions of said p-type doped Sil-wGew supply layer, said undoped Sil-yGey spacer layer, said Sil-zGez quantum well layer, said additional undoped Sil-yGey spacer layer to expose said relaxed Sil-yGey layer and forming electrodes on said exposed relaxed Sil-yGey layer to form a photodetector.

47. A method for forming a semiconductor structure comprising the steps of: selecting a single crystal semiconductor substrate, forming a Sil-xGex buffer layer graded from x =O to x =y where y is in the range from 0.1 to 0.9, forming a symmetrically strained superlattice and comprising alternating layers of Sil-wGew and Sil-zGez, where w is greater thany and where y is greater than z, said alternating layers having corresponding individual thicknesses such that the average Ge composition of the layer is y, said alternating layers having a total thickness in the range from 0.25 μm to 10 μm, forming an additionally thin Sil-yGey layer, forming a quantum well layer, forming an undoped Sil-yGey spacer layer, formining an n-type doped Sil-zGez supply layer, wherein said symmetrically strained superlattice may function as the absorbing region of a photodetector, and said quantum well layer may function as the conducting channel of a field effect transistor.

48. The method of claim 47 further including the steps of forming a trench or mesa defined isolation regions, forming source and drain electrodes and a Schottky gate contact, and forming two or more interdigitated Schottky electrodes deposited onto the etch exposed surface of Sil-yGey buffer layer.

49. A method for forming a semiconductor structure comprising the steps of: selecting a substrate from the group consisting of Si, SiGe, Ge, GaAs, SiC, SOS, and SOI, forming a Sil-xGex buffer layer graded from x =O to x =y, where y is in the range from 0.1 to 1.0, forming a constant composition layer of relaxed Sil-yGey having a thickness in the range from 0.25 μm to 10 μm, forming a thin Si surface layer, forming a thin gate dielectric, wherein said constant composition layer of relaxed Sil-yGey acts as the absorbing region of a photodetector, and said Si surface layer acts as the conducting channel of a field effect transistor.

50. The method of claim 49 further including the step of forming a trench or mesa defined isolation regions, forming source and drain electrodes and a gate electrode, and forming two or more Schottky electrodes on the surface of the top Si layer to form a photodetector.

51. The method of claim 49 wherein said steps of forming said transistor source and drain electrodes and the photodetector Schottky electrodes include the step of forming one of a metal silicide and a metal germanosilicide.

52. A method for forming a semiconductor structure comprising the steps of forming a single crystal semiconductor substrate, forming a Sil-xGex buffer layer graded from x =O to y where y is in the range from 0.1 to 0.9, forming a layer of relaxed Sil-yGey having a thickness in the range from 0.25 μm to 10 μm, forming an n-type doped Sil-yGey supply layer, forming a first undoped Sil-yGey layer, forming a first quantum well layer which acts as an electron channel for an NMOS FET, forming a second undoped Sil-yGey offset layer, forming a second quantum well layer which acts as a hole channel for a PMOS FET, forming a third undoped Sil-yGey offset layer, forming an undoped Si layer, forming a gate dielectric and foming a gate electrode layer whereby NMOS FET's and PMOS FET's may be formed by forming the respective n-type and p-type drain and source regions.