Skew management in cables and other interconnects

Abstract

Transmit-side active signal management circuitry applies one or more active signal management processes to a digital signal at a transmit side of an interconnect. At the receive side of the interconnect, receive-side active signal management circuitry applies one or more corresponding active signal management processes, as appropriate, to the received digital signal to recover the information represented by the original digital signal. The interconnect can include a cable used to transmit the signals between a source device and a destination device, whereby one or both of the transmit-side active signal management circuitry and the receive-side active signal management circuitry is implemented at a corresponding cable receptacle of the cable. Alternately, one or both of the transmit-side active signal management circuitry and the receive-side active signal management circuitry can be implemented at a cable adaptor, thereby permitting the use of a passive cable interconnect to transmit the signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings. The use of the same reference symbols in different drawings indicates similar or identical items.

FIG. 1 is a block diagram illustrating a signal management system for improving transmitted signal quality and reach and reducing electromagnetic interference (EMI) in accordance with at least one embodiment of the present disclosure.

FIG. 2 is a diagram illustrating the signal management system of FIG. 1 implemented in a cable in accordance with at least one embodiment of the present disclosure.

FIG. 3 is a perspective view diagram illustrating a cable receptacle of the cable assembly of FIG. 2 in accordance with at least one embodiment of the present disclosure.

FIG. 4 is a diagram illustrating the signal management system of FIG. 1 as implemented in a cable adaptor in accordance with at least one embodiment of the present disclosure.

FIG. 5 is a perspective view diagram illustrating the cable adaptor of FIG. 4 in accordance with at least one embodiment of the present disclosure.

FIG. 6 is a block diagram illustrating an implementation of active signal management circuitry utilizing quasi differential to true differential signal conversion in accordance with at least one embodiment of the present disclosure.

FIG. 7 is a block diagram illustrating an implementation of active signal management circuitry utilizing quasi differential to true differential signal conversion in accordance with at least one embodiment of the present disclosure.

FIG. 8 is a block diagram illustrating an implementation of active signal management circuitry utilizing encoding and quasi differential to true differential signal conversion in accordance with at least one embodiment of the present disclosure.

FIG. 9 is a block diagram illustrating an implementation of active signal management circuitry utilizing true differential to quasi differential signal conversion and decoding in accordance with at least one embodiment of the present disclosure.

FIG. 10 is a block diagram illustrating an implementation of active signal management circuitry utilizing deserialization-serialization and encoding in accordance with at least one embodiment of the present disclosure.

FIG. 11 is a block diagram illustrating an implementation of active signal management circuitry utilizing deserialization-serialization and decoding in accordance with at least one embodiment of the present disclosure.

FIG. 12 is a block diagram illustrating an implementation of active signal management circuitry utilizing a quasi differential receiver and transmitter in accordance with at least one embodiment of the present disclosure.

FIG. 13 is a block diagram illustrating an implementation of active signal management circuitry utilizing a true differential receiver and transmitter in accordance with at least one embodiment of the present disclosure.

FIG. 14 is a circuit diagram illustrating an implementation of a quasi differential signal transmitter in accordance with at least one embodiment of the present disclosure.

FIG. 15 is a circuit diagram illustrating an implementation of a true differential signal transmitter in accordance with at least one embodiment of the present disclosure.

FIG. 16 is a circuit diagram illustrating an implementation of a quasi differential signal receiver in accordance with at least one embodiment of the present disclosure.

FIG. 17 is a circuit diagram illustrating an implementation of a true differential signal receiver in accordance with at least one embodiment of the present disclosure.

FIG. 18 is a circuit diagram illustrating an implementation of a quasi-to-true differential signaling converter in accordance with at least one embodiment of the present disclosure.

FIG. 19 is a circuit diagram illustrating an implementation of a true-to-quasi differential signaling converter in accordance with at least one embodiment of the present disclosure.

FIG. 20 is a diagram illustrating a bidirectional active signal management system employed at respective ends of a cable assembly in accordance with at least one embodiment of the present disclosure.

FIG. 21 is a diagram illustrating an alternate implementation of a bidirectional active signal management system employed at respective ends of a cable assembly in accordance with at least one embodiment of the present disclosure.

FIG. 22 is a diagram illustrating a direction detection module in accordance with at least one embodiment of the present disclosure.

FIG. 23 is a diagram illustrating an implementation of a signal processing path of a bidirectional active signal management system in accordance with at least one embodiment of the present disclosure.

FIG. 24 is a diagram illustrating another implementation of a signal processing path of a bidirectional active signal management system in accordance with at least one embodiment of the present disclosure.

FIG. 25 is a block diagram illustrating an implementation of active signal management circuitry utilizing a bit alignment module in accordance with at least one embodiment of the present disclosure.

FIG. 26 is a block diagram illustrating an implementation of active signal management circuitry utilizing a skew management module in accordance with at least one embodiment of the present disclosure.

FIG. 27 is a block diagram illustrating an implementation of active signal management circuitry utilizing a control symbol encoder/decoder in accordance with at least one embodiment of the present disclosure.

FIG. 28 is a block diagram illustrating an implementation of an EMI encoder/decoder in accordance with at least one embodiment of the present disclosure.

FIG. 29 is a block diagram illustrating an implementation of an EMI encoder/decoder in accordance with at least one embodiment of the present disclosure.

FIG. 30 is a block diagram illustrating an implementation of an EMI encoder/decoder in accordance with at least one embodiment of the present disclosure.

FIG. 31 is a block diagram illustrating an implementation of an EMI encoder/decoder in accordance with at least one embodiment of the present disclosure.

FIG. 32 is a block diagram illustrating an implementation of an EMI encoder/decoder in accordance with at least one embodiment of the present disclosure.

FIG. 33 is a block diagram illustrating an implementation of an EMI encoder/decoder in accordance with at least one embodiment of the present disclosure.

FIG. 34 is a block diagram illustrating an implementation of an EMI encoder/decoder in accordance with at least one embodiment of the present disclosure.

FIG. 35 is a block diagram illustrating an implementation of an EMI encoder/decoder in accordance with at least one embodiment of the present disclosure.

FIG. 36 is a block diagram illustrating an implementation of an EMI encoder/decoder in accordance with at least one embodiment of the present disclosure.

FIG. 37 is a block diagram illustrating an implementation of an EMI encoder/decoder in accordance with at least one embodiment of the present disclosure.

FIG. 38 is a block diagram illustrating an implementation of an EMI encoder/decoder in accordance with at least one embodiment of the present disclosure.

FIG. 39 is a block diagram illustrating an implementation of an EMI encoder/decoder in accordance with at least one embodiment of the present disclosure.

FIG. 40 is a state machine diagram illustrating an operation of an EMI encoder/decoder in accordance with at least one embodiment of the present disclosure.

Claims

1. A method comprising: receiving a plurality of digital signals;for each digital signal of the plurality of digital signals: bit shifting the digital signal into a shift register of the integrated circuit to determine a data symbol of the digital signal;buffering the data symbol in one of a plurality of buffers corresponding to the digital signal; andconfiguring one of a plurality of buffer signals corresponding to the digital signal to have a first state in response to buffering the data symbol; andconcurrently accessing the data symbol from each of the plurality of buffers in response to each of the buffer signals of the plurality of buffer signals having the first state.

2. The method of claim 1, further comprising: for each digital signal of the plurality of digital signals: configuring the buffer signal corresponding to the digital signal to have a second state in response to accessing the data symbol from the buffer corresponding to the digital signal.

3. The method of claim 1, further comprising: concurrently performing a signal management process for each accessed data symbol.

4. The method of claim 1, further comprising: concurrently providing each digital signal of a second plurality of digital signals for transmission via a corresponding one of a plurality of conductive interconnects, each digital signal of the second plurality of digital signals including a data symbol based on corresponding one of the data symbols concurrently accessed from the plurality of buffers.

5. An apparatus comprising: a first plurality of ports, each port configured to receive a corresponding digital signal of a first plurality of digital signals;a plurality of bit shift registers, each bit shift register comprising an input coupled to a corresponding one of the first plurality of ports and an output configured to provide a data symbol of the corresponding digital signal of the first plurality of digital signals;a plurality of buffers, each buffer comprising a first input coupled to the output of a corresponding one of the plurality of bit shift registers, a second input configured to receive an alignment signal, a first output configured to provide a buffering signal, and a second output configured to provide a buffered data symbol in response to the alignment signal indicating an aligned state, wherein each buffer is configured to configure the corresponding buffering signal to indicate a data buffered state in response to buffering the data symbol from the corresponding bit shift register; andan alignment controller comprising a plurality of inputs, each input coupled to the first output of a corresponding one of the plurality of buffers to receive the corresponding buffering signal, and an output configured to configure the alignment signal to indicate the aligned state in response to each buffering signal for each of the plurality of buffers indicating the data buffered state.

6. The apparatus of claim 5, further comprising: a plurality of conductive interconnects, each conductive interconnect coupled to the second output of a corresponding buffer of the plurality of buffers.

7. The apparatus of claim 6, further comprising: a plurality of active signal management circuitry, each active signal management circuitry comprising an input coupled to the second output of a corresponding buffer of the plurality of buffers, and an output coupled to a corresponding conductive interconnect of the plurality of conductive interconnects.

8. The apparatus of claim 7, wherein the apparatus comprises: a cable body comprising the plurality of conductive interconnects; anda cable receptacle coupled to an end of the cable body, the cable receptacle comprising the first plurality of ports, the plurality of bit shift registers, the plurality of buffers, and the alignment controller.

9. The apparatus of claim 6, wherein the apparatus comprises: a cable body comprising the plurality of conductive interconnects; anda cable receptacle coupled to an end of the cable body, the cable receptacle comprising the first plurality of ports, the plurality of bit shift registers, the plurality of buffers, and the alignment controller.

10. The apparatus of claim 9, wherein the cable receptacle comprises one of: a Digital Video Interface (DVI) compatible cable receptacle; a High Definition Multimedia Interface (HDMI) compatible cable receptacle; a DisplayPort compatible cable receptacle; a Universal Display Interface (UDI) compatible cable receptacle; a Universal Serial Bus (USB) compatible cable receptacle; and a FireWire compatible cable receptacle.

11. The apparatus of claim 5, further comprising: a shift register to store N bits of a digital signal;M symbol decoders, each decoder comprising an input to receive an X bit value from a corresponding X bit sequence of the N bits of the shift register, and an output to provide corresponding one of a plurality of symbol detected signals, each decoder configured to provide a first state for the corresponding symbol detected signal in response to detecting a predetermined symbol from the corresponding X bit values;a multiplexer comprising a plurality of data inputs, a control input, and a data output, each data input configured to receive a corresponding X bit value from a corresponding X bit sequence of the N bits of the shift register, wherein the multiplexer is configured to provide one of the received X bit values based on a value received at the control input; anda 1-of-M decoder comprising a plurality of inputs, each input coupled to the output of a corresponding one of the M symbol decoders, and an output coupled to the control input of the multiplexer, wherein the 1-of-M decoder is configured to output a value associated with the symbol decoder of the M symbol decoders having a corresponding symbol detected signal having the first state.

12. The apparatus of claim 11, wherein the predetermined symbol is a video symbol.

13. The apparatus of claim 11, wherein the predetermined symbol a video sync control symbol.