Slew rate control circuit

Abstract

A bi-directional communication system includes a driver capable of controlling a slew rate of transmitted data signals. Impedance matching can be provided to match an impedance of a driver circuit to an impedance of a communication line. The impedance is maintained constant as data is driven from the data driver. The data receiver circuit can adjust a reference voltage in response to simultaneously transmitted data. The slew rate of the receiver circuit trip point is controlled to maintain adequate noise margin during operation. Both the receiver and driver circuits can be controlled using a delay line circuit.

Description

TECHNICAL FIELD OF THE INVENTION

[0002] The present invention relates generally to circuit output drivers and in particular the present invention relates to a circuit for controlling slew rates.

BACKGROUND OF THE INVENTION

[0003] Integrated circuits can be provided to communicate data over a communication bus. The integrated circuits include both a data transmitter, or driver circuit, and a receiver circuit. Communicating data signals on the communication bus can be complicated and is the subject of extensive studies relating to transmission lines. To reduce data signal ringing and signal interference, the rise time or slew rate of a signal transmitted on the data bus is often controlled. In addition, an impedance mismatch between the integrated circuit driver and the communication bus can increase the signal ringing and interference. As such, it is common to employ techniques to reduce impedance mismatch.

[0004] In addition to controlling data communication slew rate and driver circuit impedance matching, a reduction in the communication bus lines is desired. That is, two data lines can be provided between integrated circuits. One data line communicates in a first direction, while the second data line is used for data communication in an opposite second direction. It is desired to reduce the two data lines by using a single data communication line. By using a single data line which communicates data in two directions simultaneously, signal interference between the two data signals creates additional difficulties in reliable data communication. As such, reference circuitry can be used to subtract a data signal, which is being transmitted, from the data signal received to isolate the received data.

[0005] For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a bidirectional data communication circuit which can provide slew rate control on transmitted data and maintain adequate noise margin on received data signals.

SUMMARY OF THE INVENTION

[0006] In one embodiment, a data communication circuit comprises a delay line circuit coupled to receive an output data signal. The delay line circuit includes a plurality of output connections for providing the output data signal, where a signal provided on each of the plurality of output connections is delayed from a previous one of the plurality of output connections. A data driver circuit is provided which comprises a plurality of stage circuits coupled to the plurality of output connections of the delay line circuit such that a slew rate of a data signal transmitted by the data driver circuit can be controlled by the delay line circuit. A data receiver circuit is coupled to the delay line circuit. A slew rate of a reference voltage signal coupled to the data receiver circuit can be controlled by the delay line circuit such that the slew rate of the data signal transmitted by the data driver circuit and the slew rate of a reference voltage signal are substantially the same.

[0007] In another embodiment, an integrated circuit is provided which comprises an output connection which can be coupled to an external data communication line, and a delay circuit having an input connection for receiving a data signal and a propagation path comprising a plurality of delay circuits. The delay circuit has a plurality of output connections located along the propagation path to provide digital output signals in response to the received data signal. A data driver circuit is coupled to the output connection and the plurality of output connections of the delay circuit. The data driver circuit comprises a plurality of stage circuits which can be selectively activated by the digital output signals to control a slew rate of an output data signal coupled to the output connection and maintain a constant impedance at the output connection while the data signal is transmitted. A data receiver circuit is provided which comprises a first input coupled to the output connection, a second input coupled to receive a first reference voltage signal, and a third input coupled to receive a second reference voltage signal. The data receiver circuit further comprises slew rate control circuitry coupled to the plurality of output connections of the delay circuit to control a slew rate of a trip point between the first and second reference voltage signals.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1 is a simplified block drawing of a communication system according to the present invention;

[0009] FIGS. 2 a and 2b illustrate data transmission signals and receiver trip point voltage levels;

[0010] FIG. 3 illustrates an ideal controlled slew rate CMOS driver circuit;

[0011] FIG. 4 illustrates a driver circuit which includes a slew rate control circuit system according to the present invention;

[0012] FIG. 5 illustrates an output signal provided by the driver circuit of FIG. 4;

[0013] FIG. 6 illustrates a driver circuit which includes a digital impedance control circuit according to the present invention; and

[0014] FIG. 7 illustrates a receiver circuit which includes reference circuit according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0015] In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the inventions may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the spirit and scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the claims.

[0016] The present invention allows control of a communication line driver slew rate, or transition time, for a digital communication system. By controlling the slew rate, the frequency content of signals on the communication system is limited, and driver circuit power delivery (di/dt) is controlled. As described in greater detail below, a digital circuit and method are provided for controlling a slew rate on a communication line, in combination with a digital impedance control scheme. An impedance of the driver circuit is controlled to remain relatively constant throughout the driver signal transition. Further, the slew rate of a driver circuit, and an input circuit reference level track each other such that simultaneous bidirectional signal communication can be performed on a common communication line.

[0017] Adjusting a slew rate of a driver circuit is affected by several system constraints. One constraint is the impedance differential between a driver circuit and the communication, or transmission line, which the driver circuit is coupled to. In some traditional circuits, source termination is provided to match an impedance of the driver circuit to the communication line. The impedance, however, needs to be maintained throughout the transition of a signal coupled to the communication line. That is, the impedance matching to the communication line should be maintained while controlling a slew rate of a signal transmitted on the communication line.

[0018] Referring to FIG. 1, a simplified block drawing of a communication system 100 according to the present invention is described. The system includes two communication circuits 102 and 104 which communicate over a common interconnect line 106. Each communication circuit includes a driver 110 and a receiver 112. The reference circuit is coupled to receive signals transmitted over the interconnect line and is coupled to a reference circuit 114 which provides a trip point to receiver 112. This configuration allows transmission of data simultaneously in both directions over the communication line. In order to decode the data, the trip point of the receiver is dynamically adjusted when outgoing data is provided. It is noted, that the impedance of the driver circuit should match the impedance of the communication line while the driver is switching output states. Further, the slew rate of the driver circuit should match the slew rate of the receiver circuit trip point to maintain an adequate noise margin for the receiver.

[0019] This is illustrated more clearly with reference to FIGS. 2a and 2b. FIG. 2a illustrates a system where data transmitted on a communication line transitions from a low state to a high state while the receiver circuit trip point transitions from a first reference voltage to a second reference voltage. Because the transition rate, or slew rate, of the two signals do not match, a noise margin during the transition period of the data approaches zero. In contrast, FIG. 2b illustrates a communication circuit where a receiver circuit trip point and a driver circuit slew rate match. As illustrated, a uniform noise margin (differential) is maintained between the two signals during simultaneous operation.

[0020] Prior to further describing the present invention, reference is made to FIG. 3 which illustrates an ideal controlled slew rate CMOS driver circuit 120. The circuit includes an ideal voltage source 122 coupled in series with a resistor of value Z0, which is equal to an impedance of the communication line which is coupled to the driver circuit. A voltage divider (R1 and R2) are connected to the same voltage source and provide the threshold voltage level, or trip point, of the receiver circuit. The circuit of FIG. 3 maintains a correct impedance throughout signal transitions, and the rate of change of the receiver's trip point matches the driver transition.

[0021] Referring to FIG. 4, a driver circuit 200 is illustrated which includes a slew rate control circuit. The driver circuit includes a plurality of push-pull driver circuits 202_0 to 202_n. Each push-pull driver circuit includes a pull-up transistor 204, a pull-up resistor 206, a pull-down resistor 208, and a pull-down transistor 210. The series resistors of each push-pull driver circuit have a resistance which is relatively large in relation to an impedance of the transistors. As such, the series coupled resistors 206 and 208 dominate the series impedance, and the push-pull driver circuit has good linearity from power rail to power rail. The resistors can be fabricated from any suitable structure, such as an N-well layer of a standard CMOS process.

[0022] The number of push-pull driver circuits provided in driver circuit 200 is determined by a number of taps provided by a delay line circuit 220. That is, delay line circuit 220 includes a plurality of delay stages which are tapped to provide a number of delayed signals. In the embodiment illustrated in FIG. 4, the delay line circuit has four taps. By controlling the delay time between each tapped signal, the driver circuit can approximate the ideal slew rate control circuit of FIG. 3. FIG. 5 illustrates an output signal provided by driver circuit 200 in response to a driver circuit input signal low to high transition. The output signal transitions from ground to VCC in a plurality of discrete steps. The number of steps corresponds to the number (n) of push-pull driver circuits provided in the driver circuit. The output signal can be filtered to provide a linear signal, as illustrated by a dotted line in FIG. 5.

[0023] Delay line 220 can be implemented in several ways. In one embodiment, the delay line can be implemented as a string of inverter circuits. This embodiment provides a resolution between consecutive tap output signals of two inverter delays. Two strings of inverters can be provided to achieve a resolution of one inverter, one driven by input data and the other driven by an inverse of the input data. In either embodiment, jitter may be experienced through the driver circuit that is close to jitter of a standard CMOS output circuit. To reduce this jitter, the delay line circuit can be coupled to receive a delay control signal from a delay locked loop circuit 224. The delay of the delay circuit, therefore, is locked to a clock signal and remains stable with respect to process, voltage, and temperature variations. Further, low-to-high and high-to-low signal transitions in the tap output signals are equal.

[0024] The above described driver circuit 200 provides a circuit and method for controlling slew rate of an output driver. As described with reference to FIG. 6, the outputs from delay line circuit 220 can be used to provide a driver circuit 300 which includes a digital impedance control circuit. Driver circuit 300 includes a plurality of binary weighted legs, and push-pull circuits as described above. The number of legs corresponds to the number of taps provided by delay line circuit 220. In the embodiment of FIG. 6, therefore, four legs 302_0 to 302_n are provided in the driver circuit. The impedance of the driver circuit is controlled by selectively changing the device width. To control the driver circuit, complementary enable signals (en_0 to en n) are used to selectively enable legs of the circuit. Each leg is weighted using a unit size transistor segment which is replicated to form larger legs. That is, leg 302_0 comprises a single pull-up and pull-down transistor, and leg 302_1 comprises two pull-up and pull-down transistors. The third leg includes four transistors, and the fourth leg comprises eight transistors. As such, each leg increases in a binary fashion using unit size transistors. It will be appreciated, that the fourth leg can comprise four transistors which are weighted at 2× the unit transistor size.

[0025] Each leg of the driver circuit includes at least one push-pull circuit with linearizing resistors. Logic gates that respond to outputs from delay line circuitry 220 (FIG. 4) and enable signals provided by a control circuit 320 control the push-pull circuits. For example, leg 302_0 includes a NAND gate 306 which provides a control signal to the gate of pull up transistor 307. The logic gate is controlled in response to an enable signal, En0, and tap0 output from the delay line circuit. Likewise, a logic NOR gate 308 is provided to control pull-down transistor 309 in response to tap0 and an enable signal, /Enb0. Each leg of the driver circuit is controlled in response to the tap outputs of the delay line circuit. To provide a higher resolution in controlling both slew rate and impedance control, it is suggested to use as many taps as possible for each leg of the driver circuit. It is noted that the smaller legs, however, which comprise less than four segments, require a compromise using the delay line output circuit signals. In the embodiment illustrated, leg 302_1 is coupled to the middle two taps (tap_1, tap_2), while leg 302_0 is coupled to tap_0. In one embodiment, leg 302_0 can be filtered to be ¼ the bandwidth of the other legs. Alternately, the smaller legs can be divided into smaller segments which use all of the tap output signals, however, a minimum transistor size may prevent implementation of that embodiment.

[0026] The driver circuit of FIG. 6, therefore, provides both slew rate control and impedance matching by using a delay line circuit and logic enable circuitry. It will be appreciated by those skilled in the art after studying the present description that the sizes of the pull-up and pull-down transistors can be selected to fine-tune the incremental signal steps provided on the communication line output. In operation, control logic circuitry 320 sets the enable, and delay line 220 alternately disables a pull-up transistor and activates a pull-down transistor. Likewise, a pull-up transistor is enabled in sequence with disabling a pull-down transistor. By controlling the transistors in this manner, a more linear transition can be experienced on output connection 330 which is coupled to the external communication line.

[0027] The above described driver circuits provide control over slew rate, and the combination of trip point slew rate and impedance matching. Referring to FIG. 7, a receiver circuit as described which includes reference circuitry that adjusts to compensate for data communicated by the driver circuit. The receiver circuit includes an input connection 422 coupled to the external data communication line 106 for receiving an input signal. The input signal is coupled to a gate connection of transistor 402. The receiver circuit is configured as a differential amplifier which receives a reference voltage signal on a gate connection of a reference transistor(s). In the embodiment illustrated, the receiver circuit includes a plurality of reference transistors 404_0-404_n which receives a first reference voltage level, and a second plurality of reference transistors 408_0-408_n which receives a second reference voltage level. The different voltage levels are used as a reference voltage for the receiver, and depend upon a state of data which is being transmitted by the driver circuit. That is, Ref_a is used when the driver is transmitting a data zero, and Ref_b is used when the driver is transmitting a data one.

[0028] The reference transistors 404_0-404_n and 408_0-408_n are coupled to transistors 406_0- 406n and 410_0-410_n, respectively. Transistors 406 are selectively activated by the tap outputs of the delay circuit. Transistors 410 are selectively activated using the complement of the tap outputs. The transistors are controlled so that when one of transistors 406 are turned off, one of transistors 410 is activated. Likewise, when a transistor 410 is tuned off, a transistor 406 is activated. This operation controls the slew rate of the receiver circuit trip point between two reference levels. It is noted that the combined size of transistors 406_0-406_n are equal to the size of transistor 414, and the combined size of transistors 410_0-410_n are also equal to the size of transistor 414. Likewise, the combined size of either transistors 404_0-404_n or 408_0-408_n are equal to the size of transistor 402. As such, the transition time of the trip point of the comparator is controlled by transistors 406 and 410 via the delay line circuit.

Conclusion

[0029] A bidirectional communication system has been described which includes a driver capable of controlling a slew rate of transmitted data signals. Circuitry has also been described which matches an impedance of a driver circuit to an impedance of a communication line. The impedance is maintained constant as data is driven from the data driver. A data receiver circuit of the system has been described which adjusts a reference voltage of the receiver in response to simultaneously transmitted data. The slew rate of the receiver circuit trip point between reference voltages is controlled to maintain adequate noise margin during operation. Both the receiver and driver circuits can be controlled using a delay line circuit.

[0030] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.

Claims

1. An apparatus comprising: a delay line circuit to provide a plurality of binary control signals in response to receiving a first data signal; and a driver circuit responsive to the plurality of binary control signals to adjust a slew rate of an output signal to be provided by the driver circuit.

2. The apparatus of claim 1, wherein the driver circuit is further responsive to the binary control signals to maintain a substantially constant impedance during transitions of the output signal.

3. The apparatus of claim 1, wherein the driver circuit includes a plurality of binary weighted stage circuits, the plurality of binary weighted stage circuits to be selectively activated in response to the plurality of binary control signals.

4. The apparatus of claim 3, wherein at least one of the plurality of binary weighted stages includes at least one push-pull circuit.

5. The apparatus of claim 1, wherein the delay line circuit includes a plurality of output connections to provide the binary control signals, each of the binary control signals having a different delay relative to the other binary control signals.

6. The apparatus of claim 5, further including a synchronous delay locked loop circuit to control a delay between the binary control signals.

7. The apparatus of claim 5, wherein the delay line circuit includes a plurality of stage circuits, each of the plurality of stage circuits being coupled to at least one of the plurality of output connections.

8. The apparatus of claim 1, further including a receiver circuit responsive to the plurality of binary control signals to adjust a slew rate of a receiver trip point.

9. An apparatus comprising: a delay line circuit; and a data receiver circuit responsive to the delay line circuit to control a slew rate of a receiver trip point to be substantially the same as a slew rate of a data signal received by the data receiver circuit.

10. The apparatus of claim 9, wherein the data receiver circuit includes a differential amplifier configured to receive two reference levels to control the slew rate between the two reference levels.

11. The apparatus of claim 9, further including a driver circuit responsive to the delay line circuit to control a slew rate of an output data signal to be transmitted over a bi-directional transmission line.

12. The apparatus of claim 11, wherein the driver circuit is responsive to the delay line circuit to maintain a substantially constant impedance during transitions of the output signal.

13. An apparatus comprising: a delay line circuit responsive to a data signal to provide a plurality of control signals; a driver circuit responsive to the plurality of control signals to control a slew rate of an output signal; and a data receiver circuit responsive to the plurality of control signals to adjust a slew rate of a receiver trip point to be substantially equal to the slew rate of the output signal.

14. The apparatus of claim 13, wherein the delay line circuit includes a delay locked loop circuit to provide a delay control signal.

15. The apparatus of claim 13, wherein the driver circuit includes a plurality of stage circuits responsive to the plurality of control signals.

16. The apparatus of claim 15, wherein the plurality of stage circuits is further responsive to a plurality of enable signals from a logic control.

17. The apparatus of claim 13, wherein the data receiver circuit includes a plurality of reference transistors, each reference transistor coupled to a transistor responsive to a separate one of the plurality of control signals.

18. The apparatus of claim 13, wherein the driver circuit is further responsive to maintain substantially constant impedance throughout signal transition to transmit the output signal as one signal of a simultaneous bidirectional signaling configuration.

19. A method comprising: providing a plurality of binary control signals from a delay line circuit in response to receiving a data signal; and adjusting a slew rate of an output signal from a driver circuit in response to the binary control signals.

20. The method of claim 19, wherein providing a plurality of binary control signals from a delay line circuit includes tapping the delay line circuit after each of a plurality of delays.

21. The method of claim 19, wherein the method further includes maintaining an impedance of the driver circuit substantially constant throughout transitions of the output signal.

22. The method of claim 19, wherein adjusting the slew rate of an output signal includes tracking a circuit reference level to provide simultaneous bidirectional signal communication on a single communication line.

23. A method comprising: providing a plurality of binary control signals from a delay line circuit in response to receiving a data signal; and adjusting a slew rate of a receiver trip point in response to the binary control signals to substantially match a slew rate of an output signal from a driver.

24. The method of claim 23, wherein providing a plurality of binary control signals from a delay line circuit includes locking a delay of the delay line circuit to a clock signal.

25. The method of claim 23, wherein the method further includes maintaining an impedance of the driver substantially constant throughout transitions of the output signal.

26. The method of claim 23, wherein adjusting a slew rate of a receiver trip point includes adjusting a reference voltage of the receiver in response to the binary control signals to provide simultaneous bidirectional signal communication.

27. An apparatus comprising: a transmission line having a first impedance; an output driver coupled to the transmission line, the output driver including a delay line circuit responsive to a data signal to provide a plurality of control signals, and a data driver circuit responsive to the control signals to control a slew rate of an output signal and to maintain an impedance of the output driver at a substantially constant value that is substantially equal to the first impedance of the transmission line.

28. The apparatus of claim 27, wherein the delay line circuit includes a plurality of output connections to provide the plurality of control signals, each of the control signals having a different delay relative to the other control signals.

29. The apparatus of claim 27, wherein the data driver circuit includes a plurality of stage circuits responsive to the plurality of controls signals to maintain substantially constant impedance throughout signal transition of the output signal for simultaneous bi-directional signaling.

30. The apparatus of claim 27, wherein the apparatus further includes a data receiver circuit responsive to the control signals to control a slew rate of a trip point of the data receiver, the slew rate of the trip point substantially equal to the slew rate of the output signal to provide for simultaneous bi-directional signaling.

31. The apparatus of claim 27, wherein the transmission line is configured to transmit simultaneous bidirectional signals.

32. An apparatus comprising: an output to couple to a data communication line; a delay line circuit having an input to receive a data signal and having a plurality of delay stages, each delay stage having a tap; and a driver circuit having a plurality of legs coupled to the output, each leg including: a pull-up transistor in series with a pull-up resistor, the pull-up transistor coupled between an upper supply voltage node and the pull-up resistor, the pull-up resistor coupled between the pull-up transistor and the output; and a pull-down transistor in series with a pull-down resistor, the pull-down transistor coupled between the pull-down resistor and a lower supply voltage node, the pull-down resistor coupled between the output and the pull-down transistor, wherein a gate of the pull-down transistor is coupled to a gate of the pull-up transistor and to one tap of the plurality of taps.

33. The apparatus of claim 32, wherein the pull-down transistor and the pull-up transistor in each leg are structured as a CMOS circuit.

34. The apparatus of claim 32, wherein the plurality of legs is a plurality of binary weighted legs such that a nth leg, n≧0, includes 2n pairs of pull-down and pull-down transistors.

35. The apparatus of claim 34, wherein the gate of each pull-up transistor is coupled to an output of one of a plurality of NAND gates, each NAND gate having a first input coupled to one of the plurality of taps and having a second input coupled to a logic control, the logic control configured to provide enable signals, and the gate of each pull-down transistor is coupled to an output of one of a plurality of NOR gates, each NOR gate having a first input coupled to one of the plurality of taps and a second input coupled to the logic control.

36. The apparatus of claim 32, wherein a kth leg, k>0, includes 2k-I pairs of pull-up and pull-down transistors, each transistor in the kth leg being twice a unit transistor size of the zeroth leg.

37. An apparatus comprising: a delay line circuit having an input to receive a data signal to be transmitted and having a plurality of delay stages, each delay stage having a tap; a receiver circuit having an input to couple to a transmission line, the receiver circuit configured as a differential amplifier including: an output node resistively coupled to a upper voltage node; an input transistor having a gate coupled to the input of the receiver circuit, the input transistor in series between a first transistor and a second transistor, the first transistor coupled between the input transistor and a first resistor, the first resistor transistor coupled to the upper voltage node, the second transistor coupled between the input transistor and a lower voltage node, the second transistor coupled to the input transistor at a first node; a first plurality of reference transistors, each reference transistor of the first plurality of reference transistors coupled to the first node, a gate of each reference transistor of the first plurality of reference transistors coupled to a first reference node; a second plurality of reference transistors, each reference transistor of the second plurality of reference transistors coupled to the first node, a gate of each reference transistor of the second plurality of reference transistors coupled to a second reference node; a first plurality of control transistors, each control transistor of the first plurality of control transistors in series with one reference transistor of the first plurality of reference transistors, the series combination of each control transistor of the first plurality of control transistors and the one reference transistor of the first plurality of reference transistors coupled between the output node and the first node, each control transistor of the first plurality of control transistors coupled to the output node, a gate of each control transistor of the first plurality of control transistors coupled to one tap of the plurality of taps; and a second plurality of control transistors, each control transistor of the second plurality of control transistors in series with one reference transistor of the second plurality of reference transistors, the series combination of each control transistor of the second plurality of control transistors and the one reference transistor of the second plurality of reference transistors coupled between the output node and the first node, each control transistor of the second plurality of control transistors coupled to the output node, a gate of each control transistor of the second plurality of control transistors coupled to one inverted tap of a plurality of inverted taps, wherein the plurality of inverted taps equals the plurality of taps, a signal at an inverted tap being the complement of a signal at a corresponding tap.

38. The apparatus of claim 37, wherein the first reference node is associated with a driver transmitting a data zero and the second reference node is associated with the driver transmitting a data one.

39. The apparatus of claim 37, wherein the first plurality of control transistors and the second plurality of control transistors are configured such that an on/off state of the first plurality of control transistors is opposite to the on/off state of the second plurality of control transistors, the first plurality of control transistors equal to the second plurality of control transistors.

40. The apparatus of claim 37, wherein a combined size of the first plurality of control transistors is equal to the combined size of the second plurality of control transistors, which is equal to the size of the first transistor.

41. The apparatus of claim 41, wherein a combined size of the first plurality of reference transistors is equal to the combined size of the second plurality of reference transistors, which is equal to the size of the second transistor.