Slicer with large input common mode range

Abstract

A slicer with large input common mode range is provided. The slicer includes an input stage coupled to receive an input signal, a current source for providing current for the input stage, a self-biased load coupled to the input stage to provide an initial output signal, and an inverter for inverting the initial output signal to provide a final output signal. The input stage includes a first circuit including a plurality of transistors and a complimentary circuit including a plurality of transistors. When a low common mode input voltage causes the transistors of the first circuit to turn off, the transistors of the complimentary circuit will take over to accomplish the same task as the first circuit.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to signal processing and, more specifically, a signal slicer with large input common mode range.

2. Description of the Related Art

A comparator is a circuit, such as a differential amplifier, that compares two inputs and produces an output that is a function of the result of the comparison. A slicer is a type of comparator which converts an analog input signal into a rail-to-rail or digital output signal.

The slicer may incorporate a threshold detection mechanism to generate a digital high or low output signal when the value of the input signal corresponds to a high or low threshold value. A conventional differential slicer generates a high or low output signal based on the zero crossing of the differential input signal.

A conventional slicer may incorporate a self-biasing resistor and an AC coupling capacitor. The capacitor removes the DC component of the input signal, and the self-biasing property of the inverter adjusts the DC level of the input signal to a level that causes the output of the inverter to switch when the input signal is at the appropriate level.

Traditionally, a slicer may require relatively large capacitors and resistors, and may not efficiently process low frequency signals. Therefore, there is a need for enhanced slicing circuits.

BRIEF DESCRIPTION OF THE DRAWINGS

For proper understanding of the invention, reference should be made to the accompanying drawings, wherein:

FIG. 1 illustrates a method according to one embodiment of the present invention;

FIG. 2 illustrates a block diagram of a slicer according to one embodiment of the present invention;

FIG. 3 illustrates a schematic diagram according to one embodiment of the present invention; and

FIG. 4 illustrates a schematic diagram according to another embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

The present invention provides, according to one embodiment, a slicer with large input common mode range. The slicer converts an analog input signal into a rail-to-rail or digital output signal. The common mode signal refers to the average of the p-side and n-side of a differential signal. While common mode rejection is a term used to describe the ability of a differential amplifier to reject, suppress, or zero-out common mode signals.

Conventional slicer circuits may require relatively large capacitors and resistors, while not providing efficient processing of low frequency signals. The present invention, on the other hand, provides the advantage of reduced die area in combination with a large input common mode range which is normally exhibited by AC coupled buffers.

The present invention provides, according to one aspect, a self-biasing signal slicer. The slicer may include an input stage coupled to receive an input signal, a current source configured to provide current for the input stage, a self-biased load coupled to the input stage to provide an initial output signal, and an inverter configured to invert the initial output signal to provide a final output signal. The input stage may include a first circuit including a plurality of transistors and a second circuit including a plurality of transistors.

According to another aspect of the invention, a method of slicing an input signal is provided. The method may include the steps of receiving an input signal at an input stage, providing a current to the input stage, generating an initial output signal in conjunction with a self-biased load, and inverting the initial output signal to provide a final output signal. The step of receiving an input signal may include receiving an input signal at an input stage. The input stage may include a first circuit including a plurality of transistors and a second circuit including a plurality of transistors. Additionally, the input stage may include a differential transistor pair, while the self-biased load may include a transistor pair with coupled gate leads. The method may further include the steps of providing a common mode signal at the coupled gate leads, and biasing the current source in accordance with the common mode signal.

FIG. 2 illustrates a block diagram according to one aspect of the present invention. Specifically, FIG. 2 illustrates a slicer 200 with large input common mode range. The slicer 200 includes a differential input stage 220, a self-biased load 240, a self-biased current source 230, and a matched inverter 250. The slicer receives a differential input signal from an analog circuit 210 via input leads 211, 212. The current source 230 provides current for the input stage via leads 231, 232. In conjunction with the self-biased load 240, the input stage 220 generates an initial output signal on leads 221, 222. A common mode connection 270 is provided between the self-biased load 240 and the self-biased current source 230. A matched inverter 250 inverts the signals from leads 221, 222 to provide output signals 251, 252 to a digital circuit 260. The self-biased output signal 221, 222 adjusts the DC level of the inverter 250.

According to an embodiment of the invention, a common mode signal is generated by the self-biased load 240. The common mode signal may control the magnitude of the current provided by the current source 230.

FIG. 1 illustrates a method according to one embodiment of the invention. According to FIG. 1, the method may include the steps of: receiving non-AC coupled differential input signals 100, providing the input signals to an input stage of the slicer 110, providing current from a self-biased current source to the input stage 120, generating an initial output signal via a self-biased load 130, and inverting the initial output signal via an inverter, thereby producing a final output signal 140.

FIG. 3 illustrates a schematic diagram of the present invention according to one embodiment. A differential analog input signal, provided via leads V_inn and V_inp, drives a differential transistor pair M₂, M₃. A current source, including transistor M₁, may provide a tail current for the differential transistor pair M₂, M₃. The load for the differential transistor pair M₂, M₃ includes resistors R₁, R₂ and transistors M₄ and M₅.

The differential output of the differential transistor pair M₂, M₃ is provided to an inverter. The inverter may comprise a plurality of transistors M₆, M₇, M₈, M₉, M₁₀, M₁₁. The output signal is inverted by the transistors of the inverter producing a rail-to-rail output signal at the output V_out. The slicer of the present invention, according to the embodiment illustrated in FIG. 3, does not require an AC coupling capacitor at the input since the biasing of the output inverters is accomplished by the self-biased input stage which includes transistors M₁–M₅ and resistors R₁ and R₂. Such a configuration presents a significant reduction in die area.

FIG. 4 illustrates a schematic diagram of a slicer according to another embodiment of the present invention. A differential analog input signal is provided via leads V_inn and V_inp and drives a differential transistor pair M_2, M₃, as well as the complementary differential transistor pair M₈, M₉. An input stage of the slicer is comprised of a first circuit and a second complementary circuit. The first circuit includes transistors M₁–M₅, and the second circuit includes transistors M₆–M₁₀. A common mode signal CM is provided as an average of the differential input signal. An initial output of the input stage is provided to an inverter. The inverter may include transistors M₁₁–M₁₆. The initial output signal is inverted by the transistors of the inverter producing a rail-to-rail output signal is inverted by the transistors of the inverter producing a rail-to-rail output signal at the output V_out.

The configuration illustrated in FIG. 4 results in a significant increase in the input common mode range of the slicer. The complementary circuit, comprised of transistors M₆–M₁₀, may be utilized to accomplish the same task as transistors M₁–M₅ when the common mode voltage is less than midrail. In other words, when a low common mode input voltage causes transistors M₁–M₅ to turn off, transistors M₆–M₁₀ will serve the same function as transistors M₁–M₅. As a result, the slicer may function like an AC coupled buffer without the use of large AC coupling caps, thereby resulting in a reduction in die area.

The various components of the present invention, as described herein, may be implemented on a single silicon substrate. Alternatively, each of the components may be used in a circuit independently of the other components. As such, a circuit incorporating the slicer of the present invention may include numerous combinations of these components and does not necessarily include all of the components described herein. Additionally, the components of the present invention may be implemented as separate distinct solutions. Further, the present invention may be implemented entirely is software or entirely in hardware. In addition, the present invention may be implemented in a combination of hardware and software. Moreover, the components and functions of the present invention may be connected or coupled in many different ways and may be coupled directly or indirectly.

The various embodiments of the present invention disclosed herein may be incorporated in a variety of circuits. For instance, the slicer may be used in a communications receiver to slice a received signal.

One having ordinary skill in the art will readily understand that the invention as discussed above may be practiced with steps in a different order, and/or with hardware elements in configurations which are different than those which are disclosed. Therefore, although the invention has been described based upon these preferred embodiments, it would be apparent to those of skill in the art that certain modifications, variations, and alternative constructions would be apparent, while remaining within the spirit and scope of the invention. In order to determine the metes and bounds of the invention, therefore, reference should be made to the appended claims.

Claims

1. A self-biasing signal slicer comprising: an input stage coupled to receive an input signal, the input stage comprising a first circuit including a first plurality of transistors and a second circuit including a second plurality of transistors;a current source configured to provide current for the input stage;a self-biased load coupled to the input stage to provide an initial output signal, wherein the self-biased load comprises a transistor pair with coupled gate leads and the self-biased load provides a common mode signal at the coupled gate leads; andan inverter configured to invert the initial output signal to provide an output signal.

2. The slicer of claim 1, wherein the second circuit is utilized when a common mode voltage is less than a midrail voltage.

3. The slicer of claim 1, wherein the input stage comprises a differential transistor pair.

4. The slicer of claim 3, wherein the current source is coupled to source leads of the differential transistor pair.

5. The slicer of claim 3, wherein the self-biased load is coupled to drain leads of the differential transistor pair.

6. The slicer of claim 1, wherein the inverter is matched with the current source and the self-biased load.

7. A method of slicing an input signal, the method comprising the steps of: receiving an input signal at an input stage;providing a current to the input stage;generating an initial output signal which is coupled with a self-biased load, the self-biased load comprising a transistor pair with coupled gate leads; andinverting the initial output signal to provide a final output signal;wherein the step of receiving an input signal comprises receiving an input signal at an input stage comprising a first circuit including a plurality of transistors and a second circuit including a plurality of transistors,wherein the method further comprises providing a common mode signal at the coupled gate leads and biasing the current source in accordance with the common mode signal.

8. The method of claim 7, wherein the step of receiving an input signal comprises receiving an input signal at an input stage comprising a differential transistor pair.

9. The method of claim 7, further comprising matching the inverter with the current source and the self-biased load.

10. A self-biasing signal slicer comprising: receiving means for receiving an input signal at an input stage;current source means for providing a current to the input stage;generating means for generating an initial output signal in conjunction with a self-biased load comprising a transistor pair with coupled gate leads; andinverting means for inverting the initial output signal to provide a final output signal;wherein the receiving means comprises means for receiving an input signal at an input stage, and wherein said input stage comprises a first circuit including a first plurality of transistors and a second circuit including a second plurality of transistors andwherein the slices comprises means for providing a common mode signal at the coupled gate leads and biasing the current source in accordance with the common mode signal.