Patent Application
20250079990
Voltage regulators use an input voltage to generate an output voltage at a regulated level. One type of voltage regulator is a switching regulator in which solid-state switches (e.g., metal oxide semiconductor field effect transistors) are turned on and off. The switches may be coupled to an inductor. When one of the switches is turned on, current through the inductor increases, and when that switch is turned off and another switch is turned on, the inductor current decreases. Switching regulators can be implemented as boost converters, buck converters, etc.
The switching frequency of the converter may be fixed or variable. Further, the duty cycle associated with the control of the switch(es) may be fixed or variable. One type of control technique for switching regulators is current mode control in which a clock is used to turn on a first switch, and the inductor current reaching a threshold signal (either peak or valley threshold) causes the control logic to turn off the first switch and turn on a second switch.
For switching regulators that implement fixed frequency switching and peak current mode control, the peak threshold signal should be slope-compensated when the duty cycle exceeds 50%. For valley mode control, the valley threshold signal should be slope-compensated when the duty cycle is less than 50%.
In one example, a circuit includes a sense circuit and a comparator having a first input and a second input, the first input coupled to the sense circuit. The circuit also includes a first transistor having a control terminal and a current terminal, the current terminal coupled to the second input of the comparator and an amplifier having an input and an output, the input coupled too the control terminal of the first transistor. Additionally, the circuit includes a second transistor having a control terminal and a current terminal, the control terminal coupled to the output of the amplifier and a capacitor having a terminal coupled to the current terminal of the second transistor and to the input of the amplifier.
In an example, a circuit includes a comparator having a first input, a second input, and an output and a slope compensation circuit coupled to the first input of the comparator. The circuit also includes a peak detection circuit coupled to the second input of the comparator. The peak detection circuit includes an amplifier having an input and an output and a transistor having a control terminal and a current terminal, the control terminal coupled to the output of the amplifier and the current terminal coupled to the input of the amplifier. The peak detection circuit also includes a capacitor having a terminal coupled to the current terminal of the transistor and to the input of the amplifier.
In an example, a circuit includes a comparator having a first input, a second input, and an output and a slope compensation circuit coupled to the first input of the comparator. The circuit also includes a peak detection circuit coupled to the second input of the comparator. The peak detection circuit includes an amplifier having an input and an output and a transistor having a control terminal and a current terminal, the control terminal coupled to the output of the amplifier and the current terminal coupled to the input of the amplifier. The peak detection circuit also includes a capacitor having a terminal coupled to the current terminal of the transistor and to the input of the amplifier. Additionally, the circuit includes driver logic having an input, a first output, and a second output, the input coupled to the output of the comparator and a second transistor having a current terminal and a control terminal, the control terminal coupled to the first output of the driver logic. Also, the circuit includes a third transistor having a current terminal and a control terminal, the current terminal coupled to the current terminal of the second transistor and the control terminal coupled to the second output of the driver logic.
For a current mode control switching regulator, an error amplifier amplifies the difference between the output voltage (Vout), or a scaled down version of Vout, and a reference voltage. The output signal from the error amplifier is provided to a control loop to control the timing of the converter's switching transistors to thereby regulate the current through the converter's inductor. Regulating the inductor current regulates the output voltage.
For robust safety protection concerns, over-current protection is desirable for a switching regulator. In some applications, it is helpful to monitor the inductor current to keep track of the load current for the regulator. Because the error signal is used to regulate the inductor current, one technique for providing over-current protection is to limit the maximum level of the error signal. Also, the error signal can be provided to an analog-to-digital converter to facilitate in the implementation of the load current tracking function, as described herein. Some switching regulators implement slope compensation. Slope compensation helps to maintain the converter in a stable operating condition, but the added slope compensation introduces a difference between the error signal and the inductor current. The addition of slope-compensation to the control loop thus makes it difficult to determine at what level the error signal should be limited for over-current protection and provide an accurate signal to implement the load current tracking function.
The embodiments described herein address this problem by sampling the slope signal responsive to the inductor current reaching the peak command (in the case of peak current control) or the valley command (in the case of valley current control). The sampled slope signal is then added into the control loop as an offset to cancel the effect of the addition of slope compensation. In such embodiments, the error signal from the error amplifier more closely represents the inductor current, and thus the error signal can be limited for over-current protection in a more accurate manner.
Types of switching regulators include boost converters, buck converters, buck-boost converters, single-ended primary-inductor converters (SEPICs), etc.
In this example, the HS transistor is a p-channel field effect transistor (PFET), and the LS transistor is an n-channel field effect transistor (NFET). The inductor L1 is coupled between the input terminal 101 (and thus Vin) and the drain of the HS transistor at a switch node (SW). The current through the inductor L1 is designated as IL. The driver logic 125 generates gate signals HS_G and LS_G. Gate signal HS_G is provided to the gate of the HS transistor, and gate signal LS_G is provided to the gate of the LS transistor. In general, HS_G is the logical inverse of LS_G (including some dead time during each change of state of the switching transistors). The source of the LS transistor is coupled to ground (PGND), and thus when the LS transistor is ON, the voltage on the SW node is pulled low toward ground (approximately equal to PGND). When the LS transistor is OFF and the HS transistor is ON, the SW node voltage is forced high.
The error amplifier 115 has a negative input (−) and a positive input (+). The negative input is coupled to resistor R2 and receives Vfb. A reference voltage VFEF is provided to the positive input of the error amplifier 115. The output of the error amplifier 115 provides an output signal, Vea, whose magnitude is proportional to the difference between Vfb and VREF. Transistors M4 and M5 (both NFETs in this example) are included. The gates of transistors M4 and M5 are coupled to the output of the error amplifier and thus receive Vea. Transistor M4 converts Vea to a current lea through resistor R4 to ground. Similarly, transistor M5 converts Vea to a current lea through resistor R5 to ground. Capacitors C1 and C2 and resistor R3 implement a low-pass filter for Vea to compensate for the loop stability.
Sense circuit 110 is coupled to the HS transistor and senses the current through the HS transistor when the HS transistor is ON. The sense circuit 110 includes transistors M1, M2, and M3 (all PFETs in this example). The source of the HS transistor is coupled to the source of transistor M1, and the drain of the HS transistor is coupled to the source of transistor M3. The output terminal 102 is coupled to the drain of the HS transistor. The gates of the HS transistor and transistors M1-M3 are coupled together. The drain of transistor M1 and the source of transistor M2 are coupled together. The current through transistor M1 is designated as I1, and the current through transistor M3 is designated as current I3. Current I1 is a scaled down version of current IL. Accordingly, current I1 is a sense current representation of IL. Numerous other implementations for a current sense circuit are possible as well.
The slope compensation circuit 150 is coupled to the drain of transistor M2 and to the negative (−) input of the comparator 120. In this example, the sense current is slope-compensated. The slope compensation circuit 150 produces a ramp current (ISLP). If Islp=0 and los=0, when the control loop is “closed” (that is, when the control loop has reached a steady state), the control loop will be at a state in which VEA (IEA) is at a level so as to force the voltage on the drain of transistor M1 to be approximately equal to VOUT. Because the SW node voltage is higher than VOUT due to the direction of the current flow of current IL, the drain-to-source voltage (Vds) of the HS transistor is approximately equal to the Vds of transistor M1. Accordingly, current I1 is a scaled-down version of IL. Transistors M2 and M3 are the same size in this embodiment, I1 is equal to lea, and I2 also is equal to lea (assuming Islp and los are both 0 amperes). The Vds of transistor M2 is the same as the Vds of transistor M3. As a result, the control loop will force the voltage on the negative input of comparator 120 to be approximately equal to the voltage on the positive input of the comparator. The addition of the slope current Islp helps to stabilize the operation of the converter but renders Vea (or lea) to be less than an ideal representation of current IL.
During operation, the control loop attempts to make the slope-compensated sense current approximately equal to Iea. If the output voltage deviates from its target regulated level, the sense current will increase or decrease thereby causing the output of comparator 120 to become logic high or low. The driver logic 125 responds by adjusting the duty cycle of the next switching cycle to force Vout to return closer to its target level.
The inductor LI1 is coupled between the input terminal 101 and the drain of the HS transistor at switch node SW. The driver logic 125 generates gate signals HS_G and LS_G. Gate signal HS_G is provided to the gate of the HS transistor, and gate signal LS_G is provided to the gate of the LS transistor. The source of the LS transistor is coupled to PGND.
Sense circuit 110 is coupled to the HS transistor and senses the current through the HS transistor when the HS transistor is ON. The sense circuit 110 includes transistors M1, M2, and M3, and are connected as described above.
The slope compensation circuit 150 is coupled to the drain of transistor M2 and to the negative (−) input of the comparator 120. In this example, the sense current is slope-compensated. The slope compensation circuit 150 produces ramp current (ISLP).
To offset the error introduced by Islp, which slope-compensates the sense current I1, the peak detection sample-and-hold circuit of the converter 200 of
The voltage waveform on the gates of transistors M31 and M32 is VCslp plus the gate-to-source voltage (Vgs) of transistor M31. The voltage on the source of transistor M32 (Vslp) is 1 Vgs below the voltage on the gate of transistor M32. Thus, Vslp is approximately equal to VCslp and has waveform that largely is the same as the VCslp waveform shown in
The peak detection sample-and-hold circuit 210 includes an amplifier 405, a transistor M34, a capacitor C4, and a current source circuit Ilkg. The positive input of amplifier 405 is coupled to the gates of transistors M31 and M32, and thus receive the ramp waveform of VCslp plus the Vgs of transistor M31. The negative input of the amplifier 405 is coupled to the source of transistor M34 and to the gate of a transistor M33. The source of transistor M34 is coupled to the upper plate of capacitor C4 and to the current source circuit Ilkg. The voltage across capacitor C4 is labeled VCcor. The drain of transistor M34 is coupled to Vin.
As the voltage on the positive input of the amplifier 405 increases, transistor M34 turns ON and current flows through the transistor to capacitor C4 to thereby increase the voltage across capacitor C4 (VCcor). Upon the voltage on the positive input of the amplifier suddenly dropping (e.g., at a falling edge 410), the voltage on the negative input of the amplifier does not drop as fast because of the charge on capacitor C4. Accordingly, the output voltage from the amplifier to the gate of transistor M34 is forced low thereby turning OFF transistor M34 and charge current to the capacitor C4. The voltage VCcor thus remains fixed. VCcor increases (tracks) while VCslp (and thus Islp) increases, and is then held at its level when VCslp (and Islp) suddenly falls. Points 420 in
The current source circuit Ilkg is a relatively small current source that provides a discharge current path for capacitor C4 in the event that VCslp changes to a lower voltage. If the ramp voltage decreases over time, some of the charge on capacitor C4 will need to be removed for the voltage VCcor to be reset to the lower corresponding voltage level. Current source Ilkg is a small leakage current source that removes some of the charge on capacitor C4 to reduce its voltage as needed.
In this description, the term “couple” may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B by direct connection; or (b) in a second example, device A is coupled to device B through intervening component C if intervening component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.
A device that is “configured to” perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or reconfigurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof.
As used herein, the terms “terminal”, “node”, “interconnection”, “pin” and “lead” are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean an interconnection between or a terminus of a device element, a circuit element, an integrated circuit, a device, or other electronics or semiconductor component.
A circuit or device that is described herein as including certain components may instead be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and/or the sources to form the described structure either at a time of manufacture or after a time of manufacture, for example, by an end-user and/or a third-party.
While the use of particular transistors is described herein, other transistors (or equivalent devices) may be used instead with little or no change to the remaining circuitry. For example, a PFET may be used in place of an NFET, an NFET in place of a PFET, a bipolar junction transistor in place of a FET, etc.
References herein to a FET being “ON” means that the conduction channel of the FET is present and drain current may flow through the FET. References herein to a FET being “OFF” means that the conduction channel is not present and drain current does not flow through the FET. An “OFF” FET, however, may have current flowing through the transistor's body-diode.
Circuits described herein are reconfigurable to include additional or different components to provide functionality at least partially similar to functionality available prior to the component replacement. Components shown as resistors, unless otherwise stated, are generally representative of any one or more elements coupled in series and/or parallel to provide an amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as the single resistor or capacitor.
While certain elements of the described examples are included in an integrated circuit and other elements are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features illustrated as being external to the integrated circuit may be included in the integrated circuit and/or some features illustrated as being internal to the integrated circuit may be incorporated outside of the integrated. As used herein, the term “integrated circuit” means one or more circuits that are: (i) incorporated in/over a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; and/or (iv) incorporated in/on the same printed circuit board.
Uses of the phrase “ground” in the foregoing description include a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of this description. In this description, unless otherwise stated, “about,” “approximately” or “substantially” preceding a parameter means being within +/−10 percent of that parameter.
Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.
The present application is a continuation of U.S. patent application Ser. No. 17/875,192 filed Jul. 27, 2022, which application is hereby incorporated herein by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 17875192 | Jul 2022 | US |
| Child | 18952630 | US |
