Claims
- 1. A multiplication processing device having a first latch for inputting a multiplier, and a partial product generating and adding circuit, the multiplication processing device comprising:
- a carry generating circuit connected to said first latch, said carry generating circuit having selection circuit means for selecting one of a constant number and a variable number and for outputting the number selected thereby, wherein said constant number and said variable number have a same format;
- a multiplier recoding circuit connected to said first latch, to said carry generating circuit and to said partial product generating and adding circuit, said multiplier recoding circuit having:
- first means for receiving signed digit data, the radix of which is 2, from said first latch and for dividing the received signed digit data into 2-digit sets and for calculating an intermediate sum S.sub.1 and an intermediate carry C.sub.i from a value Z.sub.gi of an ith set wherein Z.sub.gi is given by
- Z.sub.gi =4.times.C.sub.i +S.sub.i
- (where i represents natural numbers equal to or greater than a predetermined number L), and calculating a secondary intermediate Sum R.sub.1 and a secondary intermediate carry B.sub.i corresponding to the ith set given by
- R.sub.i =S.sub.i +Q.sub.i-1
- and
- B.sub.i =C.sub.i +Q.sub.1
- by using a signal Q.sub.i representing the information indicating whether a value at a higher-order digit of the ith set is 1, by inputting a signal Q.sub.L-1 corresponding to an (L-1)th set from said selection circuit means and by also using another signal Q.sub.i-1 corresponding to an (i-1)th set; and
- second means for calculating a recoded value Z.sub.1 given by
- Z.sub.i =C.sub.i-1 +S.sub.i =B.sub.i-1 +R.sub.i-1
- by using the secondary intermediate sum R.sub.i, by inputting the selected number from said selection circuit means as the secondary intermediate carry BL-1 corresponding to the (L-1)th set and using the secondary intermediate carry B.sub.i-1 corresponding to the (i-1)th set.
- 2. A multiplication processing device comprising:
- first means for selecting a first part represented by digits at predetermined digit places having orders which are higher than a first predetermined digit position of an input number and of a constant and for outputting the selected first part of the input number and the constant;
- second means for inverting a sign of a second part represented by digits at predetermined digit places having orders which are equal to and lower than a third predetermined digit position of the input number and for outputting the second part of the input number having the inverted sign;
- third means for inverting a sign of a value represented by a second predetermined digit position of the input number and for outputting the value represented by the second predetermined digit position having the inverted sign if a value held at the first predetermined digit position is 0 and for outputting a value represented by the second predetermined digit position of the input number if the value held at the first predetermined digit position is other than 0; and
- recoding circuit means capable of inputting the values outputted from the first, second and third means.
- 3. The multiplication processing device as set forth in claim 2 further comprising iterating means for performing an iterative multiplication process, wherein said recoding circuit means further operates for rounding an intermediate result of said iterative multiplication process performed by said iterating means, thereby eliminating a rounding circuit from said iterating means of said multiplication processing device.
- 4. The multiplication processing device as set forth in claim 2 further comprising iterating means for performing an iterative multiplication process, wherein said first, second and third means and said recoding circuit means cooperate to provide logical inversions of corresponding input digits thereby eliminating a subtraction circuit for redundant numbers from said iterating means of said multiplication processing device.
- 5. The multiplication processing device as set forth in claim 2 further comprising iterating means for performing an iterative multiplication process, wherein said first, second and third means and said recoding circuit means cooperate to provide logical inversions of corresponding input digits thereby eliminating an adder circuit for redundant numbers from said iterating means of said multiplication processing device.
- 6. A multiplication processing device having a first latch for inputting a multiplier, and a partial product generating and adding circuit, the multiplication processing device comprising:
- a carry generating circuit connected to said first latch, the carry generating circuit having selection circuit means for selecting one of a constant number and a variable number, said constant number and said variable number having a same format, said selection circuit means operating for outputting the selected number; and
- recoding circuit means, connected to said first latch, to said carry generating circuit and to said partial product generating and adding circuit, for receiving an M-digit number (where M is a natural number and N is equal to M in case of obtaining one set of N consecutive digits., and N is a natural number less than M in case of obtaining two or more sets of N consecutive digits from the M-digit number), the radix of which is .UPSILON., and for obtaining one or more sets of N consecutive digits from the M-digit number by using the M-digit number as the set of N consecutive digits when N is equal to M and, by dividing the M-digit number into the sets of N consecutive digits, for receiving the selected number from said selection circuit as an intermediate carry C.sub.L-1 corresponding to an (L-1)th set (where L is a predetermined number) and for calculating an intermediate sum S.sub.i and an intermediate carry C.sub.i according to Z.sub.gi =C.sub.i .times..UPSILON..sup.N +S.sub.i =.UPSILON..sup.N-1 X.sub.j+N-1 + . . . +.UPSILON.X.sub.j+1 +X.sub.j (wherein Z.sub.gi is the value of an ith set, i represents natural numbers equal to or greater than the predetermined number L, and X.sub.j+N-1, . . . X.sub.j+1 and X.sub.j are values of the N consecutive digits of the ith set), for adding the intermediate sum S.sub.L corresponding to the Lth set to the number received as the intermediate carry C.sub.L-1 corresponding to an (L-1)th set and for adding the intermediate sum S.sub.i corresponding to the ith set to an intermediate carry C.sub.i-1 corresponding to an (i-1)th set.
- 7. The multiplication processing device as set forth in claim 6 wherein said recoding circuit means comprises:
- a plurality of recoding means, the number of which is equal to or greater than (M/N), wherein a kth one of said recoding means calculates an intermediate sum S.sub.L+k-1 and an intermediate carry C.sub.L+k-1 in accordance with a relation described by Z.sub.g(L+k-1)=C.sub.L+k-1 .times..UPSILON..sup.N S.sub.L+k-1 =.UPSILON..sup.N-1 X.sub.j+N-1 + . . . +.UPSILON.X.sub.j+1 +X.sub.j (where Z.sub.g (L+k-1) is the value of an (L+k-1)th set; and X.sub.j+N-1, . . . X.sub.j+1 X.sub.j are the values of the N consecutive digits of the (L+k-1)th set)) and adds the intermediate sum S.sub.L+k-1 corresponding to the (L+k-1)th set to an intermediate carry C.sub.L+k-2 corresponding to an (L+k-2)th set, wherein each of said plurality of recoding means comprises:
- first means for dividing the M-digit number into the N-digit sets and for calculating the intermediate sum S.sub.i and the intermediate carry C.sub.i in accordance with a relation described by Z.sub.gi =C.sub.i .times..UPSILON..sup.N +S.sub.i, Z.sub.gi being the value of the ith set; and
- second means for adding the intermediate sum S.sub.i to the intermediate carry C.sub.i-1 corresponding to an (i-1)th set for each value of i, wherein said selection circuit means outputs the selected number to said recoding circuit means as the intermediate carry C.sub.i-1.
- 8. The multiplication processing device as set forth in claim 6 which further comprises carry-due-to-rounding generating means for outputting a carry generated due to rounding to said selection circuit means.
- 9. The multiplication processing device as set forth in claim 6, wherein said recoding circuit means effects logical inversion of the M-digit number and then obtains one or more sets of the consecutive N digits from data obtained as a result of the logical inversion, and wherein a value of 1 is inputted to said selection circuit means and further said selection circuit means selects the input value of 1.
- 10. The multiplication processing device as set forth in claim 6 wherein signed digit data indicating the M-digit number is inputted to said recoding circuit means.
- 11. The multiplication processing device as set forth in claim 6 wherein a value of the carry saving type is inputted to said recoding circuit means.
- 12. The multiplication processing device as set forth in claim 6 further comprising iterating means for performing an iterative multiplication process, wherein said recoding circuit means further operates for rounding an intermediate result of said iterative multiplication process performed by said iterating means, thereby eliminating a rounding circuit from said iterating means of said multiplication processing device.
- 13. The multiplication processing device as set forth in claim 6 further comprising iterating means for performing an iterative multiplication process, wherein said recoding circuit means operates to provide logical inversions of corresponding digits input thereto, thereby eliminating a subtraction circuit for redundant numbers from said iterating means of said multiplication processing device.
- 14. The multiplication processing device as set forth in claim 6 further comprising iterating means for performing an iterative multiplication process, wherein said recoding circuit means operates to provide logical inversions of predetermined digits input thereto, thereby eliminating an adder circuit for redundant numbers from said iterating means of said multiplication processing device.
- 15. A multiplication processing device having a first latch for inputting a multiplier and a partial product generating and adding circuit, the multiplication processing device performing an iterative multiplication processing in which an intermediate result is rounded upon completion of each cycle of iterative multiplication, the multiplication processing device comprising:
- a carry generating circuit connected to said first latch, said carry generating circuit having selection circuit means for selecting one of a constant number and a variable number and for outputting the number selected thereby, wherein said constant number and said variable number have a same format;
- recoding circuit means, connected to said first latch, to said carry generating circuit and to said partial product generating and adding circuit, for receiving an M-digit number (wherein M is a natural number and N is equal to M in case of obtaining one set of N consecutive digits, and N is a natural number less than M in case of obtaining two or more sets of N consecutive digits from the M-digit number), the radix of which is .UPSILON., and for obtaining one or more sets of N consecutive digits from the M-digit number by using the M-digit number as the set of N consecutive digits when N is equal to M and, by dividing the M-digit number into the sets of N consecutive digits, for receiving the selected number from said selection circuit as an intermediate carry C.sub.L-1 corresponding to an (L-1)th set (where L is a predetermined number) and for calculating an intermediate sum S.sub.i and an intermediate carry C.sub.i according to Z.sub.gi =C.sub.i .times..UPSILON..sup.N +S.sub.i =.UPSILON..sup.N-i X.sub.j+N-1 + . . . +.UPSILON.X.sub.j+1 +X.sub. j (Z.sub.gi is the value of an ith set (i represents natural number equal to or greater than the predetermined number L); and X.sub.j+N-1, . . . X.sub.j+1 and X.sub.j are the values of the N consecutive digits of the ith set)), for adding the intermediate sum S.sub.L corresponding to the Lth set to the number received as the intermediate carry C.sub.L-1 corresponding to an (L-1)th set and for adding the intermediate sum S.sub.i corresponding to the ith set to an intermediate carry C.sub.i-1 corresponding to an (i-1)th set; and
- a carry-due-to-rounding generating means for generating a carry caused due to rounding from a part of the M-digit number, which part consists of digits having orders equal to or less than the lowest-order digit of the Lth set, and for outputting the carry caused due to rounding to said selection means, wherein the numbers to be selected by said selection circuit means are 0 and the carry caused due to rounding, and said selection circuit means selects 0 in a first cycle of iterative multiplication and selects the carry caused due to rounding in each cycle subsequent to the first cycle.
Priority Claims (1)
Number |
Date |
Country |
Kind |
2-210903 |
Aug 1990 |
JPX |
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Parent Case Info
This application is a continuation of application Ser. No. 07/741,876 filed Aug. 7, 1991, now U.S. Pat. No. 5,289,398.
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Tokumaru et al. |
Feb 1989 |
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4864528 |
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Continuations (1)
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Number |
Date |
Country |
Parent |
741876 |
Aug 1991 |
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