Comparing two numbers forms one of the fundamental building blocks of logical operations. The use of logic operations in circuits, microprocessors, and computer systems is widespread. Increasing the speed at which compare operations take place as well as reducing the amount of components to compare two numbers is therefore desirable.
The present invention uses adder units to compare two numbers. Numbers can be represented using bits. Logic values (a 0 or 1; bits) from a first number and logic values from a second number are fed to logic units. The logic units perform logic operations on the logic values (bits) and output the result of the logic operations to an adder unit.
The adder unit performs an operation on these values and a “carry in” value (e.g., from a previous adder unit in a chain of adder units), and feeds the result to an output. The output of an individual adder unit is partially determinative of whether the second number is greater than the first. If an adder unit is the last in a chain of adder units, the output of that adder unit is determinative of which number is greater.
Known comparators require a look-up table (e.g., a logic unit) with the same amount of inputs as the number of bits being compared. For example, if two two-bit numbers are being compared, a look-up table would require four inputs. Additionally, the known comparators would also require that all of the bits of both numbers be input into the look-up table.
Comparators of the present invention use logic units that perform logic operations that do not require that all of the bits of both sets of numbers be fed into the logic units. Therefore, less inputs are required. Additionally, smaller look-up tables (i.e., those that have fewer inputs) can be utilized to perform compare operations. For example, to compare two pairs of two-bit numbers, two logic units (look-up tables) with three inputs each can compare the numbers.
The above and other objects and advantages of the invention will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which:
Possible results of the compare operation are represented in
Turning to
In addition to the three inputs (i.e., CIN, input from number A, and input from number B), adder unit 300 has two outputs: “Sum” 330 and “COUT=” 340. The “Sum” of adder unit 300 is represented logically as: A XOR B XOR CIN. In the preferred embodiment of the present invention, the Sum can be disregarded. As such, further discussion on the Sum is not warranted. COUT, or “Carry Out,” is a single bit with a logic value of 0 or 1. If there is an additional adder unit in a chain of adder units, COUT may be CIN of the next adder unit in the chain.
For ease of description, a nomenclature is used to describe the input into adder units. The nomenclature is a “left-side” logic value and a “right-side” logic value surrounded by parentheses and separated by a comma (e.g., the values of A[i] and B[i] in the third line of logic values in
Assuming that the logic value of a particular bit position of a number is passed directly through to the adder unit (e.g., no logic intervenes), the logic value the adder unit interprets to be from that bit position will be the logic value of that bit position as presented to the adder unit. On the other hand, if a logic unit (e.g., logic unit 410, logic unit 510, logic unit 710, logic unit 760, logic unit 770, logic unit 860, logic unit 870; described in detail in connection with
Turning to
In its most simple logical representation, the logic operations that logic unit 510 performs can be reduced to one statement: (−A[i],B[i]). This is because if A[i] is equal to B[i] is equal to 0, the output is (1,0) (i.e., (−0,0)). If A[i] is equal to B[i] is equal to 1, the output is (0,1) (i.e., (−1,1)). If A[i] is less than B[i] (which can only logically happen when A[i] is 0 and B[i] is 1), then the output is (1,1) (i.e., (−0,1)). If A[i] is greater than B[i] (which can only logically happen when A[i] is 1 and B[i] is 0), then the output is (0,0) (i.e., (−1,0)).
Note that logic units 410 and 510 generate the same outputs when A[i] is equal to B[i] is equal to 0; A[i] is less than B[i]; and A[i] is greater than B[i]. However, when A[i] is equal to B[i] is equal to 1, logic units 410 and 510 generate different outputs. As shown above in
Using the logic operations as performed by logic unit 510, the same results of those logic operations can be achieved without feeding both A[i] and B[i] to the same logic unit (as is required using logic unit 410). In other words, logic unit 510 can be separated into two logic units; one for receiving A[i] and the other for receiving B[i]. This principle is shown in
In application, this means that two single-input look-up tables can be used to compare two bits. Each single-input look up table receives a single bit and outputs a single bit accordingly. The two single-input look-up tables can be used instead of an individual two-input look-up table (as used in logic unit 410).
Extrapolating this difference, it is also possible to use two three-input look-up tables to compare four bits as two pairs of two bits each. A pair of bits from a number A and a pair of bits from a number B are compared to determine which pair is greater. Each bit in the pair of bits are preferably in neighboring bit positions. In other words, the bits in the pair are preferably next to each other in the number (e.g., bit position i−3 and bit position i−4 where “i−3” is the fourth MSB and “i−4” is the fifth MSB (the bit positions three and four bit positions away from the MSB)). Additionally, the bit positions in number A are preferably identical to the bit positions of number B.
Two logic units 860 and 870 for performing logic operations on a pair of bits from a number A and a corresponding pair (same bit positions) of bits from number B is shown in
The first step in determining which pair of bits is greater is comparing the MSBs of both pairs. The MSBs have to be directly compared against each other. Thus, logic units such as units 860 and 870 for comparing pairs of bits have the MSB of both pairs as an input.
If the MSBs of the pair of numbers are equal, then the LSBs (out of the pair of two numbers) determine whether the pair of bits from number A is greater than, less than, or equal to the pair of bits from number B. Instead of inputting the LSBs of both pairs of numbers in logic units (e.g., units 860 and 870) and thereby using more inputs into look-up tables (logic units) than necessary, the negative A logic operation described in connection with
This can be expressed logically as “If A[i]=B[i], then (−A[i−1], B[i−1]).” Performing a negative A logic operation on the LSBs logically achieves a correct result without directly comparing (inputting both numbers into the same logic unit) the two numbers against each other.
Because the LSBs of the pairs need not be directly compared against each other, logic units 860 and 870 need not have both LSBs as their inputs. As mentioned above however, the MSBs of both pairs are input into logic units 860 and 870. As shown in
If the MSB of the pair of numbers from number A is less than the MSB of the pair of numbers from number B, logic unit 860 outputs a logic 1 and logic unit 870 also outputs a logic 1 (i.e., an output of (1,1)). If the MSB of the pair of numbers from number A is greater than the MSB of the pair of numbers from number B, logic unit 860 outputs a logic 0 and logic unit 870 also outputs a logic 0 (i.e., an output of (0,0)).
Logic units such as units 860 and 870 are implemented as look-up tables. As shown in
Logic modules which include adder units can be adapted for use as a comparator. For example, the Stratix II Adaptive Logic Module made by the Altera Corporation of San Jose, Calif. can be adapted for use in compare operations.
A second set of two-bit pairs—A[i−2], A[i−3], B[i−2], and B[i−3]—is compared using look-up tables 1030 and 1040. As shown, the MSBs of both pairs of numbers (i.e., A[i−2] and B[i−2]) are input into look-up tables 1030 and 1040. The LSB of the pair of bits from number A (i.e., A[i−3]) is input into only look-up table 1030. Similarly, the LSB of the pair of bits from number B (i.e., B[i−3]) is input into only look-up table 1040.
The “left-side” and “right-side” of the compare operation and a CIN 1020 from a previous compare operation (if any) are input into adder unit 1010. The output of adder unit 1010, COUT 1040, is input as CIN 1080 into the next adder unit in the chain of adder units. The next adder unit, unit 1050, receives at its inputs CIN 1080 and the “left-side” and “right-side” of the compare operation of a first set of two-bit pairs. The first set of two-bit pairs—A[i], A[i−1], B[i], and B[i−1]—is compared using look-up tables 1060 and 1070.
As illustrated, both look-up table 1060 and table 1070 have at least three inputs. Look-up table 1060 has as its inputs the MSBs of both pairs of numbers (i.e., A[i] and B[i]). Table 1060 also has as an input the LSB of the pair of bits from number A (i.e., A[i−1]). Table 1070 also has as its inputs the MSB of both pairs of numbers. In addition, table 1070 also has as an input the LSB of the pair of bits from number B (i.e., B[i−1]).
If adder unit 1050 is the last adder unit in the chain of adder units, the output 1090 of adder unit 1050 is determinative of the comparison between number A and number B. If output 1090 is 1, then number A is less than number B. If output 1090 is 0, then number A is equal to number B or greater than number B.
It is important to note that
It is preferable that an additional adder unit beyond the adder units required to compare the bits of a number A and a number B is used when comparing numbers A and B. This adder unit receives as its input the carry out of the last adder unit (e.g., output 1090 of adder unit 1050) that was used in performing logic operations.
Therefore, for comparing two numbers each N-bits in length where adder unit compares a set of two-bit pairs, the number of adder units required to compare these two numbers is N divided by two (rounded up to the nearest whole number if two does not divide into N evenly) plus one. The plus one is for the additional adder unit that receives as its input the carry out of the last adder unit in the chain of adder units used in performing logic operations.
Comparator 1100 of
For example, look-up table 1160 receives a set of bits from a number A. Table 1160 receives bits in the i'th position, i−1 position, and i−2 position from number A. Additionally, table 1160 receives bits in the i'th position and i−1 position from a number B.
Tables 1160 and 1170 operate in a similar fashion to tables 960 and 970 except that the logic operations of tables 960 and 970 (i.e., logic 860 and 870) is surrounded by another “if . . . else . . . ” clause:
Similarly, tables 1260 and 1270 operate in a similar fashion to logic tables 1160 and 1170 except that the logic performed by tables 1160 and 1170 are surrounded by another “if . . . else . . . ” clause:
For tables that have additional bits as an input, another “if . . . else . . . ” clause surrounds the logic operations for each additional bit.
Generally, the look-up tables (logic units) used in accordance with the present invention use less inputs and logic elements than prior comparators. For example, the present invention can compare two eight-bit numbers using 5 Adaptive Look-Up Tables (“ALUTs”) in comparison to known comparators which require 6 ALUTs. To compare two sixteen-bit numbers, the present invention uses 9 ALUTs, known comparators use 14 ALUTs. To compare thirty-two-bit numbers, the present invention uses 17 ALUTs, known comparators use 32 ALUTs. To compare sixty-four-bit numbers, the present invention uses 33 ALUTs, known comparators use 66 ALUTs.
Comparators designed in accordance with the present invention are also faster than known comparators. The present invention can compare to eight-bit numbers in one nanosecond. Known comparators take 1.5 nanoseconds to compare two eight-bit numbers. The present invention compares two sixteen-bit numbers in 1.25 ns; known comparators, 4 ns. The present invention compares two thirty-two-bit numbers in 1.7 ns, known comparators 5.6 ns. The present invention compares two sixty-four-bit numbers in 2.4 ns, known comparators in 8.9 ns.
One skilled in the art will appreciate that the invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims which follows.