Claims
- 1. A fan module comprising:
two or more individual fans, each fan having an air movement means and a motor engaged with the air movement means for accelerating air entering each of the two or more individual fans; a temperature sensor for sensing a temperature associated with the two or more fans and for outputting a first signal corresponding to the temperature; rotational speed means for outputting a second signal corresponding to a rotational speed of each of the two or more fans; and a processor for receiving the first and second signals and controlling the two or more individual fans based on the first and second signals.
- 2. The fan module of claim 1, wherein the temperature sensor is selected from a group consisting of a thermistor and thermocouple.
- 3. The fan module of claim 1, wherein the rotational speed means comprises an RPM signal output from each of the two or more individual fans, the RPM signal comprising the second signal.
- 4. The fan module of claim 1, wherein each processor controls each corresponding fan by varying a pulse width of a supply voltage supplied to each of the two or more individual fans.
- 5. The fan module of claim 1, further comprising a bracket for housing each of the two or more fans.
- 6. The fan module of claim 1, further comprising means for damping vibration from each of the two or more fans.
- 7. The fan module of claim 1, further comprising a nonvolatile memory connected to each processor for storing a control program for instructing each processor.
- 8. An array of fans, each fan having an air movement means and a motor engaged with the air movement means for accelerating air entering each fan, the array of fans comprising:
two or more fan modules, each fan module having two or more individual fans, a temperature sensor for sensing a temperature associated with the two or more fans and for outputting a first signal corresponding to the temperature, rotational speed means for outputting a second signal corresponding to a rotational speed of each of the two or more fans, and a processor for receiving the first and second signals and controlling the two or more individual fans based on the first and second signals; and a fan frame for housing the at least two or more fan modules.
- 9. The array of fans of claim 8, further comprising a bracket corresponding to each of the two or more fan modules, each bracket housing the two or more fans therein and further having a means for securing to the frame.
- 10. The array of fans of claim 9, further comprising a host controller for interacting with each of the processors of each of the two or more modules.
- 11. The array of fans of claim 10, further comprising an electrical connector on each bracket and a mating electrical connector on the frame for electrically connecting each of the processors to the host controller.
- 12. The array of fans of claim 11, where each electrical connector has location identification pins hard wired therein for determining the physical location of the fan module in the frame.
- 13. The array of fans of claim 10, further comprising at least one indicator operatively connected to the host controller and disposed on a side of the bracket for displaying the status of the fan module.
- 14. The array of fans of claim 13, wherein the at least one indicator comprises two LED indicators, one of which is a first color and the second of which is a second color different from the first color.
- 15. The array of fans of claim 10, further comprising a data link operatively connected to the host controller for communicating with a remote location.
- 16. A computer comprising:
heat generating elements; and an array of cooling fans for cooling at least one of the heat generating elements, each cooling fan having an air movement means and a motor engaged with the air movement means for accelerating air entering each cooling fan, the array of cooling fans comprising, two or more fan modules, each fan module having two or more individual cooling fans, a temperature sensor for sensing a temperature associated with the cooling fans and for outputting a first signal corresponding to the temperature, rotational speed means for outputting a second signal corresponding to a rotational speed of each of the cooling fans, a processor for receiving the first and second signals and controlling the individual cooling fans based on the first and second signals, and a fan frame for housing the at least two or more fan modules.
- 17. The computer of claim 16, further comprising a bracket corresponding to each of the two or more fan modules, each bracket housing the two or more cooling fans therein and further having a means for securing to the frame.
- 18. The computer of claim 16, further comprising a host controller for interacting with each of the processors of each of the two or more modules.
- 19. The computer of claim 18, further comprising an electrical connector on each bracket and a mating electrical connector on the frame for electrically connecting each of the processors to the host controller.
- 20. The computer of claim 19, where each electrical connector has location identification pins hard wired therein for determining the physical location of the fan module in the frame.
- 21. The computer of claim 20, further comprising at least one indicator operatively connected to the host controller and disposed on a side of the bracket for displaying the status of the fan module.
- 22. The computer of claim 21, wherein the at least one indicator comprises two LED indicators, one of which is a first color and the second of which is a second color different from the first color.
- 23. The computer of claim 18, further comprising a data link operatively connected to the host controller for communicating with a remote location.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] The present invention claims the benefit of commonly-owned, co-pending U.S. Provisional Patent Application Serial No. 60/271,124 filed Feb. 24, 2001 entitled MASSIVELY PARALLEL SUPERCOMPUTER, the whole contents and disclosure of which is expressly incorporated by reference herein as if fully set forth herein. This patent application is additionally related to the following commonly-owned, co-pending United States Patent Applications filed on even date herewith, the entire contents and disclosure of each of which is expressly incorporated by reference herein as if fully set forth herein. U.S. patent application Ser. No. (YOR920020027US1, YOR920020044US1 (15270)), for “Class Networking Routing”; U.S. patent application Ser. No. (YOR920020028US1 (15271)), for “A Global Tree Network for Computing Structures”; U.S. patent application Ser. No. (YOR920020029US1 (15272)), for “Global Interrupt and Barrier Networks”; U.S. patent application Ser. No. (YOR920020030US1 (15273)), for “Optimized Scalable Network Switch”; U.S. patent application Ser. No. (YOR920020031US1, YOR920020032US1 (15258)), for “Arithmetic Functions in Torus and Tree Networks”; U.S. patent application Ser. No. (YOR920020033US1, YOR920020034US1 (15259)), for “Data Capture Technique for High Speed Signaling”; U.S. patent application Ser. No. (YOR920020035US1 (15260)), for ‘Managing Coherence Via Put/Get Windows’; U.S. patent application Ser. No. (YOR920020036US1, YOR920020037US1 (15261)), for “Low Latency Memory Access And Synchronization”; U.S. patent application Ser. No. (YOR920020038US1 (15276), for “Twin-Tailed Fail-Over for Fileservers Maintaining Full Performance in the Presence of Failure”; U.S. patent application Ser. No. (YOR920020039US1 (15277)), for “Fault Isolation Through No-Overhead Link Level Checksums”; U.S. patent application Ser. No. (YOR920020040US1 (15278)), for “Ethernet Addressing Via Physical Location for Massively Parallel Systems”; U.S. patent application Ser. No. (YOR920020041US1 (15274)), for “Fault Tolerance in a Supercomputer Through Dynamic Repartitioning”; U.S. patent application Ser. No. (YOR920020042US1 (15279)), for “Checkpointing Filesystem”; U.S. patent application Ser. No. (YOR920020043US1 (15262)), for “Efficient Implementation of Multidimensional Fast Fourier Transform on a Distributed-Memory Parallel Multi-Node Computer”; U.S. patent application Ser. No. (YOR9-20010211US2 (15275)), for “A Novel Massively Parallel Supercomputer”; and U.S. patent application Ser. No. (YOR920020045US1 (15263)), for “Smart Fan Modules and System”.
Provisional Applications (1)
|
Number |
Date |
Country |
|
60271124 |
Feb 2001 |
US |
Divisions (1)
|
Number |
Date |
Country |
Parent |
10083270 |
Feb 2002 |
US |
Child |
10437766 |
May 2003 |
US |