Patent Application
20130176009
This disclosure relates generally to power management circuits, and particularly relates to low drop-out voltage regulators.
Most electronic devices operate at regulated and stable voltages. In particular, most semiconductor based electronic devices operate at relatively low direct current (“DC”) voltages, for example DC voltages lower than 12 volts. However, much of the electrical energy to power electronic devices is made available at substantially higher voltages. For example, residential electrical power in the United States is an alternate current (“AC”) voltage nominally rated at 120 volts, and in China is an AC voltage nominally rated at 220 Volts.
Generally power supplies are employed to provide appropriate supply voltages for electronic devices. Typically, a power supply may comprise a voltage regulator to convert a relatively high voltage into a relatively low and regulated voltage suitable for powering electronic devices. One type of commonly used voltage regulators comprises a low drop-out voltage regulator (“LDO”). The operation of the low drop-out voltage regulator is based on feeding back an amplified difference signal between its output voltage and a desired value, which is used to control an output current flow of a pass device (such as a power transistor) driving a load. The drop-out voltage is the value of the input/output differential voltage lost during feedback regulation.
A low drop-out voltage regulator may be used alone to provide power. A low drop-out voltage regulator may also be integrated into an integrated circuit (“IC”) such as a driver or a power converter etc. to provide an appropriate operating voltage required by other circuit elements in the integrated circuit from a high voltage power bus (e.g. a high-voltage AC power bus). However, since the voltage of the high voltage power bus may vary largely under different conditions, a traditional low drop-out voltage regulator usually consume a lot of power and may even cause thermal problems. For example, in most high-voltage applications wherein the voltage of the high-voltage power bus may be as high as several hundreds volts, the possibility to connect a traditional low drop-out voltage regulator to the high voltage power bus is normally limited by the thermal handling capability of the IC package.
Sometimes, a power resistor and a zenor diode may be used to replace a low drop-out voltage regulator to provide a desired voltage from a high voltage power bus. However, the power consumed on the power resistor may also be very high.
A need therefore exists for a low drop-out voltage regulator wherein the abovementioned disadvantage(s) may be alleviated.
In accomplishing the above and other objects, there has been provided, in accordance with an embodiment of the present disclosure, a low drop-out voltage regulator, comprising: an input terminal configured to receive a power supply voltage; an output terminal configured to provide an output voltage; a pass device having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the input terminal, and wherein the second terminal is coupled to the output terminal; and a controller comprising an input terminal configured to receive an input signal, and an output terminal configured to provide a driving signal to the control terminal of the pass device based on the input signal, wherein the driving signal turns the pass device ON when the input signal is within a predetermined range; and wherein the driving signal turns the pass device OFF when the input signal is without the predetermined range.
In addition, there has been provided, in accordance with an embodiment of the present disclosure, a method for converting a power supply voltage to a regulated output voltage, comprising: providing the power supply voltage to a first terminal of a pass device, wherein the pass device further comprises a second terminal and a control terminal; and controlling the pass device to provide the regulated output voltage at the second terminal; wherein controlling the pass device comprises: comparing an input signal related to the power supply voltage and/or the output voltage with a predetermined range to generate a driving signal having an enable logic state and a disable logic state, wherein the driving signal is at the enable logic state when the input signal is within the predetermined range, and wherein the driving signal is at the disable logic state when the input signal is without the predetermined range; providing the driving signal to the control terminal of the pass device; and turning the pass device ON when the driving signal is at the enable logic state, and turning the pass device OFF when the driving signal is at the disable logic state.
The following detailed description of various embodiments of the present invention can best be understood when read in conjunction with the following drawings, in which the features are not necessarily drawn to scale but rather are drawn as to best illustrate the pertinent features.
The use of the same reference label in different drawings indicates the same or like components or structures with substantially the same functions for the sake of simplicity.
Various embodiments of the present invention will now be described. In the following description, some specific details, such as example circuits and example values for these circuit components, are included to provide a thorough understanding of embodiments. One skilled in the relevant art will recognize, however, that the present invention can be practiced without one or more specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, processes or operations are not shown or described in detail to avoid obscuring aspects of the present invention.
Throughout the specification and claims, the term “coupled,” as used herein, is defined as directly or indirectly connected in an electrical or non-electrical manner. The terms “a,” “an,” and “the” include plural reference, and the term “in” includes “in” and “on”. The phrase “in one embodiment,” as used herein does not necessarily refer to the same embodiment, although it may. The term “or” is an inclusive “or” operator, and is equivalent to the term “and/or” herein, unless the context clearly dictates otherwise. The term “based on” is not exclusive and allows for being based on additional factors not described, unless the context clearly dictates otherwise. The term “circuit” means at least either a single component or a multiplicity of components, either active and/or passive, that are coupled together to provide a desired function. The term “signal” means at least one current, voltage, charge, temperature, data, or other signal. Where either a field effect transistor (“FET”) or a bipolar junction transistor (“BJT”) may be employed as an embodiment of a transistor, the scope of the words “gate”, “drain”, and “source” includes “base”, “collector”, and “emitter”, respectively, and vice versa. Those skilled in the art should understand that the meanings of the terms identified above do not necessarily limit the terms, but merely provide illustrative examples for the terms.
In one embodiment, the driving signal DR may comprise an enable logic state and a disable logic state, wherein the driving signal DR is at the enable logic state when the input signal IN is within the predetermined range; and wherein the driving signal DR is at the disable logic state when the input signal IN is without the predetermined range; and wherein the driving signal DR turns the pass device 103 ON when the driving signal DR is at the enable logic state; and wherein the driving signal DR turns the pass device 103 OFF when the driving signal DR is at the disable logic state.
In one embodiment, the pass device 103 may comprise a high-voltage semiconductor device controllable to be turned ON or OFF in response to a control signal applied at the control terminal. For example, the pass device 103 may comprise a high-voltage transistor such as a high-voltage metal oxide semiconductor field effect transistor (“MOSFET”), a high-voltage bipolar junction transistor (“BJT”), a high-voltage double diffused metal oxide semiconductor field effect transistor (“DMOS”), a high-voltage junction field effect transistor (“JFET”) etc. and/or combinations thereof.
In one embodiment, still referring to
In this case, the first predetermined range Δin is substantially controlled between ground potential and the first threshold voltage Vth1.
In one embodiment, the controller 104 may further comprise a logic driving circuit such as a driver (not shown) configured to receive the first control signal S1 and to convert the first control signal S1 into the driving signal DR. The logic driving circuit in this case is usually provided to improve the driving capability of the driving signal DR.
In one embodiment, the first threshold voltage Vth1 may comprise a third threshold voltage Vth3 and a fourth threshold voltage Vth4, wherein the fourth threshold voltage Vth4 has a first predetermined hysteresis from the third threshold voltage Vth3, and wherein the first control signal S1 is at the enable logic state when the power supply voltage Vin is lower than the third threshold voltage Vth3, and wherein the first control signal S1 is at the disable logic state when the power supply voltage Vin is higher than the fourth threshold voltage Vth4.
In one embodiment, the fourth threshold voltage Vth4 is higher than the third threshold Vth3 thereby providing a hysteresis for the first control signal S1's changing from the enable logic state to the disable logic state. This may reduce the possibility of back and forth logic state change of the first control signal S1 when the power supply voltage Vin has small fluctuations, which may be harmful to the ruggedness of the low drop-out voltage regulator 100. In this case, the first predetermined range Δin (the effective range) of the power supply voltage Vin is controlled between ground potential and Vth3. However, in some applications, it is desired that the effective range of the power supply voltage Vin starts from a potential higher than the ground potential. This may be achieved just by setting the fourth threshold voltage Vth4 as the starting effective potential of the power supply voltage Vin. Therefore, in one exemplary embodiment, the fourth threshold voltage Vth4 is lower than the third threshold voltage Vth3. In this way, first predetermined range Δin of the power supply voltage Vin is controlled between Vth4 and Vth3.
As illustrated in
In one embodiment, the seventh threshold voltage Vth7 may comprise an eighth threshold voltage Vth8 and a ninth threshold voltage Vth9 respectively related to the third threshold voltage Vth3 and the fourth threshold voltage Vth4, wherein the ninth threshold voltage Vth9 has a third predetermined hysteresis from the eighth threshold voltage Vth8, and wherein the first control signal S1 is at the enable logic state when the sensed voltage VS is lower than the eighth threshold voltage Vth8, and wherein the first control signal S1 is at the disable logic state when the sensed voltage VS is higher than the ninth threshold voltage Vth9.
In one embodiment, the first sensing circuit 201 may comprise a first voltage divider comprising: a first resistive device 2011 coupled between the input terminal and the output terminal of the first sensing circuit 201; and a second resistive device 2012 coupled between the output terminal of the first sensing circuit 201 and ground. In one embodiment, the first resistive device 2011 may comprise a high-voltage resistor. In other embodiments, the first resistive device 2011 may comprise other high-voltage resistive devices, such as high-voltage JFET, high-voltage MOSFET, high-voltage BJT etc. In still other embodiments, the first resistive device 2011 may comprise the combinations of a high voltage transistor and a resistor. For example, in the exemplary embodiment shown in
In one embodiment, the first comparison circuit 202 may comprise a hysteresis comparator having the eighth threshold voltage Vth8 and the ninth threshold voltage Vth9.
In other embodiment, as illustrated in
In one embodiment, still referring to
In this case, the second predetermined range Δhd out is substantially controlled around the second threshold voltage Vth2.
In one embodiment, the controller 104 may further comprise a logic driving circuit such as a driver (not shown) configured to receive the second control signal S2 and to convert the second control signal S2 into the driving signal DR. The logic driving circuit in this case is usually provided to improve the driving capability of the driving signal DR.
In one embodiment, the second threshold voltage Vth2 may comprise a fifth threshold voltage Vth5 and a sixth threshold voltage Vth6, wherein the sixth threshold voltage Vth6 has a second predetermined hysteresis from the fifth threshold voltage Vth5, and wherein the second control signal S2 is at the enable logic state when the output voltage Vout is lower than the fifth threshold voltage Vth5, and wherein the second control signal S2 is at the disable logic state when the output voltage Vout is higher than the sixth threshold voltage Vth6.
In this case, the second predetermined range Δout is substantially controlled between the fifth threshold voltage Vth5 and a sixth threshold voltage Vth6.
In one embodiment, as illustrated in
In one embodiment, the tenth threshold voltage Vth10 may comprise an eleventh threshold voltage Vth11 and a twelfth threshold voltage Vth12 respectively related to the fifth threshold voltage Vth5 and the sixth threshold voltage Vth6, wherein the twelfth threshold voltage Vth12 has a fourth predetermined hysteresis from the eleventh threshold voltage Vth11, and wherein the second control signal S2 is at the enable logic state when the feedback voltage Vf is lower than the eleventh threshold voltage Vth11, and wherein the second control signal S2 is at the disable logic state when the feedback voltage Vf is higher than the twelfth threshold voltage Vth12.
In one embodiment, the second sensing circuit 203 may comprise a second voltage divider comprising: a third resistive device 2031 coupled between the input terminal and the output terminal of the second sensing circuit 203; and a fourth resistive device 2032 coupled between the output terminal of the second sensing circuit 203 and ground. In one embodiment, the third resistive device 2031 may comprise a first resistor; the fourth resistive device 2032 may comprise a second resistor. In other embodiments, the third resistive device 2031 may comprise other resistive devices, such as JFET, MOSFET, and BJT etc. In other embodiments, the fourth resistive device 2032 may also comprise other resistive devices such as JFET, MOSFET, BJT, etc.
In one embodiment, the second comparison circuit 204 may comprise a hysteresis comparator having the eleventh threshold voltage Vth11 and the twelfth threshold voltage Vth12.
In other embodiment, as illustrated in
In one embodiment, still referring to
In one embodiment, the logic circuit 107 may comprise an AND logic circuit. In other embodiment, the logic circuit 107 may comprise an AND gate 1071 configured to receive the first control signal S1 and the second control signal S2, and to provide an “AND signal” of the first control signal S1 and the second control signal S2; and a driver 1072 configured to receive the “AND signal” and to provide the driving signal DR. In still other embodiments, the logic circuit 107 may comprise other logic components.
In one embodiment, as illustrated in
In accordance with the various embodiments described with reference to
For better understanding of the various embodiments of the present invention. Operation principles of the low drop-out voltage regulator 400 will be explained herein as an example with reference to
From time t0 to t1, the power supply voltage Vin is lower than the third threshold voltage Vth3, and the output voltage Vout is lower than the fifth threshold voltage Vth5, thus, the first control signal S1 and the second control signal S2 are respectively at their enable logic states, resulting in the driving signal DR being at the enable logic state and turning the pass device 103 ON such that the power supply voltage Vin charges the output voltage Vout. At time t1, the output voltage Vout is charged to exceed the sixth threshold voltage Vth6, the second control signal S2 changes to the disable logic state, resulting in the driving signal DR changing to the disable logic state and turning the pass device 103 OFF such that the output voltage Vout starts to be discharged.
From time t1 to t2, either the first control signal S1 is at the disable logic state or the control signal S2 is at the disable logic state, thus, the driving signal DR is at the disable logic state, keeping the pass device 103 OFF. At time t2, the power supply voltage Vin falls below the third threshold voltage Vth3 again, and the output voltage Vout falls below the fifth threshold voltage Vth5, thus, both the first control signal S1 and the second control signal S2 change to their enable logic states, resulting in the driving signal DR changing to the enable logic state and turning the pass device 103 ON.
From time t2 to t3, the pass device 103 remains ON, the power supply voltage Vin charges the output voltage Vout until at time t3, the output voltage Vout exceeds the sixth threshold voltage Vth6, the second control signal S2 changes to the disable logic state, resulting in the driving signal DR changing to the disable logic state. Thus, at time t3, the pass device 103 is turned OFF again, the output voltage Vout starts to be discharged.
From time t3 to t4, the driving signal DR keeps at the disable logic state, the pass device 103 remains OFF until at time t4, the output voltage Vout is discharged below the fifth threshold voltage Vth5. In the meanwhile, at time t4, the power supply voltage Vin is lower than the third threshold voltage Vth3, thus, the driving signal DR changes to the enable logic state again, turning the pass device 103 ON, the power supply voltage Vin starts to charge the output voltage Vout again. In the following, the low drop-out voltage regulator 400 repeats the above described operations periodically.
Based on the operation principles of the low drop-out voltage regulator 400 described above with reference to
For the low drop-out voltage regulator 100 illustrated in the example of
In the exemplary embodiments described with reference to
In the exemplary embodiments described with reference to
In the exemplary embodiments described with reference to
The low drop-out voltage regulators in accordance with various embodiments described with reference to
In one embodiment, the linear regulator 501 may comprise a transistor 5011 having a first transistor terminal, a second transistor terminal and a transistor control terminal wherein the first transistor terminal is configured to receive the output voltage Vout, the second transistor terminal is configured to generate the second output voltage Vout2; a feedback circuit 5012 having a feedback input terminal configured to receive the second output voltage Vout2, and a feedback output terminal configured to provide a regulator feedback signal Vf2 related to the second output voltage Vout2 (e.g. the regulator feedback signal Vf2 is a scaled down voltage of the second output voltage Vout2); and an amplifier 5013 having a first amplifier input terminal configured to receive a reference signal Vref, a second amplifier input terminal configured to receive the regulator feedback signal Vf2, and an amplifier output terminal configured to provide a transistor control signal Vo to the transistor control terminal of the transistor 5011, wherein the transistor control signal Vo represents a difference between the second output voltage Vout2 and the reference signal Vref, and wherein the transistor control signal Vo drives the transistor 5011 to generate the second output voltage Vout2 at the second transistor terminal. In such a configuration, the linear regulator 501 is able to regulate the second output voltage Vout2 at a desired value through negative feedback regulation. The reference signal Vref may be selected depending on the desired value of the second output voltage Vout2.
In one embodiment, the linear regulator 501 may further comprise a compensation circuit comprising a compensation capacitor CC coupled between the second amplifier input terminal and the amplifier output terminal; and a compensation resistor RC coupled between the second amplifier input terminal and the feedback output terminal. The compensation capacitor CC and the compensation resistor RC may help to improve the feedback regulation stability of the linear regulator 501. In other embodiments, other compensation circuits may be used.
In one embodiment, the feedback circuit 5012 may comprise a third voltage divider comprising: a fifth resistive device Rf1 coupled between the input terminal and the output terminal of the feedback circuit 5012; and a sixth resistive device Rf2 coupled between the output terminal of the feedback circuit 5012 and ground. In one embodiment, the fifth resistive device Rf1 may comprise a third resistor; the sixth resistive device Rf2 may comprise a fourth resistor. In other embodiments, the fifth resistive device Rf1 may comprise other resistive devices, such as JFET, MOSFET, and BJT etc. In other embodiments, the sixth resistive device Rf2 may also comprise other resistive devices such as JFET, MOSFET, BJT, etc.
In the exemplary embodiment shown in
For all the low drop-out voltage regulators 100, 200, 300, 400, and 500 described in this disclosure, the pass device 103 and the controller 104 may be integrated together and formed on a same die or be separated and formed on different dies.
In other embodiments, the pass device 103 and the controller 104 may be packaged in other arrangements.
The low drop-out voltage regulators in accordance with various embodiments of the present invention may be employed alone or be integrated with other integrated circuits to provide power for various electronic devices.
The advantages of the various embodiments of the present invention are not confined to those described above. These and other advantages of the various embodiments of the present invention will become more apparent upon reading the whole detailed descriptions and studying the various figures of the drawings.
In one embodiment, the input signal may comprise the power supply voltage, and the predetermined range may comprise a first predetermined range.
In one embodiment, the input signal may comprise the output voltage, and the predetermined range may comprise a second predetermined range.
In one embodiment, the input signal may comprise the power supply voltage and the output voltage, the predetermined range may comprise the first predetermined range and the second predetermined range, wherein comparing the input signal with the predetermined range at the step 7021 may comprise: comparing the power supply voltage with the first predetermined range to generate a first control signal having an enable logic state and a disable logic state, wherein the first control signal is at the enable logic state when the power supply voltage is within the first predetermined range, and wherein the first control signal is at the disable logic state when the power supply voltage is without the first predetermined range; comparing the output voltage with the second predetermined range to generate a second control signal having an enable logic state and a disable logic state, wherein the second control signal is at the enable logic state when the regulated output voltage is within the second predetermined range, and wherein the second control signal is at the disable logic state when the regulated output voltage is without the second predetermined range; and generating the driving signal based on the first control signal and the second control signal, wherein the driving signal is at the enable logic state when the first control signal is at the enable logic state and the second control signal is also at the enable logic state, and wherein the driving signal is at the disable logic state when the first control signal is at the disable logic state and/or the second control signal is at the disable logic state.
In one embodiment, comparing the power supply voltage with the first predetermined range may comprise: comparing the power supply voltage with a first threshold voltage to generate the first control signal, wherein the first control signal is at the enable logic state when the power supply voltage is lower than the first threshold voltage, and wherein the first control signal is at the disable logic state when the power supply voltage is higher than the first threshold voltage.
In one embodiment, the first threshold voltage may comprise a third threshold voltage and a fourth threshold voltage, wherein the fourth threshold voltage has a first predetermined hysteresis from the third threshold voltage, and wherein the first control signal is at the enable logic state when the power supply voltage is lower than the third threshold voltage, and wherein the first control signal is at the disable logic state when the power supply voltage is higher than the fourth threshold voltage.
In one embodiment, comparing the output voltage with the second predetermined range may comprise: comparing the output voltage with a second threshold voltage to generate the second control signal, wherein the second control signal is at the enable logic state when the regulated output voltage is lower than the second threshold voltage, and wherein the second control signal is at the disable logic state when the regulated output voltage is higher than the second threshold voltage.
In one embodiment, the second threshold voltage may comprise a fifth threshold voltage and a sixth threshold voltage, wherein the sixth threshold voltage has a second predetermined hysteresis from the fifth threshold voltage, and wherein the second control signal is at the enable logic state when the output voltage is lower than the fifth threshold voltage, and wherein the second control signal is at the disable logic state when the output voltage is higher than the sixth threshold voltage.
In one embodiment, comparing the power supply voltage with the first threshold voltage may comprise: monitoring the power supply voltage to generate a sensed voltage related to the power supply voltage; and comparing the sensed voltage with a seventh threshold voltage related to the first threshold voltage to generate the first control signal, wherein the first control signal is at the enable logic state when the sensed voltage is lower than the seventh threshold voltage, and wherein the first control signal is at the disable logic state when the sensed voltage is higher than the seventh threshold voltage. In one embodiment, the seventh threshold voltage may comprise an eighth threshold voltage and a ninth threshold voltage, and wherein the ninth threshold voltage has a predetermined hysteresis from the eighth threshold voltage, and wherein the first control signal is at the enable logic state when the sensed voltage is lower than the eighth threshold voltage, and wherein the first control signal is at the disable logic state when the sensed voltage is higher than the ninth threshold voltage.
In one embodiment, comparing the output voltage with the second threshold voltage may comprise: monitoring the output voltage to generate a feedback voltage related to the output voltage; and comparing the feedback voltage with a tenth threshold voltage related to the second threshold voltage to generate the second control signal, wherein the second control signal is at the enable logic state when the feedback voltage is lower than the tenth threshold voltage, and wherein the second control signal is at the disable logic state when the feedback voltage is higher than the tenth threshold voltage. In one embodiment, the tenth threshold voltage may comprise an eleventh threshold voltage and a twelfth threshold voltage, and wherein the twelfth threshold voltage has a predetermined hysteresis from the eleventh threshold voltage, and wherein the second control signal is at the enable logic state when the feedback voltage is lower than the eleventh threshold voltage, and wherein the second control signal is at the disable logic state when the feedback voltage is higher than the twelfth threshold voltage.
From the foregoing, it will be appreciated that specific embodiments of the present invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the technology. Many of the elements of one embodiment may be combined with other embodiments in addition to or in lieu of the elements of the other embodiments. Accordingly, the present invention is not limited except as by the appended claims.
