Networking has become an integral part of computer systems. Advances in network bandwidths, however, have not been fully utilized due to overhead that may be associated with processing protocol stacks. A protocol stack generally refers to a set of procedures or programs that may be executed to handle packets sent over a network, where the packets may conform to a specified protocol. For example, TCP/IP (Transport Control Protocol/Internet Protocol) packets may be processed using a TCP/IP stack.
Overhead associated with processing protocol stacks may result from bottlenecks in a computer system from using a central processing unit (CPU) to perform slow memory access functions such as data movement. Such overhead may be reduced by partitioning protocol stack processing. For example, TCP/IP stack processing may be offloaded to a TCP/IP offload engine (TOE). Also, the entire TCP/IP stack may be offloaded to a networking component, such as a MAC (media access control) component, of an I/O subsystem, such as a NIC (network interface card). However, valuable CPU cycles may still be spent on monitoring or snooping memory transactions communicated via a bus that is connected to the CPU.
The detailed description is provided with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The use of the same reference numbers in different figures indicates similar or identical items.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of various embodiments. However, some embodiments may be practiced without the specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to obscure the particular embodiments.
The devices 104-114 may be coupled to the network 102 through wired and/or wireless connections. Hence, the network 102 may be a wired and/or wireless network. For example, as illustrated in
The network 102 may utilize any suitable communication protocol such as Ethernet, Fast Ethernet, Gigabit Ethernet, wide-area network (WAN), fiber distributed data interface (FDDI), Token Ring, leased line, analog modem, digital subscriber line (DSL and its varieties such as high bit-rate DSL (HDSL), integrated services digital network DSL (IDSL), or the like), asynchronous transfer mode (ATM), cable modem, and/or FireWire.
Wireless communication through the network 102 may be in accordance with one or more of the following: wireless local area network (WLAN), wireless wide area network (WWAN), code division multiple access (CDMA) cellular radiotelephone communication systems, global system for mobile communications (GSM) cellular radiotelephone systems, North American Digital Cellular (NADC) cellular radiotelephone systems, time division multiple access (TDMA) systems, extended TDMA (E-TDMA) cellular radiotelephone systems, third generation partnership project (3G) systems such as wide-band CDMA (WCDMA), or the like. Moreover, network communication may be established by internal network interface devices (e.g., present within the same physical enclosure as a computing system) or external network interface devices (e.g., having a separate physical enclosure and/or power supply than the computing system to which it is coupled) such as a network interface card (NIC).
The processor 202 may include one or more caches (203), which may be shared in one embodiment of the invention. Generally, a cache stores data corresponding to original data stored elsewhere or computed earlier. To reduce memory access latency, once data is stored in a cache, future use may be made by accessing a cached copy rather than refetching or recomputing the original data. The cache 203 may be any suitable cache, such a level 1 (L1) cache, a level 2 (L2) cache, a level 3 (L-3), or the like to store instructions and/or data that are utilized by one or more components of the system 200.
A chipset 206 may additionally be coupled to the interconnection network 204. The chipset 206 may include a memory control hub (MCH) 208. The MCH 208 may include a memory controller 210 that is coupled to a memory 212. The memory 212 may store data and sequences of instructions that are executed by the processor 202, or any other device included in the computing system 200. In one embodiment of the invention, the memory 212 may include one or more volatile storage (or memory) devices such as random access memory (RAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), or the like. Nonvolatile memory may also be utilized such as a hard disk. Additional devices may be coupled to the interconnection network 204, such as multiple processors and/or multiple system memories.
The MCH 208 may additionally include a graphics interface 214 coupled to a graphics accelerator 216. In one embodiment, the graphics interface 214 may be coupled to the graphics accelerator 216 via an accelerated graphics port (AGP). In an embodiment of the invention, a display (such as a flat panel display) may be coupled to the graphics interface 214 through, for example, a signal converter that translates a digital representation of an image stored in a storage device such as video memory or system memory into display signals that are interpreted and displayed by the display. The display signals produced by the display device may pass through various control devices before being interpreted by and subsequently displayed on the display.
The MCH 208 may further include a data movement module (DMM) 213, such as a DMA (direct memory access) engine. As will be further discussed herein, e.g., with reference to
Referring to
The bus 222 may be coupled to an audio device 226, one or more disk drive(s) 228, and a network adapter 230. Other devices may be coupled to the bus 222. Also, various components (such as the network adapter 230) may be coupled to the MCH 208 in some embodiments of the invention. In addition, the processor 202 and the MCH 208 may be combined to form a single chip. Furthermore, the graphics accelerator 216 may be included within the MCH 208 in other embodiments of the invention.
Additionally, the computing system 200 may include volatile and/or nonvolatile memory (or storage). For example, nonvolatile memory may include one or more of the following: read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), a disk drive (e.g., 228), a floppy disk, a compact disk ROM (CD-ROM), a digital versatile disk (DVD), flash memory, a magneto-optical disk, or other types of nonvolatile machine-readable media suitable for storing electronic instructions and/or data.
The memory 212 may include one or more of the following in an embodiment: an operating system (O/S) 232, application 234, device driver 236, buffers 238, descriptors 240, protocol driver 242, and destination buffers 244. Programs and/or data in the memory 212 may be swapped into the disk drive 228 as part of memory management operations. The application(s) 234 may execute (on the processor(s) 202) to communicate one or more packets 246 with one or more computing devices coupled to the network 102 (such as the devices 104-114 of
In an embodiment, the application 234 may utilize the O/S 232 to communicate with various components of the system 200, e.g., through the device driver 236. Hence, the device driver 236 may include network adapter (230) specific commands to provide a communication interface between the O/S 232 and the network adapter 230. For example, the device driver 236 may allocate one or more source buffers (238A through 238N) to store packet data, such as the packet payload 246B. One or more descriptors (240A through 240N) may respectively point to the source buffers 238. A protocol driver 242 may implement a protocol driver to process packets sent over the network 102, according to one or more protocols.
In an embodiment, the O/S 232 may include a protocol stack that provides the protocol driver 242. A protocol stack generally refers to a set of procedures or programs that may be executed to process packets sent over a network (102), where the packets may conform to a specified protocol. For example, TCP/IP (Transport Control Protocol/Internet Protocol) packets may be processed using a TCP/IP stack. The device driver 236 may indicate the source buffers 238 to the protocol driver 242 for processing, e.g., via the protocol stack. The protocol driver 242 may either copy the buffer content (238) to its own protocol buffer (not shown) or use the original buffer(s) (238) indicated by the device driver 236.
In one embodiment, the data stored in the buffers 238 may be copied to the destination buffers 244 as will be further discussed with reference to
As illustrated in
In one embodiment, network adapter 230 may maintain descriptors 258A through 258N, each corresponding to one of the descriptors 240A through 240N. The descriptors 258 may be implemented in hardware registers and/or implemented as software descriptors, e.g., in the memory 254. In certain embodiments, the descriptors 258 may be stored in the memory 212, and the network adapter 230 may load the descriptors 258 into hardware registers of the network adaptor 230. Hence, descriptors may be represented in both the network adapter 230 (e.g., as hardware registers) and the memory 212 (e.g., as software elements accessible by the drivers 236 and 242).
Further, the descriptors 240 and/or 258 may be shared between the drivers (236 and/or 242) and components of the network adapter 230. For example, a descriptor (240) may be stored in memory 212 and the device driver 236 may write a buffer address (e.g., the address of one of the source buffers 238) in the descriptor (240) and submit the descriptor (240) to the network adapter 230. The adapter 230 may then load a corresponding local descriptor (258) with the buffer address stored in the corresponding descriptor (240) and use the buffer address to direct memory access (DMA) packet data into the network adapter 230 hardware to process (e.g., through the DMA engine 252). When the DMA operations are complete, the hardware may “write back” the descriptor (258) to the corresponding descriptor (240) and/or buffer (238) in the memory 212 (e.g., with a “Descriptor Done” bit, and other possible status bits). The device driver 236 may then take the descriptor (240) which is “done” and indicate the corresponding buffer to the protocol driver 242, e.g., for protocol processing.
Referring to
At a stage 306, the network adapter 230 (e.g., the adapter controller 254) may determine if a snoop attribute (246C) of the received packet is set. In an embodiment, a status bit (246C) may indicate (e.g., by a 0 or 1) whether that packet has its snoop attribute set (or “no snoop” attribute set). Snooping may generally refer to monitoring memory transactions communicated via a shared bus, interface, or interconnection network. For example, the processor(s) (202) may snoop the memory transactions communicated via the interconnection network 204, hub interface 218, and/or bus 222. However, each time a processor (202) snoops, valuable cycles may be spent on monitoring transactions, resulting in system performance hits. Hence, if the “no snoop” attribute is set (306), a no snoop memory write transaction may be performed (308) by other components of the system 200 without involving any transactions on the interconnection network 204. For example, the DMA engine 252 may write the packet payload (246C) to an available source buffer (238), e.g., as indicated by a corresponding descriptor (258 and/or 240) that was determined to be available at the stage 304.
Alternatively, if the stage 306 determines that the snoop attribute is set (or the no snoop attribute is clear), a memory write may be performed (310) that involves a snoop access by the processor(s) 202. After the stages 308 and 310, the method 300 continues with a stage 312, which performs protocol processing such as discussed with reference to the drivers (236 and/or 242) of
Referring to
Alternatively, if the stage 402 determines that one or more of the processors 202 are not going to access the packet payload, the device driver 236 may set a no snoop attribute (260) corresponding to the packet payload (408), e.g., by setting or clearing a status bit (260) of a corresponding descriptor (258 and/or 240). The DMM 213 may finish processing of the payload (410), e.g., by copying the payload from a source buffer (238) to a destination buffer (244), without invoking a snoop access to be handled by the processor(s) 202. The method 400 may continue with the stage 302 of
As illustrated in
The processors 502 and 504 may be any suitable processor such as those discussed with reference to the processors 202 of
At least one embodiment of the invention may be located within the processors 502 and 504. For example, the DMM 213 may be located within the processors 502 and 504. Other embodiments of the invention, however, may exist in other circuits, logic units, or devices within the system 500 of
The chipset 520 may be coupled to a bus 540 using a PtP interface circuit 541. The bus 540 may have one or more devices coupled to it, such as a bus bridge 542 and I/O devices 543. Via a bus 544, the bus bridge 543 may be coupled to other devices such as a keyboard/mouse 545, communication devices 546 (such as modems, network interface devices, or the like), audio I/O device, and/or a data storage device 548. The data storage device 548 may store code 549 that may be executed by the processors 502 and/or 504. For example, the packet 246 discussed with reference to
In various embodiments, one or more of the operations discussed herein, e.g., with reference to
Additionally, such computer-readable media may be downloaded as a computer program product, wherein the program may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals embodied in a carrier wave or other propagation medium via a communication link (e.g., a modem or network connection). Accordingly, herein, a carrier wave shall be regarded as comprising a machine-readable medium.
Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with that embodiment may be included in at least an implementation. The appearances of the phrase “in one embodiment” in various places in the specification may or may not be all referring to the same embodiment.
Also, in the description and claims, the terms “coupled” and “connected,” along with their derivatives, may be used. In some embodiments, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements may not be in direct contact with each other, but may still cooperate or interact with each other.
Thus, although embodiments of the invention have been described in language specific to structural features and/or methodological acts, it is to be understood that claimed subject matter may not be limited to the specific features or acts described. Rather, the specific features and acts are disclosed as sample forms of implementing the claimed subject matter.