Snubber circuits have many applications in power electronics circuits such as voltage and/or current rise limiters, level clamps, EMI limiters, and damping networks. Prior art snubber circuits, to be discussed hereinbelow, control the snubbing action under one set of circuit conditions, i.e. during switch on or switch off time. Snubbing is accomplished by selectively storing energy in a capacitor during one portion of an operating cycle and discharging the energy during a second portion of the cycle.
Using such a snubber with integrated power supply control circuits may pose a problem, in that the control circuit may shut down while trying to absorb the energy stored in the capacitor. Reducing the size of the snubber capacitor of course solves this problem but may well result in a capacitor incapable of controlling the ringing.
A general object of the present invention is to provide a snubber circuit which can provide two levels of current flow respectively well suited to control ringing and turn on.
In fulfillment of the foregoing object and in accordance with the present invention, a snubber circuit is provided for use with an integrated power supply control circuit incorporating an inductance generating element and a lateral power MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) on a single silicon chip and comprises a capacitor in circuit with at least part of the MOSFET. At least one resistor and at least one unidirectional element (preferably a diode) are arranged relative to each other to provide different first and second current flows respectively for damping ringing and for turn on.
In a somewhat more sophisticated design, a first resistor and a first unidirectional element, preferably a diode, in series with each other and with the capacitor are provided in parallel arrangement with a second resistor and second unidirectional element also in series with each other and the capacitor. The diodes are arranged to provide for current flow in one and an opposite direction to and from the capacitor and the first and second resistors respectively provide a first level of resistance for damping during ringing and a second and different level of resistance during current flow in the opposite direction during turn on.
In another embodiment, a pair of resistors are arranged in series with a capacitor with a diode across one resistor, the resistance across one resistor being selected for damping and the combined resistance across the two resistors being different for turn on. First level of current during damping and a second level of current for turn on.
a,
1
b, and 1c illustrate three different prior art snubber circuits;
a shows the simplest form of a snubber circuit. Resistor 10 affects charging and discharging of capacitor 12 equally. This limits the amount of energy that can be stored to the amount which can be discharged during the shortest period of the operating cycle.
b illustrates that this limitation can be overcome by adding a diode 14 through which the capacitor charges. Thus, the capacitor can have a smaller value than in
The circuit of
Using a snubber circuit of the type described with integrated power supply control circuits poses a problem in that the control circuit will shut down trying to absorb the energy stored in the snubber capacitor. Reducing the size of the capacitor solves the turn off problem but results in inadequate control of ringing.
In the snubber circuit of the present invention shown in
As will be apparent with either the
The present application is a divisional of U.S. patent application Ser. No. 10/956,913 (now issued as U.S. Pat. No. 7,190,564), filed Sep. 30, 2004 and entitled “SNUBBER CIRCUIT”, which itself claims priority from U.S. provisional Patent Application Ser. No. 60/508,433, filed on Oct. 2, 2003 and entitled “SNUBBER CIRCUIT FOR INTEGRATED CONTROL CHIP”, the contents of which are incorporated herein in their entirety.
Number | Name | Date | Kind |
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5946178 | Bijlenga | Aug 1999 | A |
6724357 | Kim et al. | Apr 2004 | B2 |
20050180179 | Hirst | Aug 2005 | A1 |
Number | Date | Country | |
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20070285862 A1 | Dec 2007 | US |
Number | Date | Country | |
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60508433 | Oct 2003 | US |
Number | Date | Country | |
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Parent | 10956913 | Sep 2004 | US |
Child | 11676784 | US |