Patent Application
20120050905
1. Field of the Invention
The present invention relates to a servo routine of a hard disk drive.
2. Background Information
Hard disk drives contain a plurality of magnetic heads that are coupled to rotating disks. The heads write and read information by magnetizing and sensing the magnetic fields of the disk surfaces. Each head is attached to a flexure arm to create a subassembly commonly referred to as a head gimbal assembly (“HGA”). The HGA's are suspended from an actuator arm. The actuator arm has a voice coil motor that can move the heads across the surfaces of the disks.
Information is typically stored in radial tracks that extend across the surface of each disk. Each track is typically divided into a number of segments or sectors. The voice coil motor and actuator arm can move the heads to different tracks of the disks.
Each sector may have also a servo field 5 located adjacent to a data field 6. The servo field 5 contains a plurality of servo bits A, B, C and D that are read and utilized in a servo routine to position the head 7 relative to the track. By way of example, the servo routine may utilize the algorithm of ((A−B)−(C−D)) to create a position error signal (“PES”). The PES is used to create a drive signal for the voice coil motor to position the head on the track. The servo bits are used to perform a servo routine within the disk drive. By way of example, the servo routine can be used to center the heads on the tracks. As disk capacity increases the number of servo samples also increases. The servo routines are typically performed by a central processing unit (“CPU”). Higher sample rates increases the overhead on the CPU. It is desirable to lower the load on the CPU caused by higher servo sample rates.
A hard disk drive that includes a disk with servo bits. The hard disk drive includes a central processing unit that performs a servo routine using the servo bits, and a separate a notch hardware engine that is utilize by the central processing unit to perform a notch filter function in the servo routine.
Described is a hard disk drive that includes a disk with servo bits. The hard disk drive also includes a central processing unit that performs a servo routine using the servo bits, and a separate a notch hardware engine that is utilize by the central processing unit to perform a notch filter function in the servo routine. Off-loading the notch filter function onto a hardware engine reduces the overhead on the central processing unit when performing a servo routine. Utilizing the notch hardware engine can improve the speed of the central processing unit by a factor of 10×.
Referring to the drawings more particularly by reference numbers,
The disk drive 10 may include a plurality of heads 20 located adjacent to the disks 12. Each head 20 may have separate write and read elements. The write element magnetizes the disk 12 to write data. The read element senses the magnetic fields of the disks 12 to read data. By way of example, the read element may be constructed from a magneto-resistive material that has a resistance which varies linearly with changes in magnetic flux.
Each head 20 may be gimbal mounted to a suspension arm 26 as part of a head gimbal assembly (HGA). The suspension arms 26 are attached to an actuator arm 28 that is pivotally mounted to the base plate 16 by a bearing assembly 30. A voice coil 32 is attached to the actuator arm 28. The voice coil 32 is coupled to a magnet assembly 34 to create a voice coil motor (VCM) 36. Providing a current to the voice coil 32 will create a torque that swings the actuator arm 28 and moves the heads 20 across the disks 12.
The hard disk drive 10 may include a printed circuit board assembly 38 that includes one or more integrated circuits 40 coupled to a printed circuit board 42. The printed circuit board 40 is coupled to the voice coil 32, heads 20 and spindle motor 14 by wires (not shown).
The read/write channel circuit 58 is connected to a controller 64 through read and write channels 66 and 68, respectively, and read and write gates 70 and 72, respectively. The read gate 70 is enabled when data is to be read from the disks 12. The write gate 72 is enabled when writing data to the disks 12. The controller 64 may be a digital signal processor that operates in accordance with a software routine, including a routine(s) to write and read data from the disks 12. The read/write channel circuit 58 and controller 64 may also be connected to a motor control circuit 74 which controls the voice coil motor 36 and spindle motor 14 of the disk drive 10. The controller 64 may be connected to a non-volatile memory device 76. By way of example, the device 76 may be a read-only memory (“ROM”) that contains instructions that are read by the controller 64.
The controller 64 includes a central processing unit (“CPU”) 78. The CPU 78 performs software routines in accordance with data and instructions. The CPU 78 can perform a servo routine utilizing the A, B, C and D servo bits shown in
where,
y(k)=the transfer function.
u(k)=is a 32 bit input variable.
a1, a2, b0, b1 and b2=Q14 filter parameters.
The notch hardware engine 80 may be an application specific integrated circuit (“ASIC”) with add and multiplication elements that perform the stated calculation. By way of example, the notch hardware engine 80 may have known Boolean operators to perform the transfer function calculation. The hardware engine 80 may be on board the same chip as the CPU 78. Alternatively, the hardware engine 80 may be on a separate chip.
The notch filter engine 80 may perform notch filtering at different notches. For example, the engine 80 may perform notch filtering at 1×, 2×, 3× and 4×. The notch engine 80 may interact with the CPU 78 in the exemplary process shown in
In decision block 108 it is determined whether the process is to calculate 2× notches. If not, the process is finished and the CPU 64 can utilize the 1× notch calculations. If yes, a process of calculating the 2× notches and setting overflow and notch ready flags is performed in blocks 110, 112, 114, and 116. When the process is completed the CPU can utilize the 1× and 2× notch calculations in a servo routine.
Providing a separate notch hardware engine reduces the overload on the CPU 78. The CPU load reduction also reduces the amount of memory and code required to perform a servo routine.
While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that this invention not be limited to the specific constructions and arrangements shown and described, since various other modifications may occur to those ordinarily skilled in the art.
