Patent Application
20240113479
This disclosure relates generally to electronic devices and, more particularly, to socket interconnect structures and related methods.
A central processing unit (CPU) socket or CPU slot is a mechanical component that provides mechanical and electrical connections between a microprocessor and a printed circuit board (PCB). Sockets allow the CPU to be replaced without soldering.
In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. The figures are not to scale. Instead, the thickness of the layers or regions may be enlarged in the drawings. Although the figures show layers and regions with clean lines and boundaries, some or all of these lines and/or boundaries may be idealized. In reality, the boundaries and/or lines may be unobservable, blended, and/or irregular.
As used herein, unless otherwise stated, the term “above” describes the relationship of two parts relative to Earth. A first part is above a second part, if the second part has at least one part between Earth and the first part. Likewise, as used herein, a first part is “below” a second part when the first part is closer to the Earth than the second part. As noted above, a first part can be above or below a second part with one or more of: other parts therebetween, without other parts therebetween, with the first and second parts touching, or without the first and second parts being in direct contact with one another.
As used in this patent, stating that any part (e.g., a layer, film, area, region, or plate) is in any way on (e.g., positioned on, located on, disposed on, or formed on, etc.) another part, indicates that the referenced part is either in contact with the other part, or that the referenced part is above the other part with one or more intermediate part(s) located therebetween.
As used herein, connection references (e.g., attached, coupled, connected, and joined) may include intermediate members between the elements referenced by the connection reference and/or relative movement between those elements unless otherwise indicated. As such, connection references do not necessarily infer that two elements are directly connected and/or in fixed relation to each other. As used herein, stating that any part is in “contact” with another part is defined to mean that there is no intermediate part between the two parts.
Unless specifically stated otherwise, descriptors such as “first,” “second,” “third,” etc., are used herein without imputing or otherwise indicating any meaning of priority, physical order, arrangement in a list, and/or ordering in any way, but are merely used as labels and/or arbitrary names to distinguish elements for ease of understanding the disclosed examples. In some examples, the descriptor “first” may be used to refer to an element in the detailed description, while the same element may be referred to in a claim with a different descriptor such as “second” or “third.” In such instances, it should be understood that such descriptors are used merely for identifying those elements distinctly that might, for example, otherwise share a same name.
As used herein, “approximately” and “about” modify their subjects/values to recognize the potential presence of variations that occur in real world applications. For example, “approximately” and “about” may modify dimensions that may not be exact due to manufacturing tolerances and/or other real world imperfections as will be understood by persons of ordinary skill in the art. For example, “approximately” and “about” may indicate such dimensions may be within a tolerance range of +/−10% unless otherwise specified in the below description.
As used herein, the phrase “in communication,” including variations thereof, encompasses direct communication and/or indirect communication through one or more intermediary components, and does not require direct physical (e.g., wired) communication and/or constant communication, but rather additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and/or one-time events.
As used herein, “processor circuitry” is defined to include (i) one or more special purpose electrical circuits structured to perform specific operation(s) and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and/or (ii) one or more general purpose semiconductor-based electrical circuits programmable with instructions to perform specific operations and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of processor circuitry include programmable microprocessors, Field Programmable Gate Arrays (FPGAs) that may instantiate instructions, Central Processor Units (CPUs), Graphics Processor Units (GPUs), Digital Signal Processors (DSPs), XPUs, or microcontrollers and integrated circuits such as Application Specific Integrated Circuits (ASICs). For example, an XPU may be implemented by a heterogeneous computing system including multiple types of processor circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more DSPs, etc., and/or a combination thereof) and application programming interface(s) (API(s)) that may assign computing task(s) to whichever one(s) of the multiple types of processor circuitry is/are best suited to execute the computing task(s).
There is an ever-growing demand for increases in electrical bandwidth and/or signaling speeds (e.g., input/output speeds) of electronical components. For example, such increase in signaling speeds requires interconnect components of higher or faster bandwidth. For example, sockets (e.g., a land grid array (LGA) sockets, a ball grid array (BGA) socket, a pin grid array (PGA) socket, double-compression socket, etc.) are interconnect components that are employed to couple a central processing unit (CPU) or other semiconductor package (e.g., GPU, memory, etc.) and a motherboard. A typical central processing unit (CPU) socket includes a large array of individual contacts (e.g., pins) that provide electrical connections (e.g., power, signal nets, ground, etc.) between a CPU socket package and a mother board. If a CPU is connected via a CPU socket, the CPU is not soldered and can therefore be removed from the motherboard and/or replaced.
Higher signaling speeds require channels of higher bandwidth. As such, socket interconnect components of higher bandwidth are needed. However, increasing electrical bandwidth of a socket device is challenging because increasing electrical bandwidth results in an increased resonance frequency. Resonance frequencies can interfere (e.g., interrupt) signals being transferred via the socket component. For example, in signal processing, a Nyquist frequency is a frequency value that is one-half of a sampling rate (e.g., samples per second). When a highest frequency (bandwidth) of a signal is less than a Nyquist frequency of a sample, the resulting discrete-time sequence is free of distortion.
Thus, to avoid signal interference at a component level, resonance free frequencies can be up to two times a Nyquist frequency of the signal. For example, Peripheral Component Interconnect Express (PCIe) technology (e.g., PCIe 6.0) operates at frequencies between approximately twenty gigahertz (GHz) and thirty gigahertz (GHz). Providing socket devices that meet PCIe 6.0 electrical requirements (e.g., 64 gigabytes/second (Gbps) PAM4 modulation technique), while being resonance free up to 32 Gbps, is challenging. Next generation PCIe can operate at 128 Gbps in PAM4, which indicates a need for a resonance-free frequency range between approximately 50 GHz and 64 GHz.
Resonance frequencies of an interconnect component are dependent on the geometry and/or structure of the socket. For example, expanding the electrical bandwidth of the socket by shifting geometry-related resonances to higher frequencies can increase the input/output speed of the corresponding computing apparatus mounted in the socket.
In some sockets, dominant resonances are related to geometries of an individual pin and/or an arrangement of the pins that form a pin array. For instance, a geometry of the pins, a number of pins, an overall height of the pins, a pitch between pins, etc., can increase or decrease bandwidth capabilities of the socket. In addition, the overall height of the socket can also increase or decrease bandwidth capabilities of the socket. However, increasing the electrical bandwidth by modifying a geometry of the pins and/or the socket device is challenging due to manufacturing and/or mechanical limitations. Such manufacturing and/or mechanical limitations can significantly increase manufacturing costs of a socket device (e.g., by more than 30 percent).
For example, as an overall height of a pin (e.g., an interconnect for a socket) decreases, the overall height of the socket also decreases. The decreased height of socket decreases the working range or capability to absorb stack warpage. For instance, increasing an area of the socket device (e.g., a length and a width in an x-y plane or direction) while maintaining the same thickness or height (e.g., in a z-direction, a stack-up thickness in a vertical direction) reduces a mechanical strength of the socket device, making it more susceptible to warpage. As used herein, the x-direction and the y-direction are in a same plane (e.g., a horizontal plane), and the z-direction is in a plane (e.g., a vertical plane) perpendicular to the x-y plane. In some such examples, heat generated by circuitry can cause a circuit board to warp, thereby reducing performance. In some instances, as a thickness (e.g., in the z-direction, a height, etc.) of a pin decreases, a thickness (e.g., in the same z-direction, a height etc.) of a plastic housing supporting and/or surrounding the pin decreases. Decreasing of the plastic housing thickness can limit an ability of the plastic housing to retain a pin (e.g., metal interconnect).
In some examples, decreasing a pitch between the pins (e.g., a distance between the pins) can increase a risk of a short circuit between the pins. Decreasing a pitch of the pins also presents a manufacturing risk of having a small web of plastic form between the pins, which can cause a short circuit. Additionally, decreasing the pitch between the pins also decreases electrical shielding for signal pins. As the electrical shielding decreases, the signals communicated by the pins may overlap thereby degrading performance of the socket.
Additionally or alternatively, reducing a height of the pins can shift resonance frequencies to higher ranges. For example, a physical height of the pins influences a speed of the socket because there is less of an electrical distance for a signal to travel through pins having a smaller height compared to pins having a larger height (e.g., standard pins). However, decreasing a height of the pins reduces the ability of the pins to deflect in a vertical direction when coupling to a motherboard or a package. Thus, reduction in pin height can cause mechanical challenges making it difficult to apply a sufficient load to make contact between the pins and respective pads of a motherboard and/or package. In some instances, a smaller height socket can restrict a form factor of land-side capacitors, limiting a decoupling capacity and/or increasing manufacturing costs. For example, land-side capacitors need to be a certain height to function (e.g., carry a charge, discharge a charge). As the height of the pins decreases, a height of the land-side capacitors must also decrease, which increases the costs of manufacturing land-side capacitors able to hold the same charge as capacitors associated with taller pins.
Examples disclosed herein provide a cost-effective alternative approach for enabling sockets to support higher speed and higher bandwidth for high speed input/output components. Specifically, example sockets disclosed herein employ a ground structure to ground two or more pins of the socket. In particular, example ground structures disclosed herein provide a common ground for a plurality of grounding pins (e.g., a subset of ground pins) surrounding signal pins that carry signals (e.g., differential pins, differential signal pins, high-speed pins). To improve bandwidth, example sockets disclosed herein employ a ground structure positioned between respective ends (e.g., between respective upper and lower ends) of the pins to achieve electrical characteristics associated with shortening the pins without actually making the pins physically shorter. In other words, a height of the pins is not mechanically or physically shortened but the pins nonetheless exhibit behavior from an electrical signal standpoint that would be present had shorter pins been employed (e.g., the ground structure is positioned to reduce the electrical path along the pins to less than the full length of the pins). While the height of the pins is not actually or physically shortened, example ground structures disclosed herein effectively improve electrical characteristics of the pins as if the pins where shortened. As a result, example ground structures disclosed herein enable a physical characteristic or height of the pins to provide mechanical advantages (e.g., loading advantages) while providing electrical advantages by improving bandwidth capabilities of the sockets.
Example ground structures disclosed herein enable ground pins of a socket to be electrically connected in a selected area of the pin array and/or socket. In some examples, a subset of pins is electrically connected via example ground structures disclosed herein to provide a mesh of ground pins in a socket. For example, example ground structures disclosed herein are provided in a socket between a first end of the pins that engage an integrated circuit (IC) package and a second end of the pins opposite the first end that engage a motherboard or printed circuit board. In some examples, ground structures disclosed herein can be configured to electrically couple all ground pins surrounding a differential pin pair area. In some examples, ground structures disclosed herein can be structured to group the ground pins into a plurality of subsets and electrically couple only the ground pins associated with a given subset. In other words, example ground structures disclosed herein can electrically couple subsets of ground pins, where a first group of ground pins associated with a first subset of ground pins are electrically decoupled from (e.g., not electrically coupled with) a second group of ground pins associated with a second subset of ground pins. Each of the corresponding subsets can be positioned and/or associated with a differential signal pair to reduce crosstalk between the signal pins of the differential signal pair.
Examples disclosed herein can increase a bandwidth of a socket by more than 35% without changing a geometry or array of a contact design (e.g., without employing shorter pins or a shorter pin array). In other words, examples disclosed herein improve bandwidth by shifting resonance frequencies higher without requiring geometric changes to pins and/or a pin array (e.g., pitch, number of pins, etc.) of a socket. For example, absent ground structures disclosed herein, a socket (e.g., a socket-E pin) having inherent resonance of approximately twenty-two GHz will exhibit a reduced bandwidth. In contrast, a socket (e.g., a socket-E pin) employing example ground structures disclosed herein can provide inherent resonance of approximately thirty GHz, which is approximately a thirty-four percent to thirty-six percent improvement over the prior approach. In some examples, ground structures disclosed herein can provide a socket that is resonance free between fifty GHz and sixty-four GHz.
The array 101 of contacts 102 of the illustrated example forms a grid-like pattern (e.g., a rectangular pattern). The socket 100 of the illustrated example has a length 104 along a first axis (e.g., an x-axis), a width 106 along a second axis (e.g., a y-axis), and a thickness or height 108 along a third axis (e.g., a z-axis). In some examples, the length 104 is approximately one hundred millimeters, the width 106 is approximately seventy millimeters, and the height 108 is approximately twenty millimeters. Other dimensions are likewise possible to suit desired applications. The socket 100 of the illustrated example exhibits between approximately sixty thousand and approximately eighty thousand contacts 102. In some examples, the socket 100 of the illustrated example has seventy thousand contacts 102.
The example socket 100 of the illustrated example is a land grid array (LGA) socket. However, in other examples, ground structures disclosed herein are implemented with a ball grid array (BGA) socket, double-compression socket, a zero insertion force (ZIF) socket, Plastic Pin Grid Array (PPGA) socket, staggered pin grid array (SPGA) socket, pin grid array (PGA) socket, and/or any other example socket(s).
The differential pairs 206a-c are positioned in a first column in the orientation of
The example socket 100 implemented with the example array 101 of
Referring to
The socket 100 (e.g., the ground structure 302 and the housing 304) includes a plurality of openings 303 (e.g., apertures) to receive respective ones of the contacts 102 of the array 101 of
The openings 303 of the illustrated example have a first dimension 305 (e.g., a first length) and a second dimension 307 (e.g., a second length). The openings 303 of the illustrated example have a square shape or profile. In other words, the first dimension 305 is substantially similar to (e.g., equal to or within a tolerance of 5%-10%) the second dimension 307. However, in other examples, the openings 303 can have a rectangular shape, a circular or cylindrical shape, an oblong shape, and/or any other shape. The openings 303 extend (e.g. entirely) through the socket 100 (e.g., in the z-direction in the orientation of
In particular, the housing 304 of the illustrated example defines a plurality of first openings 320 (e.g., housing signal pin openings) and a plurality of second openings 322 (e.g., housing ground pin openings). The ground structure 302 of the illustrated example includes a plurality of third openings 324 (e.g., ground structure ground pin openings). When the ground structure 302 is coupled to the housing 304, the third openings 324 of the ground structure 302 align (e.g., coaxially and/or concentrically align) with the second openings 322 of the housing 304. The plurality of ground pins 204 are located in (e.g., the openings 303 defined by) respective ones of the second openings 322 and the third openings 324. The signal pins 202 (e.g., the differential pairs) are located in (e.g., the openings 303 defined by) respective ones of the first openings 320 of the housing 304. The signal pins 202 are electrically isolated or insulated from the ground structure 302 when the signal pins 202 are positioned in the respective ones of the first openings 320 of the housing 304. In other words, the signal pins 202 do not engage and/or are spaced away from the ground structure 302.
In general, the ground pins 204 of the illustrated example electrically isolate the signal pins 202 to reduce crosstalk interference between the signal pins 202. In the illustrated example, the portion 300 of the socket 100 of
To provide shielding to the first differential pair 310, the ground structure 302 of the illustrated example includes a first portion 302a (e.g., a first ground structure) to electrically couple the ground pins 204 of the first group 312 of the ground pins 204 when located in respective ones of the second openings 322 and the third openings 324 of the first portion 302a. Similarly, to provide shielding to the second differential pair 314, the ground structure 302 of the illustrated example includes a second portion 302b (e.g., a second ground structure) to electrically couple the ground pins 204 of second group 316 when located in respective ones of the second openings 322 and the third openings 324 of the second portion 302b. Thus, in the illustrated example, the first group 312 of the ground pins 204 are electrically coupled via a first portion 302a of the ground structure 302 and the second group 316 of the ground pins 204 are electrically coupled via a second portion 302b of the ground structure 302. Further, as shown in this example, the first and second portions 302a, 302b of the ground structure 302 extend completely (e.g., continuously) around the corresponding different pairs 310, 314 of the signal pins 202. Thus, the first portion 302a of ground pins 204 completely surrounds the first differential pair 310. The second portion 302b of ground pins 204 completely surrounds the second differential pair 314.
Additionally, the first group 312 of the ground pins 204 are not electrically coupled to the second group 316 of the ground pins 204. Thus, the first group 312 of the ground pins 204 are electrically decoupled from the second group of the ground pins 204. To electrically decouple the first group 312 and the second group 316 of ground pins 204, the first portion 302a is spaced from the second portion 302b by a distance 311 (e.g., a separation or space). The housing 304 provides an electrical shield or insulation between the first portion 302a of the ground structure 302 and the second portion 302b of the ground structure 302. In other words, the first portion 302a of the ground structure 302 of the illustrated example is separate from (e.g., decoupled or disconnected from) the second portion 302b of the ground structure 302. Thus, the housing 304 electrically insulates the first group 312 of ground pins 204 and the second group 316 of the ground pins 204. In some examples, all of the ground pins 204 of the array 101 can be electrically coupled via the ground structure 302. For example, the ground pins 204 of the first subset 306 and the ground pins 204 of the second subset 308 can be electrically coupled (e.g., via one or more traces, structures, and/or other conductive elements formed with the housing 304). The pins 202, 204 of the illustrated example include example protrusions 325 (e.g., teeth, hooks, etc.) that protrude from an example body 327 (e.g., a side wall) of the pins 202, 204 that couple (e.g., embed) with the housing 304 and/or the ground structure 302 to couple the contacts 102 to the ground structure 302 and/or the housing 304. The protrusions 325 that protrude from the body 327 are to protrude from the base portion 210 of the pins 202, 204, while the example of
Referring to
Referring to
The ground structures 302, 352, 362 of the illustrated examples are made of an electrically conductive material such as copper, aluminum and/or any other suitable electrically conductive material(s). The housing 304, 354, 364 of the illustrated examples are composed of a non-conductive material such as plastic and/or any other suitable insulating or non-conductive material(s).
In the illustrated example of
In operation, the ground structure 302 electrically divides the ground pins 204 into an upper portion and a lower portion which shortens the time for a response from a return path (e.g., a distance of an electrical path), which increases the resonance frequency. By increasing the resonance frequency, the speed and bandwidth of the socket 100 is increased. The socket 100 of the illustrated example provides a cost-effective approach that can expand the socket bandwidth by at least 35% without changing a design of the contacts 102 (e.g., the overall height 503, pitch, number of contacts 102 of the array 101, etc.). The examples disclosed herein remove the requirement to have more ground pins 204 which limits pin count growth and causes minimum impact to the existing CPU loading solution.
While an example manner of forming the example socket 100 has been illustrated in
Referring to the example method 600 of
Next, a housing of the socket is fabricated to support the ground structure (block 604). For example, the housing can be fabricated with (e.g., provided to) the ground structure via injection-molding. In this manner, the housing is molded with the ground structure. Referring to
The pins are then coupled within the ground structure and the housing (block 606). Referring to
In the illustrated example of
At block 608, solder joints can be coupled to the pins. Referring to
Those components of the example socket 900 that are substantially similar to the components of the socket 100 of
While an example manner of forming the example socket 100 has been illustrated in
The method 800 of
At block 804, a ground structure is provided for the socket. Specifically, the ground structure is fabricated or obtained. The ground structure is plate made of an electrically conductive material. Referring to
At block 806, the ground structure is coupled to the housing. Referring to
At block 808, a plurality of pins are coupled to a socket. Referring to
At block 810, solder joints are coupled to the pins. Referring to
In other examples, example sockets disclosed herein can be manufactured using other manufacturing process(es) and/or techniques. For example, a socket can be formed by insert or overmolding the socket assembly together. For instance, the pins may be skived pins which can be positioned inside a frame (e.g., skived)
The foregoing examples of the sockets 100, 350, 360 and 900 teach or suggest different features. Although each example socket 100, 350, 360 and 900 disclosed above has certain features, it should be understood that it is not necessary for a particular feature of one example to be used exclusively with that example. Instead, any of the features described above and/or depicted in the drawings can be combined with any of the examples, in addition to or in substitution for any of the other features of those examples. One example's features are not mutually exclusive to another example's features. Instead, the scope of this disclosure encompasses any combination of any of the features.
There are other manufacturing processes to electrically connect the ground structure 302 to the pins 202, 204. One alternative is to use a skived bus bar. The skived bus bar includes skived pins which generate manufacturing options. One manufacturing option is to make the socket 100 an insert molded or over-molded frame that has the ground pins 204 inside the frame already (through a skived process), while the signal pins 202 are stitched such as in the process of
In some examples, to electrically connect the ground pins 204 in a selected area of the socket, a fixed location for the ground pins 204 is to be finalized. Typically, a fixed location for the ground pins 204 would reduce the flexibility of the CPU pinout arrangement. However, as the CPU I/O data rate increases for PCIe 6.0 and beyond, the differential pinout is likely to be uniformly arranged. The uniform arrangement for PCIe 6.0 results in a regular pin assignment and well-defined differential area without customization as the locations of the grounds pins 204 are predictable. Thus, a requirement for fixed ground pin locations is not an issue for the techniques disclosed herein. In some examples, a mixed pitch socket pin pattern has the differential pinout in a separate patch.
The example sockets 100, 350, 360, 900 disclosed herein may be included in any suitable electronic component.
The IC device 1100 may include one or more device layers 1104 disposed on the die substrate 1102. The device layer 1104 may include features of one or more transistors 1140 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1102. The device layer 1104 may include, for example, one or more source and/or drain (S/D) regions 1120, a gate 1122 to control current flow in the transistors 1140 between the S/D regions 1120, and one or more S/D contacts 1124 to route electrical signals to/from the S/D regions 1120. The transistors 1140 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 1140 are not limited to the type and configuration depicted in
Each transistor 1140 may include a gate 1122 formed of at least two layers, a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some examples, an annealing process may be conducted on the gate dielectric to improve its quality when a high-k material is used.
The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1140 is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).
In some examples, when viewed as a cross-section of the transistor 1140 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the die substrate 1102 and two sidewall portions that are substantially perpendicular to the top surface of the die substrate 1102. In other examples, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the die substrate 1102 and does not include sidewall portions substantially perpendicular to the top surface of the die substrate 1102. In other examples, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
In some examples, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some examples, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
The S/D regions 1120 may be formed within the die substrate 1102 adjacent to the gate 1122 of each transistor 1140. The S/D regions 1120 may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the die substrate 1102 to form the S/D regions 1120. An annealing process that activates the dopants and causes them to diffuse farther into the die substrate 1102 may follow the ion-implantation process. In the latter process, the die substrate 1102 may first be etched to form recesses at the locations of the S/D regions 1120. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 1120. In some implementations, the S/D regions 1120 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some examples, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some examples, the S/D regions 1120 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further examples, one or more layers of metal and/or metal alloys may be used to form the S/D regions 1120.
Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors 1140) of the device layer 1104 through one or more interconnect layers disposed on the device layer 1104 (illustrated in
The interconnect structures 1128 may be arranged within the interconnect layers 1106-1110 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 1128 depicted in
In some examples, the interconnect structures 1128 may include lines 1128a and/or vias 1128b filled with an electrically conductive material such as a metal. The lines 1128a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the die substrate 1102 upon which the device layer 1104 is formed. For example, the lines 1128a may route electrical signals in a direction in and out of the page from the perspective of
The interconnect layers 1106-1110 may include a dielectric material 1126 disposed between the interconnect structures 1128, as shown in
A first interconnect layer 1106 (referred to as Metal 1 or “M1”) may be formed directly on the device layer 1104. In some examples, the first interconnect layer 1106 may include lines 1128a and/or vias 1128b, as shown. The lines 1128a of the first interconnect layer 1106 may be coupled with contacts (e.g., the S/D contacts 1124) of the device layer 1104.
A second interconnect layer 1108 (referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer 1106. In some examples, the second interconnect layer 1108 may include vias 1128b to couple the lines 1128a of the second interconnect layer 1108 with the lines 1128a of the first interconnect layer 1106. Although the lines 1128a and the vias 1128b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 1108) for the sake of clarity, the lines 1128a and the vias 1128b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some examples.
A third interconnect layer 1110 (referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 1108 according to similar techniques and configurations described in connection with the second interconnect layer 1108 or the first interconnect layer 1106. In some examples, the interconnect layers that are “higher up” in the metallization stack 1119 in the IC device 1100 (i.e., further away from the device layer 1104) may be thicker.
The IC device 1100 may include a solder resist material 1134 (e.g., polyimide or similar material) and one or more conductive contacts 1136 formed on the interconnect layers 1106-1110. In
The IC package 1200 may include a die 1206 coupled to the package substrate 1202 via conductive contacts 1204 of the die 1206, first-level interconnects 1208, and conductive contacts 1210 of the package substrate 1202. The conductive contacts 1210 may be coupled to conductive pathways 1212 through the package substrate 1202, allowing circuitry within the die 1206 to electrically couple to various ones of the conductive contacts 1214 or to the substrate that may connect to the example sockets 100, 350, 360, 900 (or to other devices included in the package substrate 1202, not shown). The first-level interconnects 1208 illustrated in
In some examples, an underfill material 1216 may be disposed between the die 1206 and the package substrate 1202 around the first-level interconnects 1208, and a mold compound 1218 may be disposed around the die 1206 and in contact with the package substrate 1202. In some examples, the underfill material 1216 may be the same as the mold compound 1218. Example materials that may be used for the underfill material 1216 and the mold compound 1218 are epoxy mold materials, as suitable. Second-level interconnects 1220 may be coupled to the conductive contacts 1214. The second-level interconnects 1220 illustrated in
In
Although the IC package 1200 illustrated in
In some examples, the circuit board 1302 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1302. In other examples, the circuit board 1302 may be a non-PCB substrate.
The IC device assembly 1300 illustrated in
The package-on-interposer structure 1336 may include an IC package 1320 coupled to an interposer 1304 by coupling components 1318. The coupling components 1318 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1316. Although a single IC package 1320 is shown in
In some examples, the interposer 1304 may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some examples, the interposer 1304 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some examples, the interposer 1304 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 1304 may include metal interconnects 1308 and vias 1310, including but not limited to through-silicon vias (TSVs) 1306. The interposer 1304 may further include embedded devices 1314, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1304. The package-on-interposer structure 1336 may take the form of any of the package-on-interposer structures known in the art.
The IC device assembly 1300 may include an IC package 1324 coupled to the first face 1340 of the circuit board 1302 by coupling components 1322. The coupling components 1322 may take the form of any of the examples discussed above with reference to the coupling components 1316, and the IC package 1324 may take the form of any of the examples discussed above with reference to the IC package 1320.
The IC device assembly 1300 illustrated in
Additionally, in various examples, the electrical device 1400 may not include one or more of the components illustrated in
The electrical device 1400 may include a processor circuitry 1402 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processor circuitry 1402 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The electrical device 1400 may include a memory 1404, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some examples, the memory 1404 may include memory that shares a die with the processor circuitry 1402. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).
In some examples, the electrical device 1400 may include a communication chip 1412 (e.g., one or more communication chips). For example, the communication chip 1412 may be configured for managing wireless communications for the transfer of data to and from the electrical device 1400. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some examples they might not.
The communication chip 1412 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra-mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 1412 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1412 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1412 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 1412 may operate in accordance with other wireless protocols in other examples. The electrical device 1400 may include an antenna 1422 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some examples, the communication chip 1412 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 1412 may include multiple communication chips. For instance, a first communication chip 1412 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 1412 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some examples, a first communication chip 1412 may be dedicated to wireless communications, and a second communication chip 1412 may be dedicated to wired communications.
The electrical device 1400 may include battery/power circuitry 1414. The battery/power circuitry 1414 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device 1400 to an energy source separate from the electrical device 1400 (e.g., AC line power).
The electrical device 1400 may include a display 1406 (or corresponding interface circuitry, as discussed above). The display 1406 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.
The electrical device 1400 may include an audio output device 1408 (or corresponding interface circuitry, as discussed above). The audio output device 1408 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds.
The electrical device 1400 may include an audio input device 1424 (or corresponding interface circuitry, as discussed above). The audio input device 1424 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
The electrical device 1400 may include a GPS circuitry 1418. The GPS circuitry 1418 may be in communication with a satellite-based system and may receive a location of the electrical device 1400, as known in the art.
The electrical device 1400 may include any other output device 1410 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The electrical device 1400 may include any other input device 1420 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
The electrical device 1400 may have any desired form factor, such as a hand-held or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop electrical device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some examples, the electrical device 1400 may be any other electronic device that processes data.
“Including” and “comprising” (and all forms and tenses thereof) are used herein to be open ended terms. Thus, whenever a claim employs any form of “include” or “comprise” (e.g., comprises, includes, comprising, including, having, etc.) as a preamble or within a claim recitation of any kind, it is to be understood that additional elements, terms, etc., may be present without falling outside the scope of the corresponding claim or recitation. As used herein, when the phrase “at least” is used as the transition term in, for example, a preamble of a claim, it is open-ended in the same manner as the term “comprising” and “including” are open ended. The term “and/or” when used, for example, in a form such as A, B, and/or C refers to any combination or subset of A, B, C such as (1) A alone, (2) B alone, (3) C alone, (4) A with B, (5) A with C, (6) B with C, or (7) A with B and with C. As used herein in the context of describing structures, components, items, objects and/or things, the phrase “at least one of A and B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects and/or things, the phrase “at least one of A or B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the performance or execution of processes, instructions, actions, activities and/or steps, the phrase “at least one of A and B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the performance or execution of processes, instructions, actions, activities and/or steps, the phrase “at least one of A or B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.
As used herein, singular references (e.g., “a”, “an”, “first”, “second”, etc.) do not exclude a plurality. The term “a” or “an” object, as used herein, refers to one or more of that object. The terms “a” (or “an”), “one or more”, and “at least one” are used interchangeably herein. Furthermore, although individually listed, a plurality of means, elements or method actions may be implemented by, e.g., the same entity or object. Additionally, although individual features may be included in different examples or claims, these may possibly be combined, and the inclusion in different examples or claims does not imply that a combination of features is not feasible and/or advantageous.
From the foregoing, it will be appreciated that example systems, methods, apparatus, and articles of manufacture have been disclosed that increase the resonance frequency of a socket, which increases the speed that the socket is able to transfer data. Disclosed systems, methods, apparatus, and articles of manufacture improve the efficiency of using a computing device by increasing the speed at which the socket is able to transfer data. Disclosed systems, methods, apparatus, and articles of manufacture are accordingly directed to one or more improvement(s) in the operation of a machine such as a computer or other electronic and/or mechanical device. Additionally, the example sockets disclosed herein provide a cost-effective approach that can expand the socket bandwidth by at least 35% without changing the design of the contacts (e.g., pins, interconnects, conductive contacts). The techniques disclosed herein remove the requirement to have more ground pins which limits pin count growth and causes minimum impact to the existing CPU loading solution.
Example methods, apparatus, systems, and articles of manufacture to extend socket electrical bandwidth through ground structure enhancement are disclosed herein.
Example 1 includes an apparatus including a housing defining a plurality of first openings and a plurality of second openings, a ground structure coupled to the housing, the ground structure defining a plurality of third openings, the third openings of the ground structure to align with the second openings of the housing when the ground structure is coupled to the housing, a plurality of ground pins located in respective ones of the second openings and third openings, the ground structure to electrically couple different ones of the ground pins, and a plurality of signal pins located in respective ones of the first openings of the housing, the signal pins electrically isolated from the ground structure.
Example 2 includes the apparatus of example 1, wherein the ground structure is to electrically bifurcate the ground pins into an upper portion of the ground pins and a lower portion of the ground pins without decreasing a physical overall length of the ground pins.
Example 3 includes the apparatus of example 1, wherein the ground structure engages the ground pins at a point between opposite ends of the ground pins.
Example 4 includes the apparatus of example 3, wherein the ground structure engages the ground pins at a midpoint between two equal portions.
Example 5 includes the apparatus of example 1, wherein the ground structure is embedded between a first surface of the housing and a second surface of the housing opposite the first surface.
Example 6 includes the apparatus of example 1, wherein the ground structure includes a first portion and a second portion, the first portion of the ground structure associated with a first group of the ground pins and a first pair of the signal pins, the second portion of the ground structure associated with a second group of the ground pins and a second pair of the signal pins.
Example 7 includes the apparatus of example 6, wherein the first portion of the ground structure is electrically decoupled from the second portion of the ground structure.
Example 8 includes the apparatus of example 7, wherein the first group of ground pins are electrically coupled via the first portion of the ground structure and the second group of ground pins are electrically coupled via the second portion of the ground structure.
Example 9 includes a socket including a housing having a plurality of first ground openings and signal openings, and a ground structure coupled to the housing, the ground structure including a plurality of second ground openings, the first ground openings to align with respective ones of the second ground openings when the ground structure is coupled to the housing.
Example 10 includes the socket of example 9, further including a plurality of ground pins positioned in respective ones of the first ground openings and the second ground openings.
Example 11 includes the socket of example 10 wherein the ground structure is to electrically couple the ground pins.
Example 12 includes the socket of example 10, further including a plurality of signal pins located in respective ones of the signal openings of the housing.
Example 13 includes the socket of example 12, wherein the signal pins are electrically isolated from the ground structure.
Example 14 includes the socket of example 13, wherein the ground pins surround the signal pins to reduce crosstalk interference between the signal pins.
Example 15 includes the socket of example 9, wherein the ground structure is made of an electrically conductive material and the housing is made of an electrically insulating material.
Example 16 includes the socket of example 15, wherein the ground structure is positioned between respective ends of the ground pins.
Example 17 includes a method including providing a ground structure for a socket, fabricating a housing for the socket to support the ground structure, and inserting ground pins into the ground structure, the ground structure to engage a body of the ground pins to electrically couple the ground pins.
Example 18 includes the method of example 17, wherein fabricating the housing includes overmolding the housing and the ground structure via injection molding.
Example 19 includes the method of example 17, wherein fabricating the housing includes an injection-molding process prior to coupling the housing to the ground structure.
Example 20 includes the method of example 19, further including attaching the ground structure and the housing via a press-fit manufacturing process.
The following claims are hereby incorporated into this Detailed Description by this reference. Although certain example systems, methods, apparatus, and articles of manufacture have been disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, methods, apparatus, and articles of manufacture fairly falling within the scope of the claims of this patent.
