SOFT-START CIRCUIT AND METHOD FOR LOW-DROPOUT VOLTAGE REGULATORS

Abstract

A low drop-out voltage regulator having soft-start. A low drop-out regulator circuit is provided having an input node, an output node, a power FET connected by a source and drain between the input node and the output node, and a feedback circuit having an output connected and providing a control signal to a gate of the power FET. A current limit circuit is configured to control the power FET to limit the current through it when the voltage across a controllable sense resistor connected to conduct a current representing the current through the power FET exceeds a predetermined limit value. At start-up, control unit provides a control signal to the controllable resistor to cause the resistance value of the controllable resistor to decrease incrementally in value at respective predetermined incremental times during a predetermined time interval.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a technique for powering LDO regulators from a USB bus.

FIG. 2 is a circuit diagram of a typical prior art LDO regulator having current limiting.

FIG. 3 is a circuit diagram of a preferred embodiment of an LDO regulator implementing the invention.

FIG. 4 is a circuit diagram of the digitally controlled resistor of FIG. 3.

Claims

1. A low drop-out voltage regulator, comprising: a low drop-out regulator circuit having an input node, an output node, a power FET connected by a source and drain between the input node and the output node, and a feedback circuit having an output connected and providing a control signal to a gate of the power FET;a current limit circuit configured to control the power FET to limit the current therethrough when the voltage across a controllable sense resistor connected to conduct a current representing the current through the power FET exceeds a predetermined limit value; anda control unit adapted to provide, at start-up, a control signal to the controllable resistor to cause the resistance value of the controllable resistor to decrease incrementally during a predetermined time interval.

2. A low drop-out voltage regulator according to claim 1 wherein the controllable resistor comprises a plurality of resistors that are configured to be connected in parallel in selectable numbers under control of the control signal.

3. A low drop-out voltage regulator according to claim 2, wherein: the controllable resistor comprises the plurality of resistors each connected in series with a respective switch to thereby comprise a plurality of switch-resistor branches, with the plurality of resistor-switch branches being connected in parallel.

4. A low drop-out voltage regulator according to claim 2 wherein the controllable resistor further comprises a fixed resistor connected in parallel with the plurality of resistor-switch branches.

5. A low drop-out voltage regulator according to claim 1 wherein the control unit is configured to provide a control signal that controls the controllable resistor to decrease incrementally in value during the predetermined time interval.

6. A low drop-out voltage regulator according to claim 5 wherein the control unit is configured to provide a control signal that controls the controllable resistor to decrease incrementally in value at respective predetermined incremental times during the predetermined time interval.

7. A low drop-out voltage regulator according to claim 1, wherein: the low drop-out regulator circuit comprises an error amplifier configured to provide an output corresponding to the difference between a first reference voltage and a feedback voltage,a buffer amplifier receiving at an input the error amplifier output and providing at an output a power FET control signal,a feedback circuit configured to sense the voltage at the output node and to provide the feedback voltage at a level corresponding to the voltage at the output node; andthe current limit circuit comprises a sense FET connected by a source and a drain between one terminal of the controllable sense resistor, the other terminal of the sense resistor being connected to the input node, and the output node, a gate of the sense FET being connected to receive the power FET control signal,a current-limit amplifier having a first input connected to the common connection node of the sense resistor and the sense FET and having a second input connected to a second reference voltage, configured to provide at an output a voltage representing the difference between the voltages at the first and second inputs, anda current-limit FET connected by a source and drain between the input of the buffer amplifier and the input node, a gate of the current-limit FET being connected to the output of the current-limit amplifier.

8. A low drop-out voltage regulator according to claim 7 further comprising: a voltage-follower stage comprising a current source connected to the input node and providing a current at an output thereof, and a voltage-follower FET connected by a source and a drain between the current source output and ground, a gate of the voltage-follower FET being connected to the input of the buffer amplifier, anda capacitor connected between the common connection node of the current source and the voltage-follower FET and the output of the current-limit amplifier.

9. A low drop-out voltage regulator, comprising: a power FET connected by a source and a drain between an input node for receiving an input voltage and an output node for providing an output voltage;a feedback loop configured to compare a voltage representing the output voltage to a first reference voltage and provide an output signal representing the difference between them to a gate of the power FET;a controllable sense resistor having a first terminal connected to the input node;a sense FET connected by a source and a drain between a second terminal of the controllable sense resistor and the output node, and connected to receive at a gate the output signal of the feedback loop;a current limit amplifier having a first input connected to the connection node of the controllable sense resistor and the sense FET and a second input connected to receive a second reference voltage representing a current limit, and having an output for providing an output signal when the voltage at the connection node of the controllable sense resistor and the sense FET goes below the second reference voltage;a limit FET connected by a source and a drain between the input node and the output of the feedback loop and having a gate connected to the output of the current limit amplifier; anda control unit adapted to provide, at start-up, a control signal to the controllable resistor to cause the resistance value of the controllable resistor to decrease over a predetermined time to a final value.

10. A method for soft start in a low drop-out voltage regulator comprising an input node, an output node, a power FET connected by a source and drain between the input node and the output node, and a feedback circuit having an output connected and providing a control signal to a gate of the power FET, comprising the steps of: controlling the power FET to limit the current therethrough when the voltage across a controllable sense resistor connected to conduct a current representing the current through the power FET exceeds a predetermined limit value; andproviding, at start-up, a control signal to the controllable resistor to cause the resistance value of the controllable resistor to decrease incrementally in value at respective predetermined incremental times during a predetermined time interval.