Patent Application
20080030177
Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. In the following discussion and in the claims, the terms “include” and “comprise” are used in an open-ended fashion. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Thus, if a first device is coupled to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
The soft-start linear voltage regulator circuit 29 has a first mode and a second mode. For example, the first mode can be thought of as a current-limiting mode while the second mode be thought of as a normal mode. The capacitive load circuit 34 is an “asynchronous” capacitive load. More specifically, when the soft-start linear voltage regulator circuit 29 changes from the current-limiting mode to the normal mode, the capacitive load circuit 34 provides a a large capacitive load to node 36. When the soft-start linear voltage regulator circuit 29 changes from the normal mode to the current-limiting mode, the capacitive load circuit 34 provides a small capacitive load to node 36. When the soft-start linear voltage regulator circuit 29 is turned off, i.e., the soft-start linear voltage regulator circuit 29 does not provide the voltage regulating function, the capacitive load circuit 34 pulls high the voltage at node 36, so that the soft-start linear voltage regulator circuit 29 enters, or approaches, the current-limiting mode.
When the soft-start linear voltage regulator circuit 29 is initially started up, Iout is limited because the soft-start linear voltage regulator circuit 29 is in, or close to, the current-limiting mode. At this time, the soft-start linear voltage regulator circuit 29 changes slowly from the current-limiting mode to the normal mode by gradually changing the voltage at node 36, resulting in a slowly increased Iout.
In a normal operation, when over-current occurs, the voltage at node 36 causes the soft-start linear voltage regulator circuit 29 to change from the normal mode to the current-limiting mode. The response time of over-current protection will not be affected because the capacitive load circuit 34 is now a small capacitive load.
Please refer to
In this embodiment, the linear voltage regulator 202, including a control module 210, a pass transistor Mx, and resistors R21, R22, is used to regulate the output voltage Vout. The functionality of the control module 210, which can be implemented by a low drop out (LDO) control circuit, is controlled by an enabling signal EN. A voltage regulating function is performed when, for example, EN is logic low.
As to the current sensing and comparing circuit 204, it includes a plurality of transistors M21-M22. It should be noted that the transistor M22 is biased by a bias voltage Vbias. The current sensing and comparing circuit 204 is capable of sensing the output current Iout to obtain a sensed output current IR and monitoring whether the sensed output current IR exceeds a predetermined current value Ilimit. That is, the current sensing and comparing circuit 204 senses the output current Iout and outputs a result signal according to the sensed output current IR and the predetermined current value Ilimit. If the sensed output current IR exceeds the predetermined current value Ilimit, it implies that the output current Iout exceeds a desired current limit. In this embodiment, the biased transistor M22 serves as a current source for defining the predetermined current value Ilimit. Additionally, the sensed output current IR passing through the current mirror path where the transistor M22 is located is designed to be less than the actual output current Iout. The result signal, which represents a comparison result between the sensed output current IR and the predetermined current value Ilimit, is presented at node A to control the voltage level thereof. However, this is merely provided as an example. Assume the same current sensing and comparing function is implemented; other circuit designs are possible for the current sensing and comparing circuit 204.
The control circuit 208 includes a plurality of transistors M26-M29, where the on/off status of the transistor M26 is controlled by the enabling signal EN. The control circuit 208 is utilized to tune the voltage V1 according to the result signal given by the current sensing and comparing circuit 204.
The key difference between the soft-start linear voltage regulator circuit 200 and the related art linear voltage regulator circuit 100 is the inclusion of the capacitive load circuit 206. As shown in
The current sensing and limiting circuit, implemented by the current sensing and comparing circuit 204, the capacitive load circuit 206, and control circuit 208, ensures the output current Iout is within a predetermined level. More specifically, when the sensed output current IR exceeds the predetermined current value Ilimit, the current sensing and limiting circuit will lower the output current Iout to keep the sensed output current IR at a highest acceptable value, said Ilimit. In this embodiment, when the enabling signal EN is logic low, the soft-start linear voltage regulator circuit 200 works normally for voltage-regulating purposes. Please note that the enabling signal ENb is logic high accordingly. On the other hand, once the enabling signal EN becomes logic high, the soft-start linear voltage regulator circuit 200 is turned off, and then the output voltage Vout is lowered to 0V. In addition, the voltage level at node A is pulled up to approach the input voltage Vin.
Next, when the soft-start linear voltage regulator circuit 200 starts up, the voltage level at node A is pulled down from its original level approximately equal to the input voltage Vin. The voltage level at node B is decreased as the voltage level at node A is decreased due to the activated transistor M22. Once the decreasing voltage level at node B causes the transistors M23, M24 to be turned on, the capacitance viewed by node A is magnified. In the capacitive load circuit 206, the aspect ratio (W/L) of the transistor M23 and the aspect ratio of the transistor M24 are K1 and K2, where K2/K1=K (K>1). In other words, a current mirror ratio of a second current mirror path corresponding to the transistor M24 to a first current mirror path corresponding to the transistor M23 is K. Therefore, the equivalent capacitive load viewed by node A is substantially equal to (1+K)*CL. In this embodiment, K is significantly greater than one. The equivalent capacitive load viewed by node A, therefore, is substantially equal to K*CL. Please note that the capacitive load CL has small capacitance such that the chip area for implementing the capacitive load circuit 206 is small. However, with the specific configuration shown in
The voltage level at node A is slowly decreased because of the large capacitance K*CL. In other words, the voltage level at node A is slowly pulled down. The transistor M29 is gradually turned off, leading to a gradually increasing gate voltage of the transistor M28 and a slowly decreasing voltage V1. Therefore, the output current Iout passing through the pass transistor Mx increases slowly until it becomes stable. This prevents an instant large current from causing unpredictable damage to the soft-start linear voltage regulator circuit 200 or other circuits coupled to the soft-start linear voltage regulator circuit 200.
Furthermore, when the enabling signal EN is logic low, the soft-start linear regulator 200 is able to work normally for voltage regulating purposes. In this embodiment, as the sensed output current IR exceeds the predetermined current value Ilimit, the voltage level at node A is pushed up due to the current IR over the predetermined current value limit. The transistors M23, and M24 are turned off when the voltage level at node A is rising. At this time, since the transistor M25 is turned off, the node B is equivalent to a floating end. Therefore, the capacitive load CL has no effect on the voltage level at node A. Later, when the voltage level at node B is sufficiently high, the diode D1 is forward biased to connect node B and the input voltage Vin. Because the capacitive load CL has small capacitance, it will not affect the response speed of tuning the output current Iout. In short, at a start-up of the linear voltage regulator circuit 200, the capacitive load 206 can obtain the objective of slowly pushing up the output current Iout. This is called “soft-start”.
After reading the above disclosure, a person skilled in this art can easily understand that other circuit designs can be applied to implement the linear voltage regulator 202, the current sensing and comparing circuit 204, the capacitive load circuit 206, and the control circuit 208. That is, the circuit configuration shown in
Briefly summarized, the present disclosure provides a method and apparatus thereof for offering a “soft-start” mechanism. This is achieved by implementing an asymmetric capacitive load, i.e., the capacitive load circuit 206 shown in
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
