Patent Grant
7124351
1. Field of the Invention
The present invention relates to a circuit arranged to perform a cyclic redundancy check (CRC) on a received data stream. The circuit may additionally be used to perform other forms of coding on selected data.
2. Description of the Related Art
Error coding is often added to data when there is a possibility that the data may be corrupted or otherwise interfered with during transmission. Simple error coding may include simply adding a parity bit which indicates to the receiver that the data received is not identical with the data transmitted. However, such simple schemes do not protect for cases where more than a single bit is at fault. This can pose problems when, in reality, a burst error may corrupt several bits in a message.
Cyclic Redundancy Checking (CRC) is one form of error checking employed in a wide variety of data traffic systems. CRC uses a system of polynomial division to code a given string of data.
For example, assume the message to be transmitted is a multi-bit message, M(D).DN. This message is divided, using modulo-2 arithmetic, by a so-called generator polynomial, G(D). This division yields a division polynomial, Y(D), and a remainder polynomial R(D).
The long division process (normal, or modulo-2 for polynomials) yields Y(D) and R(D) as two separate outputs. In practice, only the remainder, R(D), is of interest, and Y(D) is discarded. The message, M(D) is then normally appended by N zero digits, or simply shifted left N positions, where N is the order of the generator polynomial, G(D). The data that is transmitted is therefore: M(D).DN+R(D).
The data may be transmitted over any one of a number of different interfaces. During the course of the transmission, an error E(D) may occur. The error may affect one or more bits of the message, which means that the receiver will receive M(D).DN+R(D) +E(D).
In order to verify the authenticity of the received data, the receiver divides the received data by the same generator polynomial, G(D).
The first term in the result of equation (2) yields Y(D) and R(D) as before. The term R(D)/G(D) yields just the remainder R(D). The term E(D)/G(D) yields e(D) and r(D) which represent the errors introduced by E(D).
The result of the division by the receiver, may therefore be written as:
(Y(D)+e(D))+R(D)+R(D)+r(D) (3)
Y(D) is not significant, as before, and may simply he discarded. The same is true for e(D), which is the result of E(D) divided by G(D). In practice, Y(D) and e(D) are combined and cannot be separated.
Accordingly, if no error E(D) has occurred during transmission, then r(D) is zero. If an error E(D) has occurred, then r(D) will have a non-zero value. In such a case, the receiver may choose to ignore the received data, flag it as erroneous and/or request a re-transmission.
As an example of this procedure, consider a binary stream of 192 bits: {1011 . . . 011}. Representing this as a polynomial already appended (or shifted) with eights ‘0’s to take into account the order of the generator, G(D):
1.D199+0.D198+1.D197+1.D196+ . . . +0.D10+1.D9+1.D8+0.D7+0.D6+0.D5+ . . . +0.D1+0.D+0.D0 (4)
The generator polynomial, G(D), of order N=8, in this case is:
D8+D7+D4+D3+D1+D0 (5)
In hardware, the modulo-2 division may be implemented as shown in
The data to be encoded is shifted into the coder 20 as shown in
After the sequence of zero bits has been loaded into the coder, the coder 20 contains the remainder R(D) of the coding division process.
The same coder circuit may be used for encoding and decoding. For encoding, the procedure is as described above. For decoding received data, the message data is first shifted into the coder 20, followed by the received remainder, R(D). If the coder 20 stores a zero value after the remainder has been shifted in, this indicates that the message and remainder sequence were received without error. A non-zero result indicates that either the message or remainder contains an error.
The CRC function can also be implemented in software. The following code demonstrates a prior art realization.
From the code above, it is evident that using a normal DSP (Digital Signal Processor) or MCU (Microprocessor Unit), a total of 3–5 instruction cycles would be required each time the LSB of the CRC register is checked for a ‘1’, performing the XOR and shift operations. The speed of this operation is further reduced when the length of the CRC register is higher than the data width of the processor or DSP accumulators, which are normally 8, 16, 24 or 32 bits. In such cases, two or more sets of XOR and shift are required.
According to a first aspect of the present invention, there is provided a method of calculating a Cyclic Redundancy Check (CRC) value for a multi-bit input data word, comprising a defined generator polynomial, including the steps of:
According to a second aspect of the present invention, there is provided an apparatus for calculating a Cyclic Redundancy Check (CRC) value for a multi-bit input data word, using a defined generator polynomial, including:
Embodiments of the invention may be used to perform CRC calculations on data quickly and efficiently as they may be implemented in an MCU such that the calculations are completed in a few clock cycles using specialized hardware which may be called by an appropriate instruction in software.
The basic apparatus and circuit may further be used in a variety of different coding schemes including Turbo coding, PN sequence generation and convolutional coding. Such coding schemes benefit from the more speedy execution achieved through use of the custom hardware provided.
For a better understanding of the present invention and to understand how the same may be brought into effect, the invention will now be described by way of example only, with reference to the appended drawings in which:
Hamming distance is defined as the number of occurrences of bit differences between two variables. For a modulo-2 case, the hamming distance is defined as the number of bit positions in which the corresponding bits of two binary words of the same length are different. This can be calculated by XORing the individual bits and counting the number of occurrences of differences. As an example, the hamming distance between 1011101 and 1001001 is two.
The result of the calculation is stored back into the first accumulator 58. Additionally, a carry flag 66 is provided. The carry flag stores the parity of the result, and is set to ‘0’ if even, or ‘1’ if odd.
The circuit of
The circuit 100 shown in
This process is repeated for all the message data bits, after which a number of ‘0’s equal to the length of the generator polynomial are shifted into the CRC register. After the message sequence and sequence of ‘0’s have been shifted in, the result contained in the CRC register is the remainder of the division.
The remainder is read from the CRC register in reverse bit order. The generator polynomial is also programmed in reverse bit order, and the MSB of the generator polynomial is not included.
Implementing a CRC function in software in the prior art requires several steps to perform the necessary shift, compare and XOR functions. Moreover, the task is repeated as many times as there are incoming data bits, making the process slow for large data words.
Embodiments of the present invention provide hardwired instructions which allow software calls to be made to specialized hardware which results in the process being performed significantly more speedily, thus freeing up the processor to perform other tasks. The specialized hardware is provided as part of an MCU or DSP, which is thus able to offer specialized commands for performing CRC calculations. Such commands may be implemented more speedily in such a specialized processor than in a general purpose processor as the specialized hardware can perform the required calculations in fewer instruction cycles.
For the CRC function, the hardware is implemented in such a way that cascading may be used to calculate the CRC for data words having a greater width than the accumulator of the MCU. For instance, if the MCU has a 16-bit accumulator, cascading may be used to allow the CRC to be calculated for a data word wider than 16-bits.
The hardware function is implemented as shown in
Circuit 50 extracts the LSB of the CRC register by calculating the parity of the auxiliary input. The auxiliary input is a copy of the CRC register that has been processed by software in the MCU by masking the CRC LSB position. The hardware is implemented in this way, rather than simply extracting the LSB from the CRC register, so that a CRC may be calculated that is not aligned to the word length of the CRC register, where the LSB of the CRC register may be in the middle of the word. This implementation also allows hardware to be easily used in other coding applications outlined below.
If the parity output from circuit 50 is determined to be odd, the new value of the CRC register becomes {Carry Flag, CRC register [m:1]}, and this is XORed with Generator [m:0]. If the parity output from circuit 50 is even, then the new value of CRC register is {Carry Flag, CRC register [m:1]}, and no XOR operation occurs.
For either odd or even parity, the new value of Carry Flag is simply CRC register[0].
A typical implementation of the circuit shown in
The hardwired instruction may be called from software using a suitably defined command, such as CRC(&A, &Tn, &C, #value), where &A represents the LSB of the CRC register, &Tn represents all bits of the CRC register, &C represents the carry flag and #value represents the generator polynomial.
If the Generator Polynomial, G(D), is D16+D12+D3+D1+D0, this is coded into #value as [1101 0000 0000 1000]. It is coded in reverse order from D0 to D15, the value of D16 is assumed by the hardware.
The following code describes how such a command may be used to calculate the CRC for a 16-bit input word, where the accumulator of the MCU is also 16-bit
Steps 2 to 4 are then repeated for all sixteen message data bits. After these steps, sixteen ‘0’s are shifted into the CRC register, and the value remaining in the CRC register after this operation is the required CRC.
In the case where the CRC is to be calculated for a word wider than the width of the accumulator, the hardwired CRC instruction is called twice. This scenario is illustrated in the code set out below for a 21-bit data word.
The CRC register is mapped to two registers
An arbitrary generator polynomial, G(D), may be defined as D21+D20+D19+D17+D12+D11+D7+D6+D3+D1+D0. This polynomial is coded onto #value1 and #value2 as:
As before, this is coded in reverse order from D0 to D20, with D21 being assumed by the hardware embodiment.
The code to realize the CRC calculation is:
As previously, the steps 3 to 6 are repeated for all bits of the input data word.
The above technique can be adapted for any length of input word, by mapping the word onto as many 16-bit registers as are required to hold the entire word. Of course, if the accumulator is wider than 16-bits, it will be capable of processing input words of greater width.
It is possible to define two versions of the CRC instruction to deal with different situations where data may need to bit-shifted to the left or the right. This may be useful in calculating CRC according to different standards which require different data structures. The only difference between their implementations is in the configuration of the bit-shifters which either shift to the left or to the right, and swap the MSB with the LSB and vice-versa. The remaining details are identical.
Each implementation may be called from software using a unique command, such as CRCR( ) for the right shifting version, and CRCL( ) for the left shifting version.
Aside from being used to calculate CRC, the basic circuit according to embodiments of the invention may be used in other applications including Pseudo Noise (PN) generators, Turbo coding and Convolutional Coding.
The generation of a PN sequence may be achieved by use of the hardwired CRC and WEIGHT instructions preciously defined. To generate a PN sequence, the following steps are performed:
The code below demonstrates how the hardwired instructions CRC( ) and WEIGHT( ) are used in the production of a PN sequence.
The following code is written in terms of the variables defined above:
Steps 6 to 13 are repeated for the required PN sequence length.
In examples of the invention where the PN register length (N) is greater than 16, two or more 16-bit registers are used to represent the PN register and two or more 16-bit registers are used represent the generator polynomial, in a similar way as described previously for calculating the CRC for a data word of greater width than the accumulator. In such a case the WEIGHT( ) and CRCR( ) instructions are called more than once as required.
The WEIGHT( ) and CRC( ) commands can be used to implement a Turbo encoder. The hardware implementation of such an encoder is shown in
The principle behind Turbo encoding is to receive an input bit 182, calculate a feedback bit 186, shift the contents of the Turbo register and then calculate the output bit 184. This process is repeated as new data input bits are shifted into the circuit.
The code below demonstrates how such a function may be realized using the CRC( ) and WEIGHT( ) commands described previously:
The following steps are executed:
Steps 5 to 14 are repeated for all the data bits to be encoded.
A convolutional encoder can also be implemented using the CRC( ) and WEIGHT( ) commands.
In the embodiment presented here, the WEIGHT( ) command is used to calculate the output bits and the CRC( ) command is used to shift the register bits right by one position.
The following steps are executed:
Steps 2 to 12 are repeated for all the data bits to be encoded.
Thus, it can be seen that by the provision of specialized hardwired instructions in an MCU, simple software routines may be developed which allow CRC calculations to be easily and quickly performed.
The basic hardware required to perform CRC calculations, which may be called in software, may further be used as a building block to perform the other forms of complex coding described above. Indeed, other coding schemes not herein described may be produced using the same techniques.
Shown in
The microprocessor unit 300 also includes a decoder 310, a CRC hardwired circuit 315, a Weight hardwired circuit 320, and an execution unit 325 interconnected by a bus 330. The decoder 310 receives an instruction from the instruction storage unit 305, determines whether the instruction is a standard instruction or one of the CRC and Weight instructions discussed above. If the received instruction is a standard instruction, the decoder 310 passes the instruction on the bus 330 to the execution unit 325 which executes the instruction normally. If the received instruction is the CRC instruction, the decoder 310 passes the instruction to the CRC hardwired circuit 315, which implements the CRC instruction in hardware as discussed above with respect to
All of the above U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety.
The present invention includes any novel feature or combination of features disclosed herein either explicitly or any generalization thereof irrespective of whether or not it relates to the claimed invention or mitigates any or all of the problems addressed.
| Number | Date | Country | Kind |
|---|---|---|---|
| 200207431-8 | Dec 2002 | SG | national |
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| Number | Date | Country | |
|---|---|---|---|
| 20040199849 A1 | Oct 2004 | US |
