Patent Application
20070134891
1. Field of the Invention
This invention relates in general to semiconductor devices and more particularly to devices implemented with semiconductor on insulator (SOI) technology.
2. Description of the Related Art
The surface orientation of a semiconductor material is descriptive of the lattice orientation of the material at the surface of the material. With some semiconductor circuits, it may be desirable to implement the P-channel transistors and N-channel transistors in semiconductor active regions having different surface orientations. For example, some N-channel transistors have a relatively higher electron mobility in silicon having a surface orientation (100) as opposed to the electron mobility of an N-channel transistor in silicon with a surface orientation (110). On the other hand, some P-channel transistors will have a higher hole mobility with their channels being implemented in silicon having a surface orientation (110) as opposed to silicon having a surface orientation (100).
Prior semiconductor devices have had semiconductor on insulator (SOI) configurations where the active semiconductor area for the N-channel transistors has a surface orientation of (100) and the active semiconductor area for the P-channel transistors has a surface orientation of (110). The different surface orientations are formed by removing areas of the active silicon layer having a first orientation (e.g. (100)) and removing the underlying oxide in those areas to expose a silicon substrate having a second surface orientation (e.g. (110)). Silicon is selectively expitaxially grown in the exposed areas such that the expitaxially grown silicon has the same surface orientation as the substrate. Oxygen is then implanted into the epitaxially grown silicon (and the wafer subsequently annealed) to form an insulator layer between the epitaxially grown silicon and the substrate. However, the selectively epitaxially grown silicon may include defects in the subsequently epitaxially grown silicon active layer e.g. at a boundary of the epitaxially grown silicon. Also, maintaining a clean surface on which to selectively grow the epitaxial silicon may be difficult due to different materials on the wafer and their pattern densities. Also, selective epitaxially grown silicon processes may lead to non epitaxial silicon growth on unwanted areas (e.g. on dielectrics). Furthermore, the insulator formation in the epitaxially grown silicon may generate defects in the epitaxially grown silicon active layer.
What is desirable is an improved process for forming a semiconductor device having an SOI configuration with active layers having different surface orientations.
The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.
The use of the same reference symbols in different drawings indicates identical items unless otherwise noted. The features shown in the Figures are not necessarily drawn to scale.
The following sets forth a detailed description of a mode for carrying out the invention. The description is intended to be illustrative of the invention and should not be taken to be limiting.
Wafer 101 has an SOI configuration with an active semiconductor layer (e.g. silicon, silicon germanium) 107 having a surface orientation (100). Layer 107 is on an insulator layer 105 (e.g. silicon oxide). Layer 105 is on substrate layer 103 (e.g. monocrystalline silicon). As shown in
In one embodiment, layer 107 is formed by implanting oxygen ions into substrate layer 103 followed by a subsequent anneal to form insulating layer 105. In this embodiment, layer 107 has the same substrate orientation as substrate layer 103. However, in other embodiments, layer 107 may be a portion of a donor wafer (not shown) having a surface orientation of (100) that is subsequently bonded to wafer 101 and then cleaved to leave layer 107. With this embodiment, substrate layer 103 may have the same or different surface orientation from semiconductor layer 107.
In one embodiment, layer 107 has a thickness of 700A, but may have other thickness (e.g. 20-1000 A) in other embodiments. However, other embodiments may be of other thicknesses. In one embodiment, insulator layer 105 has a thickness of 1400 A, but may be of other thicknesses in other embodiments. In some embodiments, wafer 101 does not include a semiconductor substrate layer.
In one embodiment, the patterning is performed by depositing a layer of photo resist (not shown) on layer 107, forming a pattern in the layer of photo resist by photolithographic techniques, remove portions of the photo resistor as per the pattern to expose portions of layer 107, and then etching the exposed portions of layer 107 (e.g. with CF4) to form the structures 201, 203, 205, and 207. However, layer 107 may be patterned utilizing other conventional techniques in other embodiments.
In one embodiment, layer 307 is formed by implanting oxygen ions in substrate layer 303 followed by a subsequent anneal to form layer 305. In such an embodiment, substrate layer 303 has a surface orientation (110). In other embodiments, layer 307 is formed by bonding a donor wafer having a surface orientation (110) to layer 305 and subsequently removing a portion of the donor wafer by cleaving. With this embodiment, the substrate layer 303 may have the same or different surface orientation from semiconductor layer 107.
In some embodiments, wafers 101 and 301 are brought together with align and bonding tools. In one embodiment, the wafers are placed in the position as shown in
In other embodiments, infrared optics visualizing images through the wafers may be utilized to align the wafers. In one embodiment, the wave length of the infrared waves are greater than 1.1 microns. The wafers with such techniques may be double polished for clarity of the infrared waves passing through the wafers. Such techniques may be referred to as through wafer alignment. However, other alignment techniques may be utilized.
In one embodiment, the surfaces of the wafers are cleaned and treated prior to alignment and contact to enhance bonding.
After the wafers 101 and 301 are in contact with each other, the resultant structure may be heated (e.g. at up to 400 degrees C. or more) to bond wafer 301 to wafer 101. Although in some embodiments, the wafers may be bonded at room temperature. In such embodiments, the oxides of insulating layers 105 and 305 form covalent bonds with oxide layers 409 and 209, respectively. However, in other embodiments, wafers 101 and 301 may be bonded together by other techniques.
Some embodiments may not include layer 209 or 409. In some embodiments, oxide layers may be formed on layers 107 and 307 prior to the patterning to form the openings in those layers. In such embodiments, such oxide may be formed by thermal growth or chemical vapor deposition of an oxide material.
After cleaving, the remaining portion of substrate layer 103 is removed. In one embodiment, the remaining portion is removed by a chemical mechanical polish (CMP) or by etching.
In the embodiment shown, these trench isolations may be formed at the locations where gaps exist between the oxides on the sidewalls of structures 201, 203, 205, 207, 401, 403, 405, and 407. The trench isolations remove the gaps and provide electrical isolation between the structures. In other embodiments, trench isolations (not shown) may be fabricated within structures 201, 203, 205, 207, 401, 403, 405, and 407 concurrently with the trench isolations shown in
In one embodiment, the trench isolations are formed by depositing an oxide layer and a nitride layer (not shown), and patterning and etching the resultant wafer to form openings, depositing a layer of trench isolation material (e.g. TEOS, oxide high density plasma oxide) over the resultant wafer, and then planarizing the resultant wafer using the silicon of structures 201, 203, 205, and 207 as an etch stop. Once the absence of nitride is detected, planarization may continue or an oxide etch is done for a predetermined time to remove the oxide layer 409 on structures 401, 403, 405, and 407. The planarization leaves the exposed surfaces of structures 201, 203, 205, 207, 401, 403, 405, and 407 coplanar. The trench isolation maybe made by other techniques and/or formed of other materials in other embodiments. For example, the trench isolation material may be formed by an initial oxidation process followed by a TEOS deposition process.
The resultant wafer as shown in
In one embodiment, the utilization of two different wafers for the formation of active material may provide a wafer having relatively high quality active material from structures of different surface orientations. In some of these embodiments, the problems with selective epitaxial silicon growth (e.g. unwanted non epitaxial growth on dielectrics and defect formation at insulating sidewalls) may be avoided in the formation of the active regions. Also, in embodiments where the active layer is formed from bonding a donor wafer to an insulator, problems associated with forming an insulator layer in the epitaxially grown silicon may be avoided.
In the embodiment shown, transistors 1101 and 1107 are N-channel devices having their channels formed in structures having a surface orientation (100) (structures 205, and 203) and transistors 1105 and 1109 are P-channel devices having their channels formed in structures having a surface orientation (110) (structures 403, and 405).
Although
The resultant wafer may be subject to subsequent processes to form subsequent structures. For example, gate spacers, contacts, interconnect layers with interconnects and interlayer dielectrics, passivation layers, and external connector structures (e.g. bond pads, bumps) (none shown) may be formed on the resultant wafer. The resultant wafer may be singulated (e.g. with a saw) into individual integrated circuits and package into integrated circuit packages.
In some embodiments, wafer 101 would not include insulating layer 105 wherein structures 201, 203, 205, 207 may be formed by etching substrate layer 103 to a predetermined depth.
In the embodiment shown, the oxide layer 1205 contacts insulating layer 1403. As shown in
After wafers 1201 and 1401 contact each other, the wafers are bonded together wherein in one embodiment, the oxide of layer 1205 forms covalent bonds with the oxide of layer 1403. However, the wafers may be bonded by other processes including those described above.
As shown in
In subsequent processes, P-channel transistors may be formed having channel regions in structures 1411, 1413, 1415, and 1417 (the structures having surface orientations of (110). N-channel transistor may be formed having channel regions in structures 1307, 1305, 1303, 1301 (the structures having surface orientations of (100)). See the text above regarding
In the embodiment of
After the stage shown in
In one embodiment, oxide layer 1919 is not formed. Also, in other embodiments, structures 1915, 1913, and 1911 may be separated from wafer 1901 by forming a damaged region in those structures (or in the layer from which the structures are formed prior to patterning), and then cleaving the structures at the damaged region.
Referring to
In the embodiment shown, openings 2021, 2023, and 2025 are sized and shaped to received structures 1915, 1913, and 1911 in an upside down position (the position of structure 1915 in
In one embodiment, the application fluid does not oxidize the silicon of semiconductor structures (e.g. 1913, 1911).
In other embodiments, the structures (e.g. 1913) to be received in the openings (e.g. 2023) of wafer 2001 may have different shapes and/or sizes. In some embodiments, the openings would have the same generally complimentary shape and size as the openings.
During the application process, the wafer may be rotated and ultrasound or other wafer movement mechanisms may be applied in some embodiments to ensure a higher filling of structures in the openings. During the application process, van der Waals forces provide a bonding force to bond the structures in the openings.
In subsequent processes, P-channel transistors may be formed having channel regions in structures 2009, 2011, 2013, and 2007 (the structures having surface orientations of (110). N-channel transistors may be formed having channel regions in structures 1915, 1913, and 1911 (the structures having surface orientations of (100)). See the text above regarding
In the embodiments shown and described, structures of one surface orientation (100) are formed on a donor wafer and then subsequently located on a handle wafer with structures of a second orientation (110) formed thereon. However, in other embodiments, structures having a surface orientation (110) may be formed on a donor wafer and then subsequently located on a handle wafer with structures having a surface orientation (100) formed thereon according to the embodiments described above. Also, structures having other surface orientations (e.g. (111)) may be utilized in the processes described above.
In one embodiment, a method of making a semiconductor device includes providing a first wafer having a semiconductor layer of a first surface orientation, selectively etching the semiconductor layer to form semiconductor structures of the first surface orientation and receptor openings, and providing semiconductor structures of a second surface orientation different from the first surface orientation. The method also includes locating the semiconductor structures of the second surface orientation into the receptor openings, forming transistors of a first type in the semiconductor structures of the first surface orientation, and forming transistors of a second type different from the first type in the semiconductor structures of the second surface orientation.
In another embodiment, a method of making a semiconductor device includes providing a wafer having a first plurality of semiconductor structures above an insulating layer. The semiconductor structures have a first surface orientation. The method includes applying a second plurality of semiconductor structures having a second surface orientation different from the first surface orientation between the first plurality of semiconductor structures and forming a substantially planar surface on the wafer. The substantially planar surface includes the first plurality of semiconductor structures, the second plurality of semiconductor structures, and isolation regions between the first plurality of semiconductor structures and the second plurality of semiconductor structures. The method includes forming transistors of a first type having their channel regions in the first plurality of semiconductor structures and forming transistors of a second type different from the first type having their channel regions in the second plurality of semiconductor structures.
Another embodiment includes a method of forming an integrated circuit having enhanced transistor mobility for two different types of transistors. The method includes providing a first semiconductor layer having a first plurality of semiconductor structures of a first surface orientation, providing a second semiconductor layer having a second plurality of semiconductor structures of a second surface orientation different from the first surface orientation, and applying the second semiconductor layer to the first semiconductor layer. The method also includes forming a planar surface comprised of the first plurality of semiconductor structures, the second plurality of semiconductor structures, and isolation regions, and using the planar surface to form transistors of two different channel types.
While particular embodiments of the present invention have been shown and described, it will be recognized to those skilled in the art that, based upon the teachings herein, further changes and modifications may be made without departing from this invention and its broader aspects, and thus, the appended claims are to encompass within their scope all such changes and modifications as are within the true spirit and scope of this invention.
