The present disclosure relates to a back electrode type (back contact type) (also called back junction type) solar cell and an electronic device including the solar cell.
Examples of a solar cell using a semiconductor substrate include a double-sided electrode type solar cell having electrodes formed on the both surfaces of a light reception surface and a back surface, and a back electrode type solar cell having electrodes formed only on the back surface. Since such a double-sided electrode type solar cell has electrodes formed on the light reception surface, the electrodes shield sunlight. On the other hand, such a back electrode type solar cell has no electrode formed on the light reception surface, and thus such a back electrode type solar cell has higher receiving efficiency of sunlight as compared with such a double-sided electrode type solar cell. Japanese Unexamined Patent Application, Publication No. 2009-200267 and Japanese Unexamined Patent Application, Publication No. 2010-092981 disclose back electrode type solar cells.
A first electrode layer 27X and a second electrode layer 37X for extracting the collected photocarriers to the outside are provided on the first conductivity type semiconductor layer 25X and the second conductivity type semiconductor layer 35X respectively. The first electrode layer 27X is formed into a so-called comb shape with a plurality of finger parts 27f corresponding to comb teeth and a bus bar part 27b corresponding to a supporting part of the comb teeth. The bus bar part 27b extends in the X direction along one peripheral portion of the semiconductor substrate 11. The finger parts 27f extend from the bus bar part 27b in the Y direction intersecting the X direction. Similarly, the second electrode layer 37X is formed into a so-called comb shape with a plurality of finger parts 37f corresponding to comb teeth and a bus bar part 37b corresponding to a supporting part of the comb teeth. The bus bar part 37b extends in the X direction along the other peripheral portion facing the one peripheral portion of the semiconductor substrate 11. The finger parts 37f extend from the bus bar part 37b in the Y direction. The finger parts 27f and the finger parts 37f are arranged alternately in the X direction as described, for example, in Japanese Unexamined Patent Application, Publication No. 2009-200267.
A wiring member is connected to each of the bus bar parts 27b and 37b. A plurality of solar cells 1X is connected in series or in parallel via these wiring members to be configured as a module. There has also been a technique of configuring a plurality of solar cells 1X as a module by connecting the finger parts 27f and the finger parts 37f using a wiring sheet instead of the bus bar parts 27b and 37b and the wiring members and by connecting the solar cells 1X in series or in parallel, as described, for example, in Japanese Unexamined Patent Application, Publication No. 2010-092981.
Products of high design quality are required as electronic devices such as wearable devices or wristwatches, and products having a variety of shapes are expected to be designed. Hence, a variety of shapes conforming to the shapes of electronic devices are also considered to be required for products of solar cells to be installed on such electronic devices. However, producing solar cells of various shapes for respective electronic devices, which is manufacture of a wide variety of products in small quantities, is not a realistic way of production.
In this regard, cutting a solar cell into an arbitrary shape on a customer side may be feasible. Regarding the conventional back electrode type solar cell 1X shown in
The present disclosure is intended to provide a solar cell that facilitates extraction of output even if the solar cell is cut into an arbitrary shape, and an electronic device including the solar cell.
A solar cell according to the present disclosure is a back electrode type solar cell including a semiconductor substrate, a first conductivity type semiconductor layer and a second conductivity type semiconductor layer arranged on a back surface of the semiconductor substrate, a first electrode layer corresponding to the first conductivity type semiconductor layer, and a second electrode layer corresponding to the second conductivity type semiconductor layer. The second electrode layer and a plurality of the first electrode layers form a sea-island structure in which the first electrode layers have island shapes and the second electrode layer has a sea shape. The solar cell includes a plate-like electrode arranged to face the back surface of the semiconductor substrate, connected to a plurality of the first electrode layers, and not connected to the second electrode layer.
Another solar cell according to the present disclosure is a back electrode type solar cell including a semiconductor substrate, a first conductivity type semiconductor layer and a second conductivity type semiconductor layer arranged on a back surface of the semiconductor substrate, a first electrode layer corresponding to the first conductivity type semiconductor layer, and a second electrode layer corresponding to the second conductivity type semiconductor layer. The second electrode layer and a plurality of the first electrode layers form a sea-island structure in which the first electrode layers have island shapes and the second electrode layer has a sea shape. The solar cell includes an insulating layer covering the second electrode layer while a plurality of the first electrode layers is exposed from the insulating layer.
An electronic device according to the present disclosure includes the solar cell described above.
According to the present disclosure, a solar cell that facilitates extraction of output even if the solar cell is cut into an arbitrary shape, and an electronic device including the solar cell can be provided.
Examples of an embodiment according to the present disclosure will be described below by referring to the accompanying drawings. It is noted that, in the drawings, the same or corresponding parts are denoted by the same reference numerals. For the sake of convenience, hatching, member reference numerals, etc. may be omitted. However, in such cases, other drawings shall be referred to.
The first conductivity type regions 7 and the second conductivity type region 8 form a sea-island structure. In the sea-island structure, a sea region is a physically continuous one region and electrically, a region having one electrical characteristic (positive or negative). On the other hand, the island regions are floating (isolated) regions in the sea region and has an electrical characteristic opposing the electrical characteristic of the sea region. The first conductivity type regions 7 correspond to the island regions and the second conductivity type region 8 corresponds to the sea region (in the following, the first conductivity type regions 7 will also be called the island regions and the second conductivity type region 8 will also be called the sea region). The island regions 7 each have a circular shape in a plan view of the major surface of the semiconductor substrate 11, for example. The shape of the island region 7 is not limited to the circular shape but it may also be a strip-like shape or a polygonal shape (rectangular shape, for example) (see a second modification described later, for example). The island regions 7 are arranged two-dimensionally at the major surface of the semiconductor substrate 11. More specifically, the island regions 7 are arranged at substantially equal intervals on points of intersection in an orthogonal grid (grid points). The sea region 8 occupies an entire region of the major surface of the semiconductor substrate 11 except the island regions 7 and a perimeter area of the semiconductor substrate 11. The sea region 8 may be arranged further at the perimeter area of the semiconductor substrate 11. This achieves increase in effective power generation area to allow increase in photoelectric conversion efficiency.
The solar cell 1 includes a passivation layer 13 and an anti-reflective layer 15 sequentially laminated on one major surface on a light reception side of the major surfaces of the semiconductor substrate 11. The solar cell 1 further includes a passivation layer 23, a first conductivity type semiconductor layer 25, and a first electrode layer 27 sequentially laminated in the island region 7 at a back surface corresponding to the other of the major surfaces of the semiconductor substrate 11 on the opposite side of the light reception surface. The solar cell 1 further includes a passivation layer 33, a second conductivity type semiconductor layer 35, and a second electrode layer 37 sequentially laminated in the sea region 8 at the back surface of the semiconductor substrate 11. The solar cell 1 further includes a plate-like electrode 40 laminated on the first electrode layer 27 in the island region 7 at the back surface of the semiconductor substrate 11. In
A conductive single crystal silicon substrate, for example, an n-type single crystal silicon substrate or a p-type single crystal silicon substrate is used as the semiconductor substrate 11. This achieves high photoelectric conversion efficiency. The semiconductor substrate 11 is preferably an n-type single crystal silicon substrate. In an n-type single crystalline silicon substrate, a carrier lifetime is longer. This is because, in a p-type single crystal silicon substrate, light induced degradation (LID) may occur, in which light irradiation affects boron (B), which is a p-type dopant, and thereby a carrier becomes a recombination center. On the other hand, in an n-type single crystal silicon substrate, LID is further suppressed from occurring.
The semiconductor substrate 11 may have a fine uneven structure of a pyramidal shape called a texture structure provided on the back surface. This increases efficiency of collecting light having passed through the semiconductor substrate 11 without being absorbed in the semiconductor substrate 11. The semiconductor substrate 11 may have a fine uneven structure of a pyramidal shape called a texture structure provided on the light reception surface. This reduces reflection of incident light on the light reception surface to improve optical confinement effect in the semiconductor substrate 11.
The thickness of the semiconductor substrate 11 is preferably between 50 and 200 μm inclusive, more preferably between 60 and 180 μm inclusive, and still more preferably between 70 and 180 μm inclusive. Forming the semiconductor substrate 11 into such a small thickness achieves increase in open-circuit voltage and reduction in costs of material of the solar cell 1. It is noted that, as the semiconductor substrate 11, a conductive polycrystalline silicon substrate may be used, for example, an n-type polycrystalline silicon substrate or a p-type polycrystalline silicon substrate. In this case, a solar cell is manufactured at lower costs.
The anti-reflective layer 15 is formed on the light reception surface of the semiconductor substrate 11 via the passivation layer 13. The passivation layer 13 is formed as an intrinsic silicon-based layer. The passivation layer 13 functions to terminate surface defect of the semiconductor substrate 11 to suppress carrier recombination. A translucent film having a refractive index of approximately 1.5 to 2.3 inclusive is preferably used as the anti-reflective layer 15. As a material of the anti-reflective layer 15, SiO, SiN, or SiON is preferable, for example. While a method of forming the anti-reflective layer 15 is not particularly limited, a CVD method achieving precise control of a film thickness is preferably used. The film formation by the CVD method achieves control of film quality by controlling material gas or conditions for the film formation.
In the present embodiment, the light reception surface has no electrode formed (back electrode type), and such a solar cell has high receiving efficiency of sunlight, and thus the photoelectric conversion efficiency thereof is high.
The first conductivity type semiconductor layer 25 is formed in the island region 7 at the back surface of the semiconductor substrate 11 via the passivation layer 23. The second conductivity type semiconductor layer 35 is formed in the sea region 8 at the back surface of the semiconductor substrate 11 via the passivation layer 33. In this way, the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35 form a sea-island structure in which the first conductivity type semiconductor layer 25 corresponds to an island-shape semiconductor layer and the second conductivity type semiconductor layer 35 corresponds to a sea-shape semiconductor layer.
The first conductivity type semiconductor layer 25 is formed as a first conductivity type silicon-based layer, for example, a p-type silicon-based layer. The second conductivity type semiconductor layer 35 is formed as a silicon-based layer of a second conductivity type different from the first conductivity type, for example, an n-type silicon-based layer. The first conductivity type semiconductor layer 25 may be an n-type silicon-based layer, and the second conductivity type semiconductor layer 35 may be a p-type silicon-based layer. Each of the p-type silicon-based layer and the n-type silicon-based layer is formed of an amorphous silicon layer or a microcrystal silicon layer containing amorphous silicon and crystal silicon. Boron (B) is preferably used as dopant impurities in the p-type silicon-based layer. Phosphorus (P) is preferably used as dopant impurities in the n-type silicon-based layer.
While a method of forming the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35 is not particularly limited, a CVD method is preferably used. As an example, SiH4 gas is preferably used as a material gas. As an example, hydrogen-diluted B2H6 or PH3 is preferably used as a dopant addition gas. A very small quantity of impurities of, for example, oxygen or carbon may be added in order to improve light transmittance. In this case, gas, for example, CO2 or CH4 is introduced during film formation by the CVD method. As a different method of forming the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35, a thermal diffusion doping method or a laser doping method is used.
In the back electrode type solar cell, light is received on the light reception surface and generated carriers are collected at the back surface. For this reason, the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35 are formed in the same plane. A method of forming (patterning) the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35 into predetermined shapes in the same plane is not particularly limited. A CVD method using a mask may be employed. Alternatively, an etching method using a resist, an etching solution, or etching paste may be employed, for example.
Preferably, the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35 are not joined. Thus, an insulating layer (not shown) may be provided between these layers. If an insulating layer is provided at a boundary between a p-type silicon-based thin film and an n-type silicon-based thin film, and if the insulating layer is made of silicon oxide, for example, and is formed by a CVD method, a film forming step can be simplified to encourage reduction in process costs and improvement of yield.
The passivation layers 23 and 33 are each formed as an intrinsic silicon-based layer. The passivation layers 23 and 33 function to terminate surface defect of the semiconductor substrate 11 to suppress carrier recombination. This extends carrier lifetime to improve output of the solar cell.
The first electrode layer 27 is formed on the first conductivity type semiconductor layer 25. The second electrode layer 37 is formed on the second conductivity type semiconductor layer 35. In this way, the first electrode layer 27 and the second electrode layer 37 form a sea-island structure in which the first electrode layer 27 corresponds to an island-shape electrode layer and the second electrode layer 37 corresponds to a sea-shape electrode layer. The first electrode layer 27 and the second electrode layer 37 are separated.
The first electrode layer 27 and the second electrode layer 37 are formed as transparent conductive layers made of a transparent conductive material. As the transparent conductive material, transparent conductive metal oxide is used, for example, indium oxide, tin oxide, zinc oxide, titanium oxide, and complex oxides thereof. An indium-based complex oxide mainly containing indium oxide is preferably used out of them. An oxide of indium is particularly preferably used, from the viewpoint of high conductivity and transparency. Furthermore, it is preferable to add dopant to an oxide of indium in order to ensure reliability or higher conductivity. Examples of the dopant include Sn, W, Zn, Ti, Ce, Zr, Mo, Al, Ga, Ge, As, Si and S. A method used for forming these transparent electrode layers is a physical vapor deposition method such as a sputtering method or a chemical vapor deposition method (CVD method, for example) using reaction of an organometallic compound with oxygen or water, for example.
The first electrode layer 27 and the second electrode layer 37 are not limited to the transparent electrode layers but they may include metal electrode layers laminated on the transparent electrode layers. Namely, the first electrode layer 27 and the second electrode layer 37 may be a laminated first electrode layer and a laminated second electrode layer each composed of the laminated transparent electrode layer and metal electrode layer. One of the first electrode layer and the second electrode layer may be a laminated electrode layer and the other may be a single-layer transparent electrode layer. Alternatively, both the first electrode layer 27 and the second electrode layer 37 may be single-layer transparent electrode layers or single-layer metal electrode layers. The metal electrode layers are made of a metal material. Examples of the metal material include Cu, Ag, Al, and an alloy of these materials. For example, a printing method such as screen printing using Ag paste or a plating method such as electrolytic plating using Cu is employed as a method of forming the metal electrode layers.
Preferably, the width of the first electrode layer 27 is smaller than that of the first conductivity type semiconductor layer 25, and the width of the second electrode layer 37 is smaller than that of the second conductivity type semiconductor layer 35. The width of the sea-shape second electrode layer 37 is the width of a portion in a predetermined direction caught between two island-shape first electrode layers 27 adjacent to each other in the predetermined direction (for example, the width of a portion in the X direction caught between two island-shape first electrode layers 27 adjacent to each other in the X direction, the width of a portion in the Y direction caught between two island-shape first electrode layers 27 adjacent to each other in the Y direction, or the width of a portion in a direction of 45 degrees tilted 45 degrees from the X direction and the Y direction caught between two island-shape first electrode layers 27 adjacent to each other in the direction of 45 degrees), or the width of a portion between the island-shape first electrode layer 27 and a perimeter of the semiconductor substrate 11. Likewise, the width of the sea-shape second conductivity type semiconductor layer 35 is the width of a portion in a predetermined direction caught between two island-shape first conductivity type semiconductor layers 25 adjacent to each other in the predetermined direction (for example, the width of a portion in the X direction caught between two island-shape first conductivity type semiconductor layers 25 adjacent to each other in the X direction, the width of a portion in the Y direction caught between two island-shape first conductivity type semiconductor layers 25 adjacent to each other in the Y direction, or the width of a portion in a direction of 45 degrees tilted 45 degrees from the X direction and the Y direction caught between two island-shape first conductivity type semiconductor layers 25 adjacent to each other in the direction of 45 degrees), or the width of a portion between the island-shape first conductivity type semiconductor layer 25 and a perimeter of the semiconductor substrate 11.
To efficiently extract photocarriers collected at the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35, the first electrode layer 27 and the second electrode layer 37 preferably have largest possible widths. Thus, the width of the first electrode layer 27 is preferably greater than 0.5 times, more preferably, greater than 0.7 times the width of the first conductivity type semiconductor layer 25. Likewise, the width of the second electrode layer 37 is preferably greater than 0.5 times, more preferably, greater than 0.7 times the width of the second conductivity type semiconductor layer 35. If an insulating layer or another layer is provided at a boundary between the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35 so the first electrode layer 27 and the second electrode layer 37 are separated from each other, the width of the first electrode layer 27 may be greater than that of the first conductivity type semiconductor layer 25, and the width of the second electrode layer 37 may be greater than that of the second conductivity type semiconductor layer 35.
On the other hand, to efficiently collect photocarriers in the semiconductor substrate 11 using the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35, the respective widths of the first electrode layer 27 and the second electrode layer 37 preferably have some certain degrees of smallness. A distance by which minority carriers can move within the semiconductor substrate 11 without being recombined with majority carriers is determined in a manner that depends on the resistivity of the substrate, etc. This distance is equal to or less than about 3 mm in a silicon substrate generally used in a solar cell. If the conductivity type of the semiconductor substrate 11 is an n-type, the island-shape first conductivity type semiconductor layer 25 is a p-type semiconductor layer, and the sea-shape second conductivity type semiconductor layer 35 is an n-type semiconductor layer, the island-shape first conductivity type semiconductor layer 25 and first electrode layer 27 function to collect holes, and the sea-shape second conductivity type semiconductor layer 35 and second electrode layer 37 function to collect electrons. Referring to
If the conductivity type of the semiconductor substrate 11 is an n-type, the island-shape first conductivity type semiconductor layer 25 is an n-type semiconductor layer, and the sea-shape second conductivity type semiconductor layer 35 is a p-type semiconductor layer, the island-shape first conductivity type semiconductor layer 25 and first electrode layer 27 function to collect electrons, and the sea-shape second conductivity type semiconductor layer 35 and second electrode layer 37 function to collect holes. Referring to
In such a case where the island-shape first conductivity type semiconductor layer 25 is an n-type semiconductor layer, even if connection failure occurs between the plate-like electrode 40 and the island-shape first electrode layer 27 to disable collection of electrons at this isolated island-shape first electrode layer 27, electrons capable of moving a long distance can reach a different adjacent island-shape first electrode layer 27. This produces an advantage in terms of suppressing loss due to the connection failure. Providing the same conductivity type of the semiconductor substrate 11 and the island-shape first conductivity type semiconductor layer 25 in this way allows collection of majority carriers at the island-shape first electrode layer 27. Thus, even on the occurrence of the connection failure between the plate-like electrode 40 and the island-shape first electrode layer 27, majority carriers are still collected at a different island-shape first electrode layer 27 to suppress loss due to the connection failure. The foregoing description proceeds on the assumption that the conductivity type of the semiconductor substrate 11 is an n-type, for example. If the conductivity type of the semiconductor substrate 11 is a p-type, the width of an electrode layer to function to collect holes as majority carriers is also preferably equal to or less than 6 mm, more preferably, equal to or less than 2 mm, particularly preferably, equal to or less than 1 mm.
As shown in
Increasing the height of the second electrode layer 37 increases a cross-sectional area for a current to flow in a plane direction, thereby achieving reduction in series resistance. However, increasing the height of an electrode layer increases stress at an interface between a semiconductor layer and the electrode layer, and this may cause detachment of an electrode. Moreover, in a back electrode type solar cell in which an electrode is provided only on one surface, increasing the height of an electrode layer causes a stress unbalance between the front and back of a substrate. In this case, deformation such as deflection of the solar cell is likely to occur, and this may cause breakage of the solar cell. If the solar cell is deformed by stress at an electrode interface, trouble such as misalignment or short-circuit may occur during configuration of the solar cell as a module. For this reason, the height H2 of the second electrode layer 37 is preferably equal to or less than 100 μm, more preferably, equal to or less than 60 μm, still more preferably, equal to or less than 30 μm. The height of an electrode is a distance from a major surface of a substrate to the top of the electrode. In the presence of a region of the substrate where a thickness is reduced partially by etching for forming a semiconductor layer, for example, a reference plane parallel to a major surface of the substrate may be defined, and a distance from the reference plane to the top of the electrode may be defined as the height of the electrode.
The plate-like electrode 40 is provided to face the semiconductor substrate 11 and connected to a plurality of the island-shape first electrode layers 27. The plate-like electrode 40 is made of a metal material. Examples of the metal material include Cu, Ag, Al, and an alloy of these materials. For example, a printing method such as screen printing using Ag paste or a plating method such as electrolytic plating using Cu is employed as a method of forming the plate-like electrode 40. Alternatively, the plate-like electrode 40 may be formed by laminating metal sheets such as copper foil or wiring sheets prepared in advance. In this case, the plate-like electrode 40 and a plurality of the island-shape first electrode layers 27 may be connected with an adhesive, for example. If screen printing using Ag paste is employed for forming the plate-like electrode 40, for example, the plate-like electrode 40 is formed into an electrode containing Ag particles. The plate-like electrode 40 may be a lattice-like or mesh-like flat plate.
The following describes cutting of the solar cell 1 described above into an arbitrary shape. The solar cell 1 may be cut by a customer or by a manufacturer before shipment.
In the solar cell 1 according to the present embodiment, the second electrode layer 37 is formed into a sea shape. Thus, in the cut solar cell 1, separation of the second electrode layer 37 is prevented. This makes it possible to extract carriers collected at the second electrode layer 37, namely, extract output of the solar cell 1. Some of the island-shape first conductivity type semiconductor layers 25 and the sea-shape second conductivity type semiconductor layer 35 are exposed at an edge of a perimeter of the cut solar cell 1. Further, some of the island-shape first electrode layers 27 and the sea-shape second electrode layer 37 face the edge of the perimeter of the cut solar cell 1.
While a method of cutting the solar cell 1 into an arbitrary shape is not particularly limited, laser dicing or blade dicing may be employed, for example. Laser dicing is particularly preferable as it allows cutting out of a complicated shape or a curved plane. If a laser is used for cutting, a laser mark is formed on the edge of the perimeter (cutting plane) of the solar cell 1 after the cutting.
A method of forming an extraction electrode will be described next. The extraction electrode may be formed by a customer or by a manufacturer before shipment.
Generally, in a back electrode type solar cell used in a high-illuminance environment (for generation of high power), an electrode layer includes a metal electrode layer in addition to a transparent electrode layer in order to reduce electrical resistance loss occurring during electricity transport in a plane direction of the solar cell. By contrast, in a back electrode type solar cell mainly used in a low-illuminance environment (for generation of low power) for an electronic device such as a wearable device or a wristwatch, electrical resistance in a plane direction is not required to be reduced to a level comparable to a level required in the back electrode type solar cell used in a high-illuminance environment. For this reason, in the solar cell 1 according to the present embodiment, the sea-shape second electrode layer 37 is formed only of the transparent electrode layer while the metal electrode, namely, the extraction electrode 45 is formed into a small size on a part of the transparent electrode layer. If there arises a need to reduce the electrical resistance of the sea-shape second electrode layer 37 even in a low-illuminance environment, the second electrode layer 37 may include a metal electrode layer in addition to the transparent electrode layer.
In an ordinary solar cell panel, transporting electricity in a plane direction of a solar cell using a wiring member such as a tab wire or a smart wire is indispensable for suppressing electrical resistance loss. On the other hand, the back electrode type solar cell according to the present embodiment is preferably employed in an electronic device mainly used in a low-illuminance environment, particularly for wearable purposes (for wristwatch, smart watch, or sensor). In this case, the intensity of light generally emitted is low and electrical resistance loss is not serious compared to that in the solar cell panel. Thus, electricity in the plane direction within the plane of the solar cell is mainly transported using the plate-like electrode 40 and the second electrode layer 37, and this makes a difference from the ordinary solar cell panel. Transporting electricity in the plane direction mainly using the plate-like electrode 40 and the second electrode layer 37 prevents a wiring member from becoming a limitation in cutting out the solar cell into an arbitrary shape, and this further acts advantageously in using the solar cell according to the present embodiment for low-illuminance purposes. In the present embodiment, the plate-like electrode 40 is used for electrical transport through the island-shape first electrode layer 27, and the plate-like electrode is not used for electrical transport through the sea-shape second electrode layer 37. Specifically, in the present embodiment, the plate-like electrode only has one polarity.
In consideration of cutting a solar cell into an arbitrary shape, the island-shape first electrode layer 27 desirably has a size of a certain degree of smallness for reducing loss. If the size of the island-shape first electrode layer 27 is small, the region of the sea-shape second electrode layer 37 not covered with the plate-like electrode 40 is reduced. Hence, in some cases, the second extraction electrode 45 is hard to form only on the sea-shape second electrode layer 37 in such a manner as to be absent from the first electrode layer 27 and the plate-like electrode 40. In this case, as shown in
The second extraction electrode 45 may be formed before cutting or after the cutting. The second extraction electrode 45 may be formed before formation of the plate-like electrode 40 or after the formation of the plate-like electrode 40. Described next is an example of forming the second extraction electrode 45 before the cutting and before the formation of the plate-like electrode 40 by referring to
Next, as shown in
If the second extraction electrode 45 is to be formed on a customer side, the second electrode layer 37 located under the insulating layer 50 is required to be exposed partially and connected to the second extraction electrode 45. A method of connecting the second electrode layer 37 and the second extraction electrode 45 after formation of the insulating layer 50 is not particularly limited. If soldering is employed for forming the second extraction electrode 45, for example, the insulating layer 50 made of resin, for example, may be cut through by heat for establishing the connection. If a photoresist is used as the insulating layer 50, an opening may be formed in a part of the insulating layer 50 through exposure and development to expose the second electrode layer 37, and then the second electrode layer 37 and the second extraction electrode 45 may be connected.
In particular, irradiating a pn junction with a laser beam causes serious output reduction of a solar cell. Hence, a semiconductor layer forming the pn junction is preferably the island-shape first conductivity type semiconductor layer 25 and not connected to the plate-like electrode 40. Namely, unlike the island-shape first conductivity type semiconductor layer 25, the semiconductor substrate 11 preferably has the second conductivity type same as that of the sea-shape second conductivity type semiconductor layer 35. Irradiating the second conductivity type semiconductor layer 35 not forming a pn junction with a laser beam causes output reduction of a solar cell but this reduction is slight.
In particular, minimizing the size of the island region 7, namely, minimizing the sizes of the island-shape first conductivity type semiconductor layer 25 and first electrode layer 27 reduces the area of the island-shape first conductivity type semiconductor layer 25 to be cut. Thus, output reduction of the solar cell can be suppressed to a greater extent. As a method of separating the plate-like electrode 40 and the cut island-shape first conductivity type semiconductor layer 25, after the solar cell is cut on a customer side or a manufacturer side, the plate-like electrode 40 may be formed in such a manner as to be absent from the first electrode layer 27 (namely, the first electrode layer 27 facing the edge of the perimeter of the solar cell) corresponding to the cut island-shape first conductivity type semiconductor layer 25. Alternatively, before the solar cell is cut on the customer side or the manufacturer side, the plate-like electrode 40 may be formed in such a manner as to be absent from the first electrode layer 27 (namely, the first electrode layer 27 facing the edge of the perimeter of the solar cell) corresponding to the island-shape first conductivity type semiconductor layer 25 to be cut in a cutting step.
For actual use of the solar cell 1 according to the present embodiment, the solar cell 1 is preferably configured as a module. The solar cell is configured as a module by an appropriate method. For example, a wire or a contact pin may be connected to the extraction electrodes 43 and 45 functioning as an anode and a cathode to allow extraction of electricity. A back electrode type solar cell is configured as a module by being sealed with a sealing agent and a glass plate. The solar cell configured as a module in this way becomes installable on an electronic device for wearable purposes (for wristwatch, smart watch, or sensor).
While the embodiments according to the present disclosure have been described so far, the present disclosure is not limited to the above-described embodiments, and various modifications are available. In the present embodiment, the heterojunction type solar cell has been described. In an example, the feature of the present disclosure may be applied to various types of solar cells such as a homojunction type solar cell, not limited to such a heterojunction type solar cell.
The back electrode type solar cell 1 shown as an example in the present embodiment described above includes the passivation layer 23, the first conductivity type semiconductor layer 25, and the first electrode layer 27 sequentially laminated in the island region (first conductivity type region) 7 at the back surface of the semiconductor substrate 11, and the passivation layer 33, the second conductivity type semiconductor layer 35, and the second electrode layer 37 sequentially laminated in the sea region (second conductivity type region) 8 at the back surface of the semiconductor substrate 11 except the island region 7. However, the feature of the present disclosure is not limited to this solar cell 1 but is further applicable to a back electrode type solar cell in which at least a part of a first conductivity type semiconductor layer and at least a part of a second conductivity type semiconductor layer overlap each other. This solar cell may be realized by forming a first electrode layer corresponding to the first conductivity type semiconductor layer into an island shape like the foregoing first electrode layer 27, forming a second electrode layer corresponding to the second conductivity type semiconductor layer into a sea shape like the foregoing second electrode layer 37, and forming a sea-island structure using the first electrode layer and the second electrode layer.
Number | Date | Country | Kind |
---|---|---|---|
2017-232916 | Dec 2017 | JP | national |
This application claims benefit of priority to International Patent Application No. PCT/JP2018/034360, filed Sep. 18, 2018, and to Japanese Patent Application No. 2017-232916, filed Dec. 4, 2017, the entire contents of each are incorporated herein by reference.
Number | Date | Country | |
---|---|---|---|
Parent | PCT/JP2018/034360 | Sep 2018 | US |
Child | 16808191 | US |