Patent Application
20070137699
This invention relates generally to solar cells and, more particularly, to a method for fabricating a solar cell.
Thermal oxides having a thickness greater than about 100 nm are commonly used for the production of high-efficiency silicon (Si) solar cells from monocrystalline and multicrystalline silicon. These conventional solar cells produce relatively high power conversion efficiencies due to the good surface passivation achieved by the reduction in density of interface states. However, there are distinct disadvantages with the process for fabricating these solar cells. First, the process is performed at high temperatures for a long period of time, thereby increasing a thermal budget required to fabricate these solar cells. Second, oxidation in a tube furnace takes place on each of a front side and a backside of the wafer, and good anti-reflection properties require the removal of oxide from the front side.
To overcome the difficulties associated with using a silicon dioxide (SiO2) passivation layer, a silicon nitride (SiNx) layer can be deposited on the SiO2 layer to improve the optical and electrical properties. However, SiNx layers are characterized by a loss in short-circuit current density (Jsc) due to the short circuiting of the inversion layers induced by the fixed charges in SiNx at rear contact points. As a result, a floating junction is shunted by the rear contact points and the passivation is reduced under operating conditions. Therefore, a back surface passivated (BSP) structure is needed that overcomes the disadvantages associated with the use of individual SiO2 and SiNx materials.
Conventional structures for solar cells include an aluminum back surface field (Al BSF) formed by firing a screen-printed Al paste. Although this process is suited in terms of industrial feasibility, processing difficulties occur when an efficiency of the solar cell is higher than 18% and/or a wafer thickness is below 150 μm. This is due to the relatively poor electrical and optical properties of an Al BSF, which will reduce the cell performance on thin substrates. Further, the wafer bows during the Al firing process and, thus, produces a nonuniform BSF that results in unacceptably high back surface recombination velocity values.
In one aspect, the present invention provides a method for fabricating a solar cell. The method includes positioning a silicon substrate having a front surface and an opposing back surface in a plasma reaction chamber. A high-efficiency emitter structure is formed on the first surface of the silicon substrate. A back surface passivated structure is formed on the second surface of the silicon substrate.
In another aspect, the present invention provides a method for fabricating a solar cell using plasma deposition processes. The method includes positioning a silicon substrate in a plasma reaction chamber. The silicon substrate is heated to a temperature of about 120° C. to about 240° C. A plasma discharge is generated within the plasma reaction chamber to dissociate a silicon compound gas in the plasma discharge. A high-efficiency emitter structure is formed on the first surface of the silicon substrate. A back surface passivated structure is formed on the second surface of the silicon substrate. The back surface passivated structure includes a stack of dielectric layers having an inner layer including SiO2 with a thickness not greater than about 200 Å deposited on the second surface of the silicon substrate and an outer layer including SiNx having a thickness not greater than about 200 Å deposited on the inner layer.
In another aspect, the present invention provides a solar cell. The solar cell includes a silicon substrate having a first surface and an opposing second surface. A high-efficiency emitter structure is formed on the first surface. A back surface passivated structure is formed on the second surface.
The present invention provides a method for fabricating a silicon solar cell including a dielectric stack layer structure including SiO2/SiNx to produce a back surface passivated (BSP) structure. A front side emitter may be formed by a compositionally graded a-Si:H, such as described in U.S. patent application Ser. No. 11/263,159 entitled Compositionally-Graded Photovoltaic Device and Fabrication Method, filed on Oct. 31, 2005, the disclosure of which is incorporated herein by reference, or any suitable high-efficiency emitter structure that is expected to provide high power conversion efficiency. In order to produce a more efficient crystalline silicon solar cell using aspects of the present invention, the surface recombination velocity may be decreased and the internal optical reflection at the rear surface may be increased. Such goals are realized by optimizing a rear surface to increase optical qualities, such as internal reflection, and/or electrical qualities, such as surface passivation. Silicon solar cells including a dielectric stack layer structure and a high-efficiency front surface emitter structure increase the benefits associated with the dielectric passivation layers, which leads to an increased power conversion efficiency for the solar cell.
In one embodiment, a method for fabricating a solar cell 10 is provided. Solar cell 10 includes a suitable silicon substrate 12, such as a monocrystalline semiconductor substrate or a multicrystalline semiconductor substrate. As shown in
Silicon substrate 12 is positioned within a plasma reaction chamber, such as a Plasma Enhanced Chemical Vapor Deposition (PECVD) apparatus (not shown). The plasma reaction chamber is evacuated by removing atmospheric gases though a vacuum pump. In this embodiment, H2 is introduced into the chamber at a flow rate of about 50 sccm to about 500 sccm. A constant processing pressure of about 200 mTorr to about 800 mTorr is maintained within the plasma reaction chamber, such as by using a throttle valve. An alternating frequency input power having a power density of about 3 mW/cm2 to about 50 mW/cm2 is used to ignite and maintain the plasma. The applied input power has a frequency of about 100 kHz to about 2.45 GHz. Within the plasma reaction chamber, silicon substrate 12 is heated to a temperature of about 120° C. to about 240° C.
A compositionally graded layer structure is formed by introducing SiH4 into the plasma process chamber at the end of an optional hydrogen plasma preparation step. The SiH4 is introduced into the plasma process chamber at a flow rate of about 10 sccm to about 60 sccm to initiate a deposition of the compositionally graded layer structure. Because no dopant precursors are included in the plasma, initially the composition of the compositionally graded layer structure is intrinsic (undoped), thus serving to passivate front surface 14 of silicon substrate 12. As the deposition progresses, a dopant precursor is subsequently added to the plasma mixture. Suitable dopant precursors include, without limitation, B2H6 and PH3. The dopant precursors may be in pure form or diluted with a carrier such as argon, hydrogen or helium. The flow rate of the dopant precursor is increased over the course of the deposition process to form a doping concentration gradient. The dopant concentration is substantially zero at the interface with substrate 14, regardless of the particular dopant profile. Thus, an intrinsic region 22 is present at the interface, serving to minimize recombination of the charge carriers. At the conclusion of the deposition process, the concentration of dopant precursor in the plasma is such that substantially doped amorphous semiconductor properties are achieved. Thus, an opposing upper region 24 of graded layer 20 is substantially conductive. The specific dopant concentration in upper region 24 will depend on the particular requirements for the semiconductor device. The thickness of compositionally graded layer 20 will also depend on various factors, such as the type of dopant employed; the conductivity type of the substrate; the grading profile; the dopant concentration in upper region 24; and the optical band gap of layer 20. In one embodiment, a thickness of graded layer 20 is less than or equal to about 250 Å. In a particular embodiment, graded layer 20 has a thickness of about 30 Å to about 180 Å.
A back surface passivated structure 30 is formed on back surface 16 of silicon substrate 12. In one embodiment, BSP structure 30 includes a stack of dielectric layers, as shown in
The dielectric stack including silicon dioxide inner layer 32 and silicon nitride outer layer 34 provides an effective back surface passivated structure for solar cell 10. The dielectric stack meets the demands of a suitable rear surface scheme including, without limitation, a high internal reflectance for good light trapping and a very good rear surface passivation under operating conditions to achieve high open-circuit voltage (Voc) and Jsc values. Further, in one embodiment, internal reflectance is maximized to enable good light trapping characteristics as well as a textured front surface. In conventional solar cells using evaporated aluminum, the reflectance varies between about 50% and about 80%. Thus, the low reflectivity of the evaporated Al does not provide the required light trapping. Conversely, the dielectric stack of this embodiment, including silicon dioxide inner layer 32 and silicon nitride outer layer 34, is expected to provide a high reflectance, which allows for good light trapping in solar cell 10. In addition to the optical properties described above, BSP structure 30 facilitates achieving low recombination velocity values due to the passivation characteristics of the dielectric stack.
As shown in
As shown in
Aspects of the present invention provide a method for fabricating a solar cell using a PECVD apparatus with depositions at low temperature. Low temperature deposition facilitates the reduction of the thermal budget associated with conventional high temperature diffused cells. Additionally, long-term performance degradation is decreased for low temperature solar cells, thus, providing stable output over longer time periods than conventional solar cells. The SiO2/SiNxBSP structure facilitates achieving an improved surface passivation to overcome the disadvantages of high recombination velocity obtained in conventional devices using aluminum. Further, the BSP structure facilitates processing large area solar cell wafers, thereby increasing the power output.
While the invention has been described in terms of various specific embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the claims.
