Patent Application
20190157489
The present disclosure relates to a solar cell and a method for producing the solar cell.
There has been conventionally known a solar cell in which amorphous silicon layers are formed on both surfaces of a crystalline silicon wafer. For example, Japanese Unexamined Patent Application Publication No. 2006-237452 A discloses a solar cell in which an n-type amorphous silicon layer is formed on a light receiving surface of an n-type crystalline silicon wafer, and a p-type amorphous silicon layer is formed on a rear surface of the wafer. The solar cell disclosed in Japanese Unexamined Patent Application Publication No. 2006-237452 A includes a transparent conductive layer and a collector electrode formed on each of the amorphous silicon layers.
Incidentally, it is an important problem to enhance an open circuit voltage (VOC) in a solar cell. Further, in a solar cell, reduction in a breakdown voltage is required.
A solar cell that is one aspect of the present disclosure includes, in an entire wafer surface and a vicinity of the entire wafer surface, an n-type crystalline silicon wafer having an n+ layer having a higher concentration of an n-type dopant than other regions, a silicon oxide layer formed on a light receiving surface of the n-type crystalline silicon wafer, an n-type crystalline silicon layer formed on the silicon oxide layer, and a p-type amorphous silicon layer formed on a rear surface side of the n-type crystalline silicon wafer, wherein the silicon oxide layer contains an n-type dopant, and a concentration of the n-type dopant in the silicon oxide layer is lower than concentrations of n-type dopants in the n+ layer and the n-type crystalline silicon layer.
A method for producing a solar cell that is one aspect of the present disclosure includes a first step of submerging an n-type crystalline silicon wafer in an acid aqueous solution containing an n-type dopant, and forming a high concentration n-type dopant-containing silicon oxide layer on an entire surface of the wafer, a second step of forming an i-type silicon layer with substantially intrinsic amorphous silicon or a substantially intrinsic polycrystalline silicon layer as a main component, in a region located on one principal surface of the n-type crystalline silicon wafer, of the high concentration n-type dopant-containing silicon oxide layer, a third step of thermally treating the n-type crystalline silicon wafer, diffusing the n-type dopant to the n-type crystalline silicon wafer and the i-type silicon layer from the high concentration n-type dopant-containing silicon oxide layer, forming, in the entire wafer surface and a vicinity of the entire wafer surface, an n+ layer having a higher concentration of the n-type dopant than other regions, and forming an n-type crystalline silicon layer by crystallizing the i-type silicon layer, a fourth step of removing an exposed part that is not covered with the n-type crystalline silicon layer, of a low concentration n-type dopant-containing silicon oxide layer formed by the n-type dopant being partially removed by the third step, and a fifth step of forming a p-type amorphous silicon layer on the other principal surface side of the n-type crystalline silicon wafer.
According to one aspect of the present disclosure, a solar cell with a high open circuit voltage (VOC), and a low breakdown voltage can be provided.
The figures depict one or more implementations in accordance with the present teachings, by way of example only, not by way of limitations. In the figures, like reference numerals refer to the same or similar elements.
A solar cell of the present disclosure has an n+ layer in an entire surface of an n-type crystalline silicon wafer and the vicinity thereof, and includes a silicon oxide layer and an n-type crystalline silicon layer on a light receiving surface of the wafer. On a rear surface of the n-type crystalline silicon wafer, a silicon oxide layer is not formed, but a p-type amorphous silicon layer is formed. By adopting a structure like this, a solar cell having a higher open circuit voltage (VOC), and a lower breakdown voltage compared with the conventional solar cell can be obtained.
Further, the solar cell of the present disclosure includes the crystalline silicon layer on a light receiving surface side of the n-type crystalline silicon wafer as described above, so that an amount of light incident on the wafer is larger, and a higher output characteristic is obtained, compared with the conventional cell including an amorphous silicon layer on the light receiving surface side.
Hereinafter, with reference to the drawings, one example of an embodiment will be described in detail. Note that the solar cell of the present disclosure is not limited to the embodiment described hereinafter. The drawings that are referred to in explanation of the embodiment are schematically illustrated, and dimensions and the like of the components shown in the drawings should be judged with the following explanation taken into consideration.
In the present specification, the description “substantially ˜” is intended to include not only an entire region but also a case substantially recognized as the entire region, explaining with a substantially entire region cited as an example. Further, an n-type dopant means an impurity that functions as a donor, and a p-type dopant means an impurity that functions as an acceptor. Hereinafter, as the silicon oxide layer that is formed on the light receiving surface of the n-type crystalline silicon wafer, a low concentration p-containing silicon oxide layer 13 including low concentration P is illustrated, but the silicon oxide layer may contain an n-type dopant other than P.
Here, “light receiving surface S1” of the n-type crystalline silicon wafer 12 means a first principal surface on which light is mainly incident (more than 50% to 100%), and “rear surface S2” means a second principal surface on an opposite side to the light receiving surface. Further, “side surface S3” of the n-type crystalline silicon wafer 12 is a surface along a thickness direction of the wafer.
The solar cell 10 is configured by a photoelectric conversion part 11 including the n-type crystalline silicon wafer 12 and the above described respective layers formed on the wafer, and electrodes formed on the photoelectric conversion part 11. In the present embodiment, a transparent conductive layer 20 (first transparent conductive layer) is formed on the n-type crystalline silicon layer 14 of the photoelectric conversion part 11, and a collector electrode 21 (first collector electrode) is formed on the transparent conductive layer 20. Further, a transparent conductive layer 22 (second transparent conductive layer) is formed on the p-type amorphous silicon layer 16, and a collector electrode 23 (second collector electrode) is formed on the transparent conductive layer 22. The transparent conductive layer 20 and the collector electrode 21 constitute a light receiving surface electrode that collects electrons generated in the n-type crystalline silicon wafer 12, and the transparent conductive layer 22 and the collector electrode 23 constitute a rear surface electrode that collects positive holes generated in the n-type crystalline silicon wafer 12.
The n-type crystalline silicon wafer 12 may be an n-type polycrystalline silicon wafer, but is preferably an n-type monocrystalline silicon wafer. The n-type crystalline silicon wafer 12 has, for example, a substantially square shape and has a thickness of 50 to 300 μm. The substantially square shape includes an octagon including two pairs of long sides parallel with one another, with short sides and long sides alternately. For the n-type crystalline silicon wafer 12, a wafer produced by the Czochralski method is used in general, but a wafer produced by an epitaxial growth method may be used.
The n-type crystalline silicon wafer 12 has an n-type dopant. As the n-type dopant, phosphorous (P), arsenic (As), antimony (Sb) and the like are illustrated, and phosphorous (P) is preferably used. A concentration of the n-type dopant in the entire surface of the n-type crystalline silicon wafer 12 and a vicinity thereof is higher than concentrations of the n-type dopants in other regions. That is, in the n-type crystalline silicon wafer 12, an n+ layer 12a that is a high dope region with a high concentration of the n-type dopant is present in the entire wafer surface and the vicinity thereof, and a low dope region with a lower concentration of the n-type dopant than the n+ layer 12a is present in a region away from the vicinity of the wafer surface. Here, the wafer surface means all surfaces including the light receiving surface S1, the rear surface S2 and the side surfaces S3.
The n+ layer 12a is formed with a thickness of 1 μm or less from the surface of the wafer, for example. The n+ layer 12a has a concentration gradient such that the concentration of the n-type dopant decreases as a distance from the wafer surface increases. The concentration of the n-type dopant in the n+ layer 12a is, for example, 1×1020 atoms/cm3 or less, and an example of a preferable concentration range is 1×1017 to 1×1020 atoms/cm3. A concentration of the n-type dopant in regions other than the n+ layer 12a, that is, the low dope region away from the vicinity of the surface of the wafer is, for example, 1×1014 to 1×1016 atoms/cm3. The concentration of the dopant can be measured by a secondary ion mass spectrometry (SIMS).
The n-type crystalline silicon wafer 12 does not substantially contain a p-type dopant such as boron (B). A concentration of the p-type dopant in the n-type crystalline silicon wafer 12 is, for example, less than 1×1014 atoms/cm3, and is a detection limit by the secondary ion mass spectrometry (SIMS) or less. The p-type amorphous silicon layer 16 is deposited in a low-temperature process, and diffusion of boron (B) into the n-type crystalline silicon wafer 12 from the p-type amorphous silicon layer 16 does not substantially occur. Therefore, in the solar cell 10, a compound defect due to diffusion of boron (B) is not formed, and lifetime reduction of carriers due to the compound defect does not occur.
A texture structure (not illustrated) is preferably formed on the surface of the n-type crystalline silicon wafer 12. The texture structure is a surface uneven structure for restraining surface reflection and increasing a light absorption amount of the n-type crystalline silicon wafer 12. The texture structure can be formed by anisotropically etching a (100) plane of a monocrystalline silicon wafer by using an alkaline solution, and an uneven structure in a pyramid shape with a (111) plane as an inclined plane is formed on the surface of the monocrystalline silicon wafer. A height of the unevenness of the texture structure is 1 to 15 μm, for example.
The low concentration P-containing silicon oxide layer 13 is interposed between the light receiving surface S1 of the n-type crystalline silicon wafer 12 and the n-type crystalline silicon layer 14, and restrains recombination of carriers on the light receiving surface S1 side of the cell. The low concentration P-containing silicon oxide layer 13 is a layer having excellent thermal stability from which a passivation property is not lost even when the layer is exposed to a high temperature, and functions as a so-called tunnel oxide film. The low concentration P-containing silicon oxide layer 13 is formed on the entire light receiving surface S1, for example. The low concentration P-containing silicon oxide layer 13 illustrated in
The low concentration P-containing silicon oxide layer 13 is made with a silicon oxide as a main component. A thickness of the low concentration P-containing silicon oxide layer 13 is several angstroms to about 50 angstroms, for example, as a specific example, 1 to 20 angstroms. The thickness of the low concentration P-containing silicon oxide layer 13 is measured by a cross-section observation using a transmission electron microscope (TEM) (the same applies to the other layers). The low concentration P-containing silicon oxide layer 13 is a silicon oxide layer including P at a dilute concentration. The concentration of P in the low concentration P-containing silicon oxide layer 13 is lower than a P concentration in the n+ layer 12a and a P concentration in the n-type crystalline silicon layer 14.
The n-type crystalline silicon layer 14 is formed on the light receiving surface S1 of the n-type crystalline silicon wafer 12 via the low concentration P-containing silicon oxide layer 13. The n-type crystalline silicon layer 14 is formed on a whole area on the low concentration P-containing silicon oxide layer 13, for example. The n-type crystalline silicon layer 14 illustrated in
The n-type crystalline silicon layer 14 is made of a polycrystalline silicon or a microcrystalline silicon doped to an n-type. The n-type crystalline silicon layer 14 contains an n-type dopant, and a concentration of the n-type dopant in the layer is 1×1021 atoms/cm3 or less. An example of a preferable concentration range is 1×1018 to 1×1021 atoms/cm3. A thickness of the n-type crystalline silicon layer 14 is 5 to 50 nm, for example. A resistivity of the n-type crystalline silicon layer 14 is higher than that of the transparent conductive layer 20, and is 0.1 to 150 nigIcm, for example.
As for n-type dopant concentrations of the respective layer per unit volume in the present embodiment, the P concentration in the low concentration P-containing silicon oxide layer 13 is the lowest, followed by the n+ layer 12a, and the P concentration in the n-type crystalline silicon layer 14 is the highest. Further, the P concentration in the low concentration P-containing silicon oxide layer 13 is higher than the concentration in the low dope region of the n-type crystalline silicon wafer 12.
A crystallization rate of the n-type crystalline silicon layer 14 is lower than a crystallization rate of the n-type crystalline silicon wafer 12. Note that the crystallization rate of the n-type crystalline silicon layer 14 is higher than a crystallization rate of the p-type amorphous silicon layer 16. The crystallization rates of the n-type crystalline silicon wafer 12, the n-type crystalline silicon layer 14 and the p-type amorphous silicon layer 16 are measured by cross-section observation of the wafer and the respective layers using a transmission electron microscope (TEM). The crystallization rate is obtained as a ratio of an area of a silicon crystal lattice to an area of an observation region.
An absorption coefficient in a wavelength range of 400 to 600 nm of the n-type crystalline silicon layer 14 is lower than the absorption coefficient of the p-type amorphous silicon layer 16, and is 5×104 to 4×105 cm−1 at a wavelength of 420 nm, for example. A refractive index of the n-type crystalline silicon layer 14 is 2.5 times as high as a refractive index of the transparent conductive layer 20 or more, or 2.5 to 3.2 times as high as the refractive index of the transparent conductive layer 20, for example, in a wavelength range of 355 to 405 nm. When the refractive index of the n-type crystalline silicon layer 14 is in this range, color irregularity of the cell is reduced, and favorable appearance can be easily obtained. Absorption coefficients and refractive indexes of the respective layers are obtained by a spectroscopic ellipsometry device.
The n-type crystalline silicon layer 14 has a lower hydrogen concentration than the p-type amorphous silicon layer 16. Further, the n-type crystalline silicon layer 14 has a lower hydrogen concentration than the passivation layer 15. The hydrogen concentration in the n-type crystalline silicon layer 14 is, for example, 1×1018 to 1×1021 atoms/cm3.
The passivation layer 15 is interposed between the rear surface S2 of the n-type crystalline silicon wafer 12 and the p-type amorphous silicon layer 16, and restrains recombination of carriers on the rear surface S2 side of the cell. The passivation layer 15 is formed on the entire rear surface S2, for example. The passivation layer 15 illustrated in
The passivation layer 15 is made with a substantially intrinsic amorphous silicon (i-type amorphous silicon) or amorphous silicon with a lower concentration of a p-type dopant than the p-type amorphous silicon layer 16 as a main component. The passivation layer 15 may be an i-type amorphous silicon layer that is substantially made of only an i-type amorphous silicon. A thickness of the passivation layer 15 is thicker than the thickness of the low concentration P-containing silicon oxide layer 13, for example, and an example of a preferable thickness range is 5 to 10 nm.
The p-type amorphous silicon layer 16 is formed on the rear surface S2 of the n-type crystalline silicon wafer 12 via the passivation layer 15. The p-type amorphous silicon layer 16 is formed in a whole area on the passivation layer 15, for example. The p-type amorphous silicon layer 16 illustrated in
The p-type amorphous silicon layer 16 is made of an amorphous silicon doped to a p-type. A concentration of the p-type dopant in the p-type amorphous silicon layer 16 is, for example, 1×1020 atoms/cm3 or more. As the p-type dopant, boron (B), gallium (Ga) and the like can be illustrated. The p-type amorphous silicon layer 16 contains, for example, boron (B) substantially uniformly. Note that a hydrogen concentration of the p-type amorphous silicon layer 16 is higher than the hydrogen concentration of the n-type crystalline silicon layer 14.
The transparent conductive layer 20 is formed on the light receiving surface S1 of the n-type crystalline silicon wafer 12 via the low concentration P-containing silicon oxide layer 13 and the n-type crystalline silicon layer 14. Further, the transparent conductive layer 22 is formed on the rear surface S2 of the n-type crystalline silicon wafer 12 via the passivation layer 15 and the p-type amorphous silicon layer 16. The transparent conductive layers 20 and 22 may be respectively formed on whole of the respective principal surfaces, or may be respectively formed in ranges except for belt-shaped peripheral regions of a width of 2 mm or less from ends of the respective principal surfaces in the respective principal surfaces. The transparent conductive layers 20 and 22 are made of a transparent conductive oxide (IWO, ITO or the like) obtained by doping a metal oxide such as an indium oxide (In2O3) and a zinc oxide (ZnO) with tungsten (W), tin (Sn), antimony (Sb) and the like. Thicknesses of transparent conductive layers 20 and 22 are, for example, 30 to 500 nm.
The collector electrodes 21 and 23 respectively contain, for example, a plurality of finger parts, and two or more bus bar parts. The finger parts are electrodes in a thin line shape that are formed in wide ranges of the transparent conductive layers 20 and 22. The bus bar parts are electrodes in a thin line shape that collect carriers from the finger parts, and are formed substantially orthogonal to the respective finger parts. The collector electrodes 21 and 23 may be formed by coating conductive paste on the transparent conductive layers 20 and 22 respectively in patterns including a large number of finger parts and two or more bus bar parts. The collector electrodes 21 and 23 contain, for example, a binder resin such as an acrylic resin, an epoxy resin and phenolic novolac, and conductive particles of silver, copper, nickel or the like dispersed in the binder resin.
The collector electrode 23 is preferably formed with a larger area than the collector electrode 21, and the number of finger parts of the collector electrode 23 which are formed is larger than the number of finger parts of the collector electrode 21. Accordingly, an area of the transparent conductive layer 22 covered with the collector electrode 23 is larger than an area of the transparent conductive layer 20 covered with the collector electrode 21. With a configuration like this, carrier collection efficiency can be enhanced on the rear surface side that is not the light receiving surface side on which light is mainly incident, and output of the solar cell 10 can be enhanced. However, a structure of the electrodes is not limited to this, and a metal layer may be formed on the substantially whole area on the transparent conductive layer 22 as the collector electrode of the rear surface electrode.
As illustrated in
(1) A First step of submerging the n-type crystalline silicon wafer 12z in an acid aqueous solution containing an n-type dopant, and forming a high concentration n-type dopant-containing silicon oxide layer on the entire wafer surface.
(2) A second step of forming an i-type silicon layer 14z having a substantially intrinsic amorphous silicon, or a substantially intrinsic polycrystalline silicon layer as a main component, in a region located on one principal surface (light receiving surface S1) of the n-type crystalline silicon wafer 12z of the high concentration n-type dopant-containing silicon oxide layer.
(3) A third step of thermally treating the n-type crystalline silicon wafer 12z, and diffusing an n-type dopant to the n-type crystalline silicon wafer 12z and the i-type silicon layer 14z from the high concentration n-type dopant-containing silicon oxide layer.
(4) A fourth step of removing an exposed part, that is not covered with the n-type crystalline silicon layer 14, of a low concentration n-type dopant-containing silicon oxide layer formed by the n-type dopant that was partially removed in the step (3).
(5) A fifth step of forming the p-type amorphous silicon layer 16 on the other principal surface (rear surface S2) side of the n-type crystalline silicon wafer 12.
In the aforementioned step (3), in the entire wafer surface and the vicinity thereof, the n+ layer 12a having a higher concentration of the n-type dopant than other regions is formed, the i-type silicon layer 14z is crystallized and the n-type crystalline silicon layer 14 is formed. Further, in the step (3), the n-type dopant is partially removed from the high concentration n-type dopant-containing silicon oxide layer, and the low concentration n-type dopant-containing silicon oxide layer containing a low concentration n-type dopant is formed. Thermal treatment in the step (3) is thermal diffusion treatment of the n-type dopant. The above described production process of the solar cell 10 uses an oxide film formed in a wet process as a diffusion source of the n-type dopant. The low concentration n-type dopant-containing silicon oxide layer substantially functions as a tunnel oxide film.
Hereinafter, phosphorous (P) is assumed to be applied to the n-type dopant contained in the high concentration n-type dopant-containing silicon oxide layer, and the high concentration n-type dopant-containing silicon oxide layer is described as a high concentration P-containing silicon oxide layer 13z. In the wet process in the above described step (1), for example, aqueous phosphoric acid solution is used as the acid aqueous solution (oxidizing chemical solution for silicon) containing the n-type dopant. An example of a preferable acid aqueous solution is a mixed solution of phosphoric acid and nitric acid. For example, a mixed solution is used, which is obtained by mixing an aqueous nitric acid solution of 85 mass % concentration and an aqueous phosphoric acid solution of 70 mass % concentration at a volume ratio of the aqueous nitric acid solution of: the aqueous phosphoric acid solution=10:90 to 50:50, preferably 20:80 to 40:60. Besides the above, an aqueous solution obtained by mixing phosphoric acid as a supply source of the n-type dopant (P) into an aqueous solution having an ability to oxidize the surface of the crystalline silicon wafer 12 may be used. As one example, a mixed solution may be used, which is obtained by further adding phosphoric acid into a mixed solution of a hydrogen peroxide solution (H2O2) and hydrochloric acid (HCl).
In the production process of the solar cell 10, the n-type crystalline silicon wafer 12z with a texture structure formed on a surface is prepared first. Subsequently, as illustrated in
As described above, the high concentration P-containing silicon oxide layer 13z is formed by the wet process of submerging the n-type crystalline silicon wafer 12z in the mixed solution of phosphoric acid and nitric acid. By submerging the n-type crystalline silicon wafer 12z in the mixed solution, the high concentration P-containing silicon oxide layer 13z is formed with a thickness of, for example, several angstroms to about 20 angstroms on the entire surface of the wafer including the light receiving surface S1, the rear surface S2 and the side surfaces S3.
One example of a preferable treatment temperature in the present process is 10° C. to 90° C. That is, in the present process, the mixed solution adjusted to a temperature of 10° C. to 90° C. is used. A submerging time period is, for example, one minute to 20 minutes. The thickness and the properties of the high concentration P-containing silicon oxide layer 13z can be adjusted by a mixing ratio of a plurality of acid solutions contained in the oxidizing chemical solution for silicon, concentrations of the respective acid solutions, the treatment temperature, the submerging time period and the like.
Next, as illustrated in
The i-type silicon layer 14z is deposited by CVD or sputtering, for example. In deposition of the n-type amorphous silicon layer by CVD, source gas obtained by diluting silane gas (SiH4) by hydrogen can be used. A deposition temperature is, for example, 200 to 300° C. When the deposition temperature is 300° C. or less, an amorphous silicon layer is formed, and diffusion of P from the high concentration P-containing silicon oxide layer 13z does not substantially occur.
Next, the n-type crystalline silicon wafer 12z on which the i-type silicon layer 14z is formed is thermally treated. As illustrated in
The above described thermal treatment is carried out under a nitrogen atmosphere, for example. One example of a preferable temperature range of the heat treatment is 800° C. to 1000° C. The thermal treatment time period is about one minute to 100 minutes, for example. By changing the thermal treatment conditions, a depth in which P diffuses, a concentration of P and the like can be adjusted.
Note that hydrogen (H2) sintering may be performed to the n-type crystalline silicon wafer 12 after the above described thermal treatment. Hydrogen sintering is performed by thermally treating the n-type crystalline silicon wafer 12 at a temperature of about 350 to 450° C. in forming gas obtained by diluting hydrogen gas with inert gas such as nitrogen gas, for example.
Next, as illustrated in
Next, as illustrated in
The passivation layer 15 and the p-type amorphous silicon layer 16 are deposited by CVD or sputtering, for example. In deposition of the passivation layer 15 (i-type amorphous silicon layer) by CVD, source gas obtained by diluting silane gas (SiH4) with hydrogen can be used. Further, in deposition of the p-type amorphous silicon layer 16 by CVD, source gas is used, which is obtained by adding diborane (B2H6) to silane gas (SiH4), and diluting the silane gas with diborane added, with hydrogen. By changing a mixing concentration of diborane, the p-type dopant concentration in the p-type amorphous silicon layer 16 can be adjusted.
The solar cell 10 is produced by forming electrodes on the photoelectric conversion part 11 obtained by the aforementioned method. In an electrode forming step of the present embodiment, the transparent conductive layers 20 and 22 are respectively formed on the n-type crystalline silicon layer 14 and on the p-type amorphous silicon layer 16. Next, the collector electrodes 21 and 23 are respectively formed on the transparent conductive layers 20 and 22. The transparent conductive layers 20 and 22 are formed by sputtering, for example. The collector electrodes 21 and 22 are formed by, for example, coating conductive paste containing silver (Ag) particles on the respective transparent conductive layers by screen printing or the like.
According to the aforementioned production method, the solar cell 10 having a high open circuit voltage (VOC), and a low breakdown voltage can be obtained. The solar cell 10 has favorable appearance with no or reduced color unevenness, and has excellent durability.
The solar cell 30 includes the low concentration P-containing silicon oxide layer 13 formed on the light receiving surface S1 of the n-type crystalline silicon wafer 12, and the n-type crystalline silicon layer 14 formed on the low concentration P-containing silicon oxide layer 13, similarly to the case of the solar cell 10. The solar cell 30 further includes a protection layer 31 on the n-type crystalline silicon layer 14. The protection layer 31 protects the n-type crystalline silicon layer 14, for example, and suppresses reflection of solar light in the surface of the cell. The protection layer 31 is preferably made of a material with high optical transparency, and is made with an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride as a main component, for example.
The solar cell 30 includes an n-type amorphous silicon layer 32 formed on a first region on the rear surface S2 of the n-type crystalline silicon wafer 12, and an insulation layer 33 formed in a part on the n-type amorphous silicon layer 32. Further, the solar cell 30 includes a p-type amorphous silicon layer 34 formed on a second region of the rear surface S2 of the n-type crystalline silicon wafer 12 and on the insulation layer 33. Further, the solar cell 30 preferably includes passivation layers 35 and 36 that are respectively formed between the n-type crystalline silicon wafer 12 and the respective amorphous silicon layers. The n-type amorphous silicon layer 32 and the p-type amorphous silicon layer 34 respectively form a p-type region and an n-type region on a rear surface side of the n-type crystalline silicon wafer 12.
An area of the p-type region formed on the rear surface S2 of the n-type crystalline silicon wafer 12 is preferably larger than an area of the n-type region. The p-type regions and the n-type regions are alternately disposed in one direction, for example, and are formed in a comb-shaped pattern in plan view in which the p-type regions and the n-type regions are meshed with each other. In the solar cell 30, a part of the p-type region overlaps a part of the n-type region, and the p-type regions and the n-type regions are formed without a gap on the rear surface S2 of the n-type crystalline silicon wafer 12. In portions where the p-type region and the n-type region overlap each other, the insulation layer 33 is provided between the respective regions. The insulation layer 33 is made, for example, by using silicon oxide, silicon nitride, silicon oxynitride or the like as a main component. The insulation layer 33 may be made of the same material as the protection layer 31.
The n-type amorphous silicon layer 32 is an amorphous silicon layer doped to n-type. A concentration of the n-type dopant in the n-type amorphous silicon layer 32 is, for example, 1×1020 atoms/cm3 or more. The n-type dopant is not specially limited, but P is used in general. The n-type amorphous silicon layer 32 and the p-type amorphous silicon layer 34 have higher hydrogen concentrations than the n-type crystalline silicon layer 14. The passivation layers 35 and 36 are each made with substantially intrinsic i-type amorphous silicon, or amorphous silicon having a lower concentration of the n-type dopant than the n-type amorphous silicon layer 32 as a main component.
The solar cell 30 includes a transparent conductive layer 37 (first transparent conductive layer) and a collector electrode 38 (first collector electrode) that are formed on the n-type amorphous silicon layer 32, and a transparent conductive layer 39 (second transparent conductive layer) and a collector electrode 40 (second collector electrode) that are formed on the p-type amorphous silicon layer 34. The transparent conductive layers 37 and 39 are separated from each other in a position corresponding to the insulation layer 33. The collector electrodes 38 and 40 are formed respectively on the transparent conductive layers 37 and 39. The collector electrodes 38 and 40 are made of a metal such as nickel (Ni), copper (Cu), and silver (Ag), may be of a laminated structure of an Ni layer and a Cu layer, and may have a tin (Sn) layer on the top surface to enhance corrosion resistance.
The solar cell 30 can be produced by the aforementioned production method using an oxide film formed in a wet process as a diffusion source of the n-type dopant, similarly to the solar cell 10. That is, a photoelectric conversion part of the solar cell 30 can be produced through the aforementioned steps (1) to (5).
While the foregoing has described what are considered to be the best mode and/or other examples, it is understood that various modifications may be made therein and that the subject matter disclosed herein may be implemented in various forms and examples, and that they may be applied in numerous applications, only some of which have been described herein. It is intended by the following claims to claim any and all modifications and variations that fall within the true scope of the present teachings.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2016-153445 | Aug 2016 | JP | national |
The present application is a continuation under 35 U.S.C. § 120 of PCT/JP2017/026187, filed Jul. 20, 2017, which is incorporated herein by reference and which claimed priority to Japanese Patent Application No. 2016-153445 filed Aug. 4, 2016. The present application likewise claims priority under 35 U.S.C. § 119 to Japanese Patent Application No. 2016-153445 filed Aug. 4, 2016, the entire content of which is also incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2017/026187 | Jul 2017 | US |
| Child | 16259178 | US |
