Patent Application
20190027637
The present disclosure relates to a solar cell and a manufacturing method thereof, and in particular to a backside-junction type solar cell and a manufacturing method thereof.
As a solar cell having a high power generation efficiency, there is known a backside-junction type solar cell in which both an n-type semiconductor layer and p-type semiconductor layer are formed over a back surface which opposes a light receiving surface on which light is incident. In the backside-junction type solar cell, there are some cases in which, after a transparent conductive layer is formed over an amorphous silicon layer, the transparent conductive layer is vaporization-machined using a laser, to separate electrodes.
When an electrode separation process for the transparent conductive layer is executed by vaporization using a laser, there had been a possibility that a leakage path is formed in the amorphous silicon layer, which resulted in degradation of characteristics of the solar cell.
The present disclosure has been made in consideration of the above circumstances, and an advantage of the present disclosure lies in provision of a solar cell having a higher power generation efficiency.
According to one aspect of the present disclosure, there is provided a solar cell, which is of a backside junction type in which an electrode portion is provided only over one surface of main surfaces of a semiconductor substrate, the solar cell including: a first amorphous silicon layer provided over a side of the one surface of the semiconductor substrate; and the electrode portion provided over the first amorphous silicon layer, wherein the electrode portion includes an n-side electrode which collects electrons and a p-side electrode which collects holes, the n-side electrode and the p-side electrode being separated from each other by a groove, and grains including at least one of amorphous silicon, microcrystalline silicon, and polycrystalline silicon discretely exist in at least one layer of the first amorphous silicon layer provided in a region in which the groove is formed.
According to another aspect of the present disclosure, there is provided a method of manufacturing a solar cell, which is of a backside-junction type in which an electrode portion is provided only over one surface of main surfaces of a semiconductor substrate, the method including: a thin film formation step in which a layered structure of an insulating layer, an amorphous silicon layer formed over the insulating layer, and a transparent conductive layer formed over the amorphous silicon layer is formed over the one surface of the semiconductor substrate; a first laser irradiation step in which a laser including a wavelength band which is absorbed by the transparent conductive layer is irradiated onto the layered structure from above the one surface of the semiconductor substrate, to remove the transparent conductive layer; and a second laser irradiation step in which, after the first laser irradiation step, a laser is again irradiated onto a region in which the transparent conductive layer is removed.
According to various aspects of the present disclosure, formation of the leakage path by the laser machining can be suppressed, and a solar cell having a high power generation efficiency can be provided.
The figures depict one or more implementations in accordance with the present teaching, by way of example only, not by way of limitations. In the figures, like reference numerals refer to the same or similar elements.
An embodiment of the present disclosure will now be described in detail with reference to the drawings. In the description of the drawings, the same elements are assigned the same reference numerals, and repetitious descriptions thereof will be omitted as suited.
The solar cell 70 comprises an n-side electrode 14 and a p-side electrode 15 provided over the back surface 70b. The n-side electrode 14 is formed in a comb shape including a bus bar electrode 14a extending in an x direction and a plurality of finger electrodes 14b extending in a y direction. Similarly, the p-side electrode 15 is formed in a comb shape including a bus bar electrode 15a extending in the x direction and a plurality of finger electrodes 15b extending in the y direction. The n-side electrode 14 and the p-side electrode 15 are formed in such a manner that the teeth thereof are interposed between each other. Alternatively, each of the n-side electrode 14 and the p-side electrode 15 may be a bus bar-less type electrode having only the plurality of fingers and no bus bar.
The semiconductor substrate 10 has a first main surface 10a provided on the side of a light receiving surface 70a, and a second main surface 10b provided on the side of the back surface 70b. The semiconductor substrate 10 absorbs light incident on the first main surface 10a, and generates electrons and holes as carriers. The semiconductor substrate 10 is formed from a crystalline semiconductor material having a conductivity type of an n-type or a p-type. The semiconductor substrate 10 in the present embodiment is an n-type monocrystalline silicon wafer.
The light receiving surface 70a refers to a main surface onto which light (solar light) is primarily incident in the solar cell 70, and more specifically refers to a surface onto which most of the light incident on the solar cell 70 is incident. On the other hand, the back surface 70b refers to the other main surface which opposes the light receiving surface 70a.
A first layered structure 12 and a second layered structure 13 are formed over the second main surface 10b of the semiconductor substrate 10. Each of the first layered structure 12 and the second layered structure 13 is formed in a comb shape corresponding to the n-side electrode 14 and the p-side electrode 15, and the layered structures are formed in such a manner as to interpose each other. Because of this, a first region W1 in which the first layered structure 12 is provided and a second region W2 in which the second layered structure 13 is provided are alternately arranged in the x direction over the second main surface 10b. In addition, the first layered structure 12 and the second layered structure 13 adjacent in the x direction are provided in contact with each other. Therefore, in the present embodiment, substantially the entirety of the second main surface 10b is covered by the first layered structure 12 and the second layered structure 13.
The first layered structure 12 is formed from the first passivation layer 12i formed over the second main surface 10b, and the first conductivity type layer 12n formed over the first passivation layer 12i. The first passivation layer 12i is formed from a substantially intrinsic amorphous semiconductor (hereinafter, intrinsic semiconductor will be also referred to as “i-type layer”). In the present embodiment, an “amorphous semiconductor” includes a microcrystalline semiconductor. A microcrystalline semiconductor refers to a semiconductor in which semiconductor crystals are precipitated in the amorphous semiconductor.
The first passivation layer 12i is formed from i-type amorphous silicon including hydrogen (H), and has a thickness of for example, about a few nm˜25 nm. No particular limitation is imposed on a formation method of the first passivation layer 12i, and, for example, the first passivation layer 12i may be formed by chemical vapor deposition (CVD) such as plasma CVD. It is sufficient that the first passivation layer 12i is a thin film which can reduce recombination centers of carriers on the surface of the semiconductor substrate 10, and the first passivation layer 12i may be formed using silicon oxide (SiO2), silicon nitride (SiN), or silicon oxynitride (SiON).
The first conductivity type layer 12n is formed from an amorphous semiconductor doped with an n-type dopant which is of the same conductivity type as the semiconductor substrate 10. The first conductivity type layer 12n in the present embodiment is formed from n-type amorphous silicon including hydrogen. The first conductivity type layer 12n has, for example, a thickness of about 2 nm 50 nm.
The first insulating layer 16 is formed over the first layered structure 12. The first insulating layer 16 is not provided in a third region W3 corresponding to a central part in the x direction of the first region W1, and is provided in a fourth region W4 corresponding to ends other than the third region W3. A width of the fourth region W4 in which the first insulating layer 16 is formed is, for example, about ⅓ of a width of the first region W1. A width of the third region W3 in which the first insulating layer 16 is not provided is, for example, about ⅓ of the width of the first region W1.
The first insulating layer 16 is formed from, for example, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or the like. The first insulating layer 16 is desirably formed from silicon nitride, and desirably contains hydrogen.
The second layered structure 13 is formed over the second region W2, of the second main surface 10b, in which the first layered structure 12 is not provided, and over an end of the fourth region W4 in which the first insulating layer 16 is provided. Because of this structure, the ends of the second layered structure 13 are provided overlapping the first layered structure 12 in a height direction (z direction).
The second layered structure 13 is formed from the second passivation layer 13i formed over the second main surface 10b, and the second conductivity type layer 13p formed over the second passivation layer 13i. The second passivation layer 13i is formed from i-type amorphous silicon including hydrogen, and has a thickness of, for example, about a few nm˜25 nm. Similar to the first passivation layer 12i, the second passivation layer 13i may be formed using silicon oxide (SiO2), silicon nitride (SiN), or silicon oxynitride (SiON).
The second conductivity type layer 13p is formed from an amorphous semiconductor doped with a p-type dopant which is of a different conductivity type than the semiconductor substrate 10. The second conductivity type layer 13p in the present embodiment is formed from p-type amorphous silicon including hydrogen. The second conductivity type layer 13p has a thickness of, for example, about 2 m˜50 nm.
Here, the i-type amorphous silicon refers to amorphous silicon having a dopant content of less than 1×1019 cm−3. The n-type amorphous silicon refers to amorphous silicon having an n-type dopant content of greater than or equal to 5×1019 cm−3. Further, the p-type amorphous silicon refers to amorphous silicon having a p-type dopant content of greater than or equal to 5×1019 cm−3.
The n-side electrode 14 which collects the electrons is formed over the first conductivity type layer 12n. The p-side electrode 15 which collects the holes is formed over the second conductivity type layer 13p. A groove is formed between the n-side electrode 14 and the p-side electrode 15, and the electrodes are electrically insulated from each other. In the present embodiment, the n-side electrode 14 and the p-side electrode 15 are formed from a layered structure of four conductive layers including a first conductive layer 19a to a fourth conductive layer 19d, which are insulated by formation of the groove in the fourth region W4.
The first conductive layer 19a is formed from a transparent conductive oxide (TCO) such as, for example, tin oxide (SnO2), zinc oxide (ZnO), and indium tin oxide (ITO). The first conductive layer 19a in the present embodiment is formed from the indium tin oxide, and has a thickness of, for example, about 50 nm˜100 nm.
The second conductive layer 19b to the fourth conductive layer 19d are made of a conductive material including metals such as copper (Cu), tin (Sn), gold (Au), silver (Ag), or the like. In the present embodiment, the second conductive layer 19b and the third conductive layer 19c are formed from copper, and the fourth conductive layer 19d is formed from tin. The second conductive layer 19b, the third conductive layer 19c, and the fourth conductive layer 19d respectively have thicknesses of about 50 nm˜1000 nm, about 10 μm˜20 μm, and about 1 μm˜5 μm.
No particular limitation is imposed on a formation method of the first conductive layer 19a through the fourth conductive layer 19d, and the conductive layers can be formed, for example, by a thin film formation method such as sputtering and chemical vapor deposition (CVD), or by plating. In the present embodiment, the first conductive layer 19a and the second conductive layer 19b are formed by the thin film formation method, and the third conductive layer 19c and the fourth conductive layer 19d are formed by plating.
The third passivation layer 17i is provided over the first main surface 10a of the semiconductor substrate 10. The third passivation layer 17i is formed from i-type amorphous silicon including hydrogen, and has a thickness of, for example, about a few nm˜25 nm. Similar to the first passivation layer 12i, the third passivation layer 17i may be formed from silicon oxide (SiO2), silicon nitride (SiN), or silicon oxynitride (SiON).
The third conductivity type layer 17n is provided over the third passivation layer 17i. The third conductivity type layer 17n is formed from an amorphous semiconductor doped with n-type dopant which is of the same conductivity type as the semiconductor substrate 10. The third conductivity type layer 17n in the present embodiment is formed from n-type amorphous silicon including hydrogen, and has a thickness of, for example, about 2 nm˜50 nm.
The second insulating layer 18 which functions as a reflection prevention film and a protective film is provided over the third conductivity type layer 17n. The second insulating layer 18 is formed from, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like. A thickness of the second insulating layer 18 is suitably set according to a reflection prevention characteristic as the reflection prevention film or the like, and is, for example, about 80 nm˜1000 nm.
Alternatively, the layered structure of the third passivation layer 17i, the third conductivity type layer 17n, and the second insulating layer 18 may function as a passivation layer of the semiconductor substrate 10. Further, the third conductivity type layer 17n may be formed from amorphous semiconductor doped with a p-type dopant, or the second insulating layer 18 may be directly layered over the third passivation layer 17i without providing the third conductivity type layer 17n.
Next, a manufacturing method of the solar cell 70 according to the present embodiment will be described with reference to
As shown in
An order of formation of the layers over the first main surface 10a and the second main surface 10b of the semiconductor substrate 10 may be suitably set. In the present embodiment, before the processes for forming the i-type amorphous semiconductor layer 21, the n-type amorphous semiconductor layer 22, and the insulating layer 23 over the second main surface 10b, an i-type amorphous semiconductor layer which becomes the third passivation layer 17i, an n-type amorphous semiconductor layer which becomes the third conductivity type layer 17n, and an insulating layer which becomes the second insulating layer 18 are formed over the first main surface 10a.
Next, as shown in
Next, as shown in
The laser 50 is irradiated in such a manner that irradiation ranges 54 of the laser 50 at adjacent irradiation positions partially overlap each other, and is irradiated while the position is shifted such that a center 52 of the laser 50 is not positioned in an area in which the insulating layer 23 is exposed by the laser irradiation. In other words, the laser 50 is desirably irradiated such that a spacing D2 between adjacent laser irradiations is larger than a radius D1 of the irradiation range 54 in which the first mask layer 31 is removed by the irradiation of the laser 50. By employing a configuration in which the irradiation ranges 54 of the laser 50 do not overlap each other, damage to the semiconductor layers below the insulating layer 23 by the laser irradiation is prevented. In the present embodiment, the irradiation ranges 54 of the laser 50 in adjacent irradiation positions are set to partially overlap each other, but alternatively, a configuration may be employed in which the irradiation ranges 54 of the laser 50 in adjacent irradiation positions do not overlap each other. By discretely placing the irradiation ranges 54 of the laser 50, a number of irradiations of the laser 50 can be reduced, and the manufacturing process can be simplified.
The laser 50 is desirably a short-pulse laser having a pulse width of nanoseconds (ns) or picoseconds (ps), in order to reduce the effect of heat on the laser irradiated area. As such a laser 50, a YAG laser, an excimer laser, or the like may be employed. In the present embodiment, as a laser light source, a third harmonic (having a wavelength of 355 nm) of a Nd:YAG laser (having a wavelength of 1064 nm) is used, and the laser 50 is irradiated with an intensity of approximately 0.1˜0.5 J/cm2 per pulse. In order to allow formation of the first opening 41 by the laser 50 in a short period of time, desirably, a laser light source having a high repetition frequency is used.
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Before the conductive layer 26 is removed, the conductive layer 27 at a portion positioned above the first insulating layer 16 is removed. When the conductive layer 27 is a metal electrode layer, the conductive layer 27 is desirably removed by wet etching, but alternatively, the conductive layer 27 may be removed using a laser. In the machining of the conductive layer 26 by the laser 60, the laser 60 irradiated from above the one surface is absorbed by the conductive layer 26 which is a transparent conductive layer, and the conductive layer 26, the second passivation layer 13i, and the second conductivity type layer 13p are vaporized and removed by heat generated by the absorption. Therefore, the laser 60 includes a wavelength which is absorbed by the conductive layer 26. For example, when the conductive layer 26 is indium tin oxide (ITO), the laser 60 desirably has an oscillation wavelength of shorter than or equal to 330 nm. In addition, an irradiation energy density of the laser 60 is desirably greater than or equal to 0.08 J/cm2 and less than or equal to 0.17 J/cm2.
In this manner, by the polycrystalline silicon grains 13b being connected by the bridge part 13c, a conductive (short-circuited) state is realized in a surface direction of the first insulating layer 16. Therefore, if the structure is left in this state, the characteristic of the solar cell 70 may be degraded.
In consideration of this, as shown in
Here, it is desirable to perform the processing such that an average distance between central positions of the remaining polycrystalline silicon grains 13b is larger than a diameter of the polycrystalline silicon grain 13b. With the irradiation conditions of the laser 60 and the laser 62, the diameter of the polycrystalline silicon grain 13b is about 100 nm. Thus, the average distance of the polycrystalline silicon grains 13b is desirably greater than 100 nm, and, for example, the average distance of the polycrystalline silicon grains 13b is set to greater than or equal to 250 nm.
A degree of crystallization of the amorphous silicon layer 13a is higher at the side of the irradiation surface of the laser 62 than the side of the non-irradiation surface, or is approximately constant in the thickness direction. The degree of crystallization may be calculated from a ratio of an intensity of a peak around 520 cm−1 and an intensity of a peak around 470 cm−1 in the Raman spectrum. In addition, a difference in the degree of crystallization can be inspected by a lattice image of a cross-sectional transmissive electron microscope observation (cross-sectional TEM).
Moreover, the compositions of the surface state over the first insulating layer 16 shown in
With such a process, the characteristic of the solar cell 70 can be improved compared to a case where the further process by the laser 62 after the process by the laser 60 is not applied.
Finally, the third conductive layer 19c including copper (Cu) and the fourth conductive layer 19d including tin (Sn) are formed by plating over the first conductive layer 19a and the second conductive layer 19b. The third conductive layer 19c and the fourth conductive layer 19d are formed by plating, through a process of setting the first conductive layer 19a and the second conductive layer 19b as seed layers, and applying a current. With the manufacturing process described above, the solar cell 70 as shown in
According to the present embodiment, the electrical shorting (short-circuiting) at an interface between the polycrystalline silicon grain 13b and the bridge part 13c can be suppressed, and the characteristic of the solar cell 70 can be improved.
In the embodiment described above, the process by the laser 62 is applied to the entirety of the region in which the conductive layers 26 and 27, the second passivation layer 13i, and the second conductivity type layer 13p are vaporized. Alternatively, the connection state by the polycrystalline silicon grains 13b and the bridge part 13c may be taken advantage of.
Specifically, in the solar cell 70, a hot spot phenomenon may occur in which, when a part of the surface of the solar cell 70 is set in shadow for some reason, heat is generated in the shadow portion, and the shadow portion is damaged. As a countermeasure for the hot spot, a method is employed in which a bypass diode is provided between the n-side electrode 14 and the p-side electrode 15, of the solar cell 70, which are adjacent to each other, to bypass an excessive current in the hot spot region.
For this purpose, a leakage route (leakage path) of a current may be formed between the n-side electrode 14 and the p-side electrode 15 which are adjacent to each other, using the polycrystalline silicon grain 13b and the bridge part 13c, and the current may flow through the leakage path when the hot spot phenomenon occurs.
For example, as shown in a surface enlarged view over the first insulating layer 16 of
By providing the leakage path taking advantage of the connection state by the polycrystalline silicon grains 13b and the bridge part 13c, it becomes possible to prevent damages of the solar cell 70 due to the hot spot.
The present disclosure has been described with reference to the embodiment and the alternative configuration. The present disclosure, however, is not limited to the embodiment and the alternative configuration, and the structures of the embodiment and the alternative configuration may be suitably combined or substituted.
While the foregoing has described what are considered to be the best mode and/or other examples, it is understood that various modifications may be made therein and that the subject matter disclosed herein may be implemented in various forms and examples, and that they may be applied in numerous applications, only some of which have been described herein. It is intended by the following claims to claim any and all modifications and variations that fall within the true scope of the present teachings.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2016-063028 | Mar 2016 | JP | national |
This application is a U.S. continuation application of PCT International Patent Application Number PCT/JP2017/000028, filed Jan. 4, 2017, claiming the benefit of priority of Japanese Patent Application Number 2016-063028, filed Mar. 28, 2016, the entire contents of which are hereby incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2017/000028 | Jan 2017 | US |
| Child | 16144287 | US |
