Patent Application
20170200850
This application claims the priority benefit of Korean Patent Application No. 10-2016-0003753, filed on Jan. 12, 2016 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.
1. Field of the invention
Embodiments of the present invention relate to a solar cell having an improved structure and a method of manufacturing the same.
2. Description of the Related Art
Recently, due to depletion of existing energy resources, such as oil and coal, interest in alternative sources of energy to replace the existing energy resources is increasing. Most of all, solar cells are popular next generation cells to convert sunlight into electrical energy.
Solar cells may be manufactured by forming various layers and electrodes based on some design. The efficiency of solar cells may be determined by the design of the various layers and electrodes. In order for solar cells to be commercialized, the problems of low efficiency and low productivity need to be overcome, and thus there is a demand for a solar cell and a method of manufacturing the same, which may maximize the efficiency and productivity of the solar cell.
According to one aspect of the present invention, there is provided a solar cell including a semiconductor substrate, a protective-film layer formed over one surface of the semiconductor substrate, a first conductive area disposed over the protective-film layer, the first conductive area being of a first conductive type and including a crystalline semiconductor, and a first electrode electrically connected to the first conductive area, wherein the first conductive area includes a first portion disposed over the protective-film layer and having a first crystal grain size, and a second portion disposed over the first portion and having a second crystal grain size, which is greater than the first crystal grain size.
According to another aspect of the present invention, there is provided a method of manufacturing a solar cell including forming a protective-film layer over a semiconductor substrate, forming a conductive area having crystallinity over the protective-film layer, and forming an electrode electrically connected to the conductive area, wherein, in the forming the conductive area, the conductive area is formed to include a first portion, which is disposed over the protective-film layer and has a first crystal grain size, and a second portion, which is disposed over the first portion and has a second crystal grain size, which is greater than the first crystal grain size.
The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings. However, it will be understood that the present invention should not be limited to the embodiments and may be modified in various ways.
In the drawings, to clearly and briefly explain the present invention, illustration of elements having no connection with the description is omitted, and the same or extremely similar elements are designated by the same reference numerals throughout the specification. In addition, in the drawings, for more clear explanation, the dimensions of elements, such as thickness, width, and the like, are exaggerated or reduced, and thus the thickness, width, and the like of the present invention are not limited to the illustration of the drawings.
In the entire specification, when an element is referred to as “including” another element, the element should not be understood as excluding other elements so long as there is no special conflicting description, and the element may include at least one other element. In addition, it will be understood that, when an element such as a layer, film, region or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. On the other hand, when an element such as a layer, film, region or substrate is referred to as being “directly on” another element, this means that there are no intervening elements therebetween.
Hereinafter, a solar cell and a method of manufacturing the same according to the embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Referring to
The semiconductor substrate 10 may include the base area 110, which is doped with a first or second conductive dopant at a relatively low doping concentration, and thus is of a first or second conductive type. The base area 110 may be formed of a crystalline semiconductor including the first or second conductive dopant. In one example, the base area 110 may be formed of a monocrystalline or polycrystalline semiconductor (e.g. monocrystalline or polycrystalline silicon) including the first or second conductive dopant. In particular, the base area 110 may be formed of a monocrystalline semiconductor (e.g. a monocrystalline semiconductor wafer, and more specifically, a semiconductor silicon wafer) including the first or second conductive dopant. The solar cell, which is manufactured based on the base area 110 or the semiconductor substrate 10 having high crystallinity and thus low defects, has excellent electrical properties.
In addition, the semiconductor substrate 10 may include a front-surface field area (or a field area) 130, which is located on the other surface (hereinafter, “front surface”) of the semiconductor substrate 10. The front-surface field area 130 may be of the same conductive type as the base area 110, and may have a higher doping concentration than the base area 110.
The present embodiment illustrates the instance where the front-surface field area 130 is configured as a doped area formed by doping the semiconductor substrate 10 with a first or second conductive dopant at a relatively high doping concentration. Thus, the front-surface field area 130 may include a first or second conductive crystalline (monocrystalline or polycrystalline) semiconductor and constitutes a portion of the semiconductor substrate 10. In one example, the front-surface field area 130 may configure a portion of a first or second conductive monocrystalline semiconductor substrate (e.g. a monocrystalline silicon wafer substrate).
At this time, the doping concentration of the front-surface field area 130 may be less than the doping concentration of the first or second conductive area 32 or 34, which is of the same conductive type as the front-surface field area 130. This is because the front-surface field area 130 needs a relatively low doping concentration in order to prevent carriers from moving toward the front surface of the semiconductor substrate 10 while allowing horizontal movement of the carriers. However, the embodiments of the present invention are not limited thereto.
The dopant included in the front-surface field area 130 may be of the same conductive type as the first or second conductive dopant included in the first or second conductive area 32 or 34. The dopant included in the front-surface field area 130 may be the same as or different from the first or second conductive dopant included in the second conductive area 34.
However, the embodiments of the present invention are not limited thereto. Thus, the front-surface field area 130 may be formed by doping a separate semiconductor layer (e.g. an amorphous semiconductor layer, a microcrystalline semiconductor layer, or a polycrystalline semiconductor layer), rather than the semiconductor substrate 10, with a first or second conductive dopant. Alternatively, the front-surface field area 130 may be configured as a field area, which functions similar to a layer (e.g. the front-surface passivation film 24 and/or the anti-reflection film 26), which is formed close to the semiconductor substrate 10 and is doped with a fixed charge. For example, when the base area 110 is of an n-type, the front-surface passivation film 24 may be formed of an oxide (e.g. an aluminum oxide) having a fixed negative charge so as to form an inversion layer on the surface of the base area 110, thereby being used as a field area. In this instance, the semiconductor substrate 10 may include only the base area 110 without a separate doped area, which may minimize defects of the semiconductor substrate 10. The front-surface field area 130 having various structures may be formed using various other methods.
In the present embodiment, the front surface of the semiconductor substrate 10 may be subjected to texturing so as to have protrusions having, for example, a pyramidal shape. The protrusions formed on the semiconductor substrate 10 may have a predetermined shape (e.g. a pyramidal shape) having an outer surface formed along a specific semiconductor crystalline face (e.g. (111). When the roughness of the front surface of the semiconductor substrate 10 is increased by the protrusions formed via texturing, the reflectance of light introduced through the front surface of the semiconductor substrate 10 may be reduced. Thus, the quantity of light, which reaches a pn junction formed by the base area 110 and the first or second conductive area 32 or 34, may be increased, which may minimize shading loss.
In addition, the back surface of the semiconductor substrate 10 may be formed into a relatively smooth flat surface having a lower surface roughness than the front surface via, for example, mirror surface grinding. This is because the properties of the solar cell 100 may considerably vary according to the properties of the back surface of the semiconductor substrate 10 in the instance where both the first and second conductive areas 32 and 34 are formed on the back surface of the semiconductor substrate 10 as in the present embodiment. Accordingly, the back surface of the semiconductor substrate 10 is not provided with the protrusions formed by texturing, so as to achieve improved passivation, which may consequently improve the properties of the solar cell 100. However, the embodiments of the present invention are not limited thereto. In some instances, the back surface of the semiconductor substrate 10 may be provided with protrusions formed by texturing. Various other alterations are also possible.
The protective-film layer 20 may be formed over the back surface of the semiconductor substrate 10. In one example, the protective-film layer 20 may be formed over the entire semiconductor substrate 10 so as to come into contact with the back surface of the semiconductor substrate 10, which may result in a simplified structure and improved tunneling effects. However, the embodiments of the present invention are not limited thereto.
The protective-film layer 20 serves as a barrier for electrons and holes, thereby preventing minority carriers from passing therethrough and allowing only majority carriers, which accumulate at a portion adjacent to the protective-film layer 20 and thus have a predetermined amount of energy or more, to pass therethrough. At this time, the majority carriers, which have a predetermined amount of energy or more, may easily pass through the protective-film layer 20 owing to tunneling effects. In addition, the protective-film layer 20 may serve as a diffusion barrier, which prevents the dopant of the conductive areas 32 and 34 from diffusing to the semiconductor substrate 10. The protective-film layer 20 may include various materials to enable the tunneling of the majority carriers. In one example, the protective-film layer may include amorphous silicon, an oxide, a nitride, a semiconductor, and a conductive polymer. For example, the protective-film layer 20 may include a silicon oxide, a silicon nitride, a silicon oxide nitride, intrinsic amorphous silicon, or intrinsic polycrystalline silicon. In one example, the protective-film layer 20 may be formed of an insulation material, such as, for example, an oxide or a nitride, and in particular, may be configured as a silicon oxide layer including a silicon oxide. This is because the silicon oxide layer has excellent passivation and thus ensures easy tunneling of carriers.
In order to achieve sufficient tunneling effects, the protective-film layer 20 may be thinner than the back-surface passivation film 40. In one example, the thickness of the protective-film layer 20 may be 5 nm or less (more specifically, 2 nm or less, for example, within a range from 0.5 nm to 2 nm). When the thickness of the protective-film layer 20 exceeds 5 nm, smooth tunneling does not occur, and consequently, the solar cell 100 cannot operate. When the thickness of the protective-film layer 20 is below 0.5 nm, it may be difficult to form the protective-film layer 20 having a desired quality. In order to further improve tunneling effects, the thickness of the protective-film layer 20 may be 2 nm or less (more specifically, within a range from 0.5 nm to 2 nm). However, the embodiments of the present invention are not limited thereto, and the thickness of the protective-film layer 20 may have any of various values.
A semiconductor layer 30 including the conductive areas 32 and 34 may be located over the protective-film layer 20. In one example, the semiconductor layer 30 may be formed so as to come into contact with the protective-film layer 20, which may result in a simplified structure and maximized tunneling effects. However, the embodiments of the present invention are not limited thereto.
In the present embodiment, the semiconductor layer 30 may include the first conductive area 32, which includes a first conductive dopant and thus is of a first conductive type, and the second conductive area 34, which includes a second conductive dopant and thus is of a second conductive type. The first conductive area 32 and the second conductive area 34 may be located in the same plane over the protective-film layer 20. That is, no layer may be interposed between the first and second conductive areas 32 and 34 and the protective-film layer 20, or when another layer is interposed between the first and second conductive areas 32 and 34 and the protective-film layer 20, the interposed layer may have the same stack structure. In addition, a barrier area 36 may be located between the first conductive area 32 and the second conductive area 34 in the same plane as the first and second conductive areas 32 and 34.
In one example, in the present embodiment, the base area 110 may be of a second conductive type. At this time, the first conductive area 32 configures an emitter area, which forms a pn junction (or a pn tunnel junction) along with the base area 110 with the protective-film layer 20 interposed therebetween so as to produce carriers via photoelectric conversion. The second conductive area 34 configures a back-surface field area, which forms a back surface field so as to prevent the loss of carriers due to recombination on the surface of the semiconductor substrate 10 (more accurately, on the back surface of the semiconductor substrate 10).
However, the embodiments of the present invention are not limited thereto. The base area 110 may be of a first conductive type. In this instance, the second conductive area 34 configures an emitter area, which forms a pn junction (or a pn tunnel junction) along with the base area 110 with the protective-film layer 20 interposed therebetween so as to produce carriers via photoelectric conversion. The first conductive area 32 configures a back-surface field area, which forms a back surface field so as to prevent the loss of carriers due to recombination on the surface of the semiconductor substrate 10 (more accurately, on the back surface of the semiconductor substrate 10).
At this time, the first conductive area 32 may include a crystalline semiconductor (e.g. silicon) including a first conductive dopant. In addition, the second conductive area 34 may include a crystalline semiconductor (e.g. silicon) including a second conductive dopant.
In the present embodiment, each of the first and second conductive areas 32 and 34 is configured as a semiconductor layer, which is formed over the semiconductor substrate 10 (more particularly, over the protective-film layer 20) separately from the semiconductor substrate 10, and is doped with a first or second conductive dopant. For example, each of the first and second conductive areas 32 and 34 may be formed by doping a polycrystalline semiconductor layer (e.g. a polycrystalline silicon layer), which may be easily manufactured by various methods such as, for example, deposition, with a first or second conductive dopant. The first or second conductive dopant may be added to the semiconductor layer in the process of forming the semiconductor layer, or may be added to the semiconductor layer after the semiconductor layer is formed, through the use of various doping methods, such as, for example, thermal diffusion and ion implantation.
At this time, when the first or second conductive dopant is of a p-type, it may be a group-III element, such as boron (B), aluminum (Al), gallium (ga), or indium (In). When the first or second conductive dopant is of an n-type, it may be a group-V element, such as phosphorus (P), arsenic (As), bismuth (Bi), or antimony (Sb). In one example, the first conductive dopant may be a p-type boron (B), and the second conductive dopant may be an n-type phosphorous (P).
In addition, the barrier area 36 may be located between the first conductive area 32 and the second conductive area 34 so that the first conductive area 32 and the second conductive area 34 are spaced apart from each other. When the first conductive area 32 and the second conductive area 34 are in contact with each other, shunts may occur, undesirably causing deterioration in the performance of the solar cell 100. Therefore, in the present embodiment, unnecessary shunts may be prevented by positioning the barrier area 36 between the first conductive area 32 and the second conductive area 34.
The barrier area 36 may be formed of any of various materials, which may substantially insulate the first conductive area 32 and the second conductive area 34 from each other. That is, the barrier area 36 may be formed of an undoped insulation material (e.g. an oxide or a nitride). Alternatively, the barrier area 36 may include an intrinsic semiconductor. At this time, the first conductive area 32, the second conductive area 34, and the barrier area 36 are formed of the same semiconductor (e.g. a polycrystalline semiconductor, and more specifically, polycrystalline silicon) so that they are successively formed to come into contact with each other at the side surfaces thereof, and the barrier area 36 may be an i-type (intrinsic) semiconductor material that substantially includes no dopant. In one example, after a semiconductor layer is formed of a semiconductor material, an area of the semiconductor layer is doped with a first conductive dopant so as to form the first conductive area 32, and another area of the semiconductor layer is doped with a second conductive dopant so as to form the second conductive area 34, whereby the remaining area in which the first conductive area 32 and the second conductive area 34 are not formed may configure the barrier area 36. Thus, the method of manufacturing the first conductive area 32, the second conductive area 34, and the barrier area 36 may be simplified.
However, the embodiments of the present invention are not limited thereto. Thus, when the barrier area 36 is formed separately from the first conductive area 32 and the second conductive area 34, the barrier area 36 may have a thickness different from the first conductive area 32 and the second conductive area 34. In one example, in order to more effectively prevent a short-circuit between the first conductive area 32 and the second conductive area 34, the barrier area 36 may be thicker than the first conductive area 32 and the second conductive area 34. Alternatively, in order to reduce the amount of a raw material required to form the barrier area 36, the barrier area 36 may be thinner than the first conductive area 32 and the second conductive area 34. Of course, various other alterations are possible. In addition, the basic constituent material of the barrier area 36 may differ from those of the first conductive area 32 and the second conductive area 34.
In addition, the present embodiment illustrates the instance where the barrier area 36 causes the first conductive area 32 and the second conductive area 34 to be wholly spaced apart from each other. However, the embodiments of the present invention are not limited thereto. Thus, the barrier area 36 may be formed to cause the first conductive area 32 and the second conductive area 34 to be spaced apart from each other only along a portion of the boundary therebetween. Thereby, the conductive areas 32 and 34 may come into contact with each other along the remaining portion of the boundary therebetween.
In the present embodiment, in one example, the base area 110 may be of a second conductive type. At this time, the first conductive area 32, which is of a different conductive type from the base area 110, may be wider than the second conductive area 34, which is of the same conductive type as the base area 110. As such, the pn junction, which is formed through the protective-film layer 20 between the base area 110 and the first conductive area 32, may have an increased width. At this time, when the conductive type of the base area 110 and the second conductive area 34 is an n-type and the conductive type of the first conductive area 32 is a p-type, the wide first conductive area 32 may effectively collect holes, which move relatively slowly. However, the embodiments of the present invention are not limited thereto.
The planar structure of the first conductive area 32, the second conductive area 34, and the barrier area 36 will be described below in more detail with reference to
The back-surface passivation film 40 may be formed over the first and second conductive areas 32 and 34 and the barrier area 36 on the back surface of the semiconductor substrate 10. In one example, the back-surface passivation film 40 may come into contact with the first and second conductive areas 32 and 34 and the barrier area 36, thus having a simplified structure. However, the embodiments of the present invention are not limited thereto.
The back-surface passivation film 40 has an opening 402 for connection of the first conductive area 32 and the first electrode 42 and an opening 404 for connection of the second conductive area 34 and the second electrode 44. As such, the back-surface passivation film 40 serves to prevent the first conductive area 32 and the second conductive area 34 from being connected to the incorrect electrode (i.e. the second electrode 44 in the instance of the first conductive area 32 and the first electrode 42 in the instance of the second conductive area 34). In addition, the back-surface passivation film 40 may be used for the passivation of the first and second conductive areas 32 and 34 and/or the barrier area 36.
The front-surface passivation film 24 and/or the anti-reflection film 26 may be located over the front surface of the semiconductor substrate 10 (more accurately, over the front-surface field area 130 formed on the front surface of the semiconductor substrate 10). In some embodiments, only the front-surface passivation film 24 may be formed over the semiconductor substrate 10, only the anti-reflection film 26 may be formed over the semiconductor substrate 10, or the front-surface passivation film 24 and the anti-reflection film may be sequentially located over the semiconductor substrate 10.
The back-surface passivation film 40, the front-surface passivation film 24 and/or the anti-reflection film 26 may be thicker than the protective-film layer 20. As such, insulation and passivation properties may be improved. Various other alterations are possible.
The back-surface passivation film may be formed throughout the back surface of the semiconductor substrate 10 excluding the openings 402 and 404, through which the first and second electrodes 42 and 44 pass. In addition, the front-surface passivation film 24 and the anti-reflection film 26 may substantially be formed through the front surface of the semiconductor substrate 10. Here, “formed throughout” includes not only physically complete formation, but also formation with inevitably excluded parts.
The front-surface or back-surface passivation films 24 and 40 are formed to be brought into contact with the front surface of the semiconductor substrate 10 or the first and second conductive areas 32 and 34 in order to realize the passivation of defects, which are present in the surface or the bulk of the first and second conductive areas 32 and 34. As such, the open-circuit voltage of the solar cell 100 may be increased via the removal of recombination sites of minority carriers. The anti-reflection film 26 reduces the reflectance of light introduced into the front surface of the semiconductor substrate 10. Thus, the quantity of light, which reaches the pn junction formed by the base area 110 and the first or second conductive area 32 or 34, may be increased. Thereby, the short-circuit current Isc of the solar cell 100 may be increased. In this way, the front-surface or back-surface passivation film 24 or 40 and the anti-reflection film 26 may increase the open-circuit voltage and the short-circuit current of the solar cell 100, thereby improving the efficiency of the solar cell 100.
The back-surface passivation film 40, the front-surface passivation film 24 and/or the anti-reflection film 26 may be formed of various materials. In one example, the back-surface passivation film 40, the front-surface passivation film 24 and/or the anti-reflection film 26 may be formed of a single film or multiple films in the form of a combination of two or more films selected from the group consisting of a silicon nitride film, a silicon nitride film containing hydrogen, a silicon oxide film, a silicon oxide nitride film, an aluminum oxide film, a silicon carbide film, and MgF2, ZnS, TiO2, and CeO2 films. In one example, the front-surface passivation film 24 may be a silicon oxide film formed over the semiconductor substrate 10, and the anti-reflection film 26 may have a structure in which a silicon nitride film and a silicon carbide film are sequentially stacked one above another. In addition, in one example, the back-surface passivation film 40 may have a structure in which a silicon nitride film and a silicon carbide film are sequentially stacked one above another. However, the embodiments of the present invention are not limited thereto, and the back-surface passivation film 40 may of course include various materials.
In one example, in the present embodiment, the front-surface passivation film 24, the back-surface passivation film 40, and/or the anti-reflection film 26 may include no dopant or the like, in order to achieve excellent insulation and passivation properties.
The electrodes 42 and 44, disposed on the back surface of the semiconductor substrate 10, include the first electrode 42, which is electrically and physically connected to the first conductive area 32, and the second electrode 44, which is electrically and physically connected to the second conductive area 34.
At this time, the first electrode 42 is connected to the first conductive area 32 through the opening 402 in the back-surface passivation film 40, and the second electrode 44 is connected to the second conductive area 34 through the opening 404 in the back-surface passivation film 40. The first and second electrodes 42 and 44 may include various metal materials. In one example, the first and second electrodes 42 and 44 may be formed of metals, and may be formed to come into contact with the first and second conductive areas 32 and 34 respectively.
Hereinafter, the plan shape of the first conductive area 32, the second conductive area 34, the barrier area 36, and the first and second electrodes 42 and 44 will be described in detail with reference to
Referring to
At this time, the first conductive area 32 may be wider than the second conductive area 34. In one example, the areas of the first conductive area 32 and the second conductive area may be adjusted by providing the first and second conductive areas 32 and 34 with different widths. That is, the width W1 of the first conductive area 32 may be greater than the width W2 of the second conductive area 34. This illustrates the instance where the first conductive area 32 functions as an emitter area. When the second conductive area 34 functions as an emitter area, the second conductive area 34 may be larger or wider than the first conductive area 32.
In addition, the first electrode 42 may be formed in a stripe shape so as to correspond to the first conductive area 32, and the second electrode 44 may be formed in a stripe shape so as to correspond to the second conductive area 34. The respective openings (see reference numerals 402 and 404 in
When light is introduced into the solar cell 100 according to the present embodiment, electrons and holes are produced via photoelectric conversion at the pn junction formed between the base area 110 and the first conductive area 32, and the produced electrons and holes move to the first conductive area 32 and the second conductive area 34 via tunneling through the protective-film layer 20, and thereafter move to the first and second electrodes 42 and 44. Thereby, electricity is generated.
In the solar cell 100 having a back-surface electrode structure in which the electrodes 42 and 44 are formed on the back surface of the semiconductor substrate 10 and no electrode is formed on the front surface of the semiconductor substrate 10, shading loss may be minimized on the front surface of the semiconductor substrate 10. Thus, the efficiency of the solar cell 100 may be improved.
In addition, because the first and second conductive areas 32 and 34 are formed over the semiconductor substrate 10 with the protective-film layer 20 interposed therebetween, the first and second conductive areas 32 and 34 are formed separately from the semiconductor substrate 10. As such, loss due to recombination may be less than that when a doped area formed by doping an area of the semiconductor substrate 10 with a dopant is used as a conductive area.
In the present embodiment, the first conductive area 32 includes the first portion 321, which is located over the protective-film layer 20 and has a first crystal grain size, and the second portion 322, which is located over the first portion 321 and spaced apart from the protective-film layer 20 and has a second crystal grain size, which is greater than the first crystal grain size. Here, the crystal grain size may mean an average crystal grain size. In addition, in the present embodiment, the second conductive area 34 includes a first portion 341, which is located over the protective-film layer 20 and has a first crystal grain size, and a second portion 342, which is located over the first portion 341 and spaced apart from the protective-film layer 20 and has a second crystal grain size, which is greater than the first crystal grain size. Likewise, the barrier area 36 includes a first portion 361, which is located over the protective-film layer 20 and has a first crystal grain size, and a second portion 362, which is located over the first portion 341 and spaced apart from the protective-film layer 20 and has a second crystal grain size, which is greater than the first crystal grain size. That is, in the present embodiment, a first portion 301 of the semiconductor layer 30 may include the first portion 321 of the first conductive area 32, the first portion 341 of the second conductive area 34, and the first portion 361 of the barrier area 36, and a second portion 302 of the semiconductor layer 30 may include the second portion 322 of the first conductive area 32, the second portion 342 of the second conductive area 34, and the second portion 362 of the barrier area 36.
When the second portions 322 and 342 of the first and second conductive areas 32 and 34 have a crystal grain size greater than the first portions 321 and 341 located over the protective-film layer 20, a large amount of dopant may be located in the second portions 322 and 342 because the diffusion rate of a dopant through the second portions 322 and 342 is low, and a relatively small amount of dopant is located in the first portions 321 and 341 compared to the second portions 322 and 342. Thus, because a relatively large amount of dopant may be located in the second portions 332 and 342 of the first and second conductive areas 32 and 34, which are located close to (e.g. in contact with) the electrodes 42 and 44, the surface concentration of the first and second conductive areas 32 and 34 may be increased, and consequently, the contact resistance between the first and second conductive areas 32 and 34 and the electrodes 42 and 44 may be reduced. In addition, because a relatively small amount of dopant is located in the first portions 321 and 341 of the first and second conductive areas 32 and 34, which are close to the protective-film layer 20, the amount of dopant to diffuse to the protective-film layer 20 or nearby portions of the semiconductor substrate 10 may be reduced, and excellent passivation properties may be maintained.
On the other hand, when the entire portion of the first and second conductive areas 32 and 34 has substantially the same crystal grain size, it may be difficult to improve all of the contact resistance, passivation properties, and carrier mobility by adjusting a doping profile. For example, when the first and second conductive areas 32 and 34 include only the first portions 321 and 341, having a relatively small first crystal grain size, without the second portions 322 and 342, a grain boundary may be large, and thus the carrier mobility may not be high. In another example, when the first and second conductive areas 32 and 34 include only the second portions 322 and 342, having a relatively large second crystal grain size, without the first portions 321 and 341, the diffusion rate of a dopant may be reduced and it may be difficult for the first and second conductive areas 32 and 34 to be doped with a sufficient concentration. Thereby, the contact resistance between the first and second conductive areas 32 and 34 and the electrodes 42 and 44 may be increased. In addition, when the amount of dopant is increased, which is another method to increase carrier mobility, an excessive amount of dopant may diffuse to the protective-film layer 20 or to nearby portions of the semiconductor substrate 10, thus causing deterioration in passivation.
In one example, the first crystal grain size of the first portion 301 may range from 10 nm to 1 μm and the second crystal grain size of the second portion 302, which is greater than the first crystal grain size, may range from 20 nm to 600 μm. At this time, the first or second crystal grain size may be the larger one of the average crystal grain size when viewed in the thickness direction and the average crystal grain size when viewed in plan. When the first crystal grain size is below 10 nm, a dopant may easily diffuse through the first portion 321, causing deterioration in passivation at the interface of the protective-film layer 20 and it may be difficult to form the first portion 321 having such a crystal grain size. On the other hand, when the first crystal grain size is above 1 μm, a dopant may not sufficiently diffuse to the first portion 321, causing an increase in resistance. When the second crystal grain size is below 20 nm, this may be too small in comparison with the crystal grain size of the first portion 301, and therefore it may be difficult to realize the above-described effects of the first portion 301 and the second portion 302. When the second crystal grain size exceeds 600 μm, it may be difficult to form the first and second conductive areas 32 and 34 having a desired doping concentration and the process of forming the first and second conductive areas 32 and 34 may be somewhat difficult because almost no dopant may diffuse.
More specifically, the first crystal grain size of the first portion 301 may range from 20 nm to 50 nm and the second crystal grain size of the second portion 302 may range from 200 nm to 500 nm (e.g. 200 nm to 300 nm). With these first and second crystal grain sizes, the above-described effects of the first portion 301 and the second portion 302 may be effectively realized.
Alternatively, a difference between the crystal grain size of the first portion 301 and the crystal grain size of the second portion 302 may range from 10 nm to 600 μm. When the difference between the crystal grain sizes is below 10 nm, the above-described effects of the first portion 301 and the second portion 302 may not be sufficient. It may be difficult to form the second portion 302 so that the difference between the crystal grain sizes exceeds 600 μm. More specifically, the difference between the crystal grain size of the first portion 301 and the crystal grain size of the second portion 302 may range from 10 nm to 500 nm (e.g. 100 nm to 300 nm). Within this range, the above-described effects of the first portion 301 and the second portion 302 may be effectively realized.
Alternatively, the ratio of the first crystal grain size of the first portion 301 to the second crystal grain size of the second portion 302 may range from 1:1.5 to 1:100 (e.g. 1:2 to 1:40, and in one example, 1:6 to 1:20). When the aforementioned ratio is below 1:1.5, the above-described effects obtained by the first portion 301 and the second portion 302 may not be sufficient. The aforementioned ratio may be difficult to set greater than 1:100 due to processing properties, and the ratio of 1:100 may make it difficult for the first and second conductive areas 32 and 34 to have the desired doping concentration. When the aforementioned ratio ranges from 1:2 to 1:40, the first portion 301 and the second portion 302 may sufficiently realize the effects attributable to the difference between the crystal grain sizes and may be easily formed in the corresponding process. In addition, when the aforementioned ratio ranges from 1:6 to 1:20, the effects attributable to the difference between the crystal grain sizes may be maximized and easy manufacture may be ensured due to processing properties.
However, the embodiments of the present invention are not limited to the above-described numerical ranges, and various other alterations are possible.
In the present embodiment, the first and second conductive areas 32 and 34 may include the first portions 321 and 341, which are formed in contact with the protective-film layer 20, and the second portions 322 and 342, which are formed in contact with the electrodes 42 and 44. Because the first and second conductive areas 32 and 34 include only two layers including the first and second portions 321 and 341 and 322 and 342, the structure of the first and second conductive areas 32 and 34 may be simplified. However, the embodiments of the present invention are not limited thereto, and the first and second conductive areas 32 and 34 may further include another layer excluding the first and second portions 321 and 341 and 322 and 342.
The thickness of the second portion 322 or 342 (or the second portion 302) relative to the thickness of the entire first or second conductive area 32 or 34 may range from 20% to 90%. When the relative thickness of the second portion is below 20%, the thickness of the second portion 322 or 342 may not be sufficient and there may be a limitation on a reduction in the contact resistance between the first or second conductive area 32 or 34 and the electrode 42 or 44. On the other hand, when the relative thickness of the second portion exceeds 90%, the thickness of the first portion 321 or 342 is too small to achieve sufficient doping, and thus the first or second conductive area 32 or 34 may have high resistance in a portion thereof that is in contact with the protective-film layer 20.
In one example, the thickness of the second portion 322 or 342 may be equal to or greater than the thickness of the first portion 321 or 341. In particular, the thickness of the second portion 322 or 342 may be greater than the thickness of the first portion 321 or 341. Thus, the thickness of the second portion 322 or 342 relative to the thickness of the entire first or second conductive area 32 or 34 may range from 50% to 90% (more specifically, may be greater than 50% and equal to or less than 90%). This is because carrier mobility may be increased and electrical properties may be improved when the relative thickness of the second portion 322 or 342 is increased.
In the present embodiment, the barrier area 36 may include the first portion 361 and the second portion 362, and the first portion 361 having a smaller crystal grain size may be located close to or in contact with the protective-film layer 20. Thus, although the portion of the barrier 36 close to the protective-film layer 20 is a portion having high carrier mobility, it may effectively prevent carriers from moving from the side surfaces of the first and second conductive areas 32 and 34 by way of the barrier area 36 in the corresponding portion. The barrier area 36 including the first portion 361 and the second portion 362 may be easily formed by undoping a portion of the semiconductor layer 30 when the first and second conductive areas 32 and 34 are formed by doping the semiconductor layer 30. However, the embodiments of the present invention are not limited thereto, and the barrier area 36 including the first portion 361 and the second portion 362 may be formed via various methods.
The present specification discloses the instance where the first portion 321 of the first conductive area 32, the first portion 341 of the second conductive area 34, and the first portion 361 of the barrier area 36, which constitute the first portion 301, have the same first crystal grain size, and the second portion 322 of the first conductive area 32, the second portion 342 of the second conductive area 34, and the second portion 362 of the barrier area 36, which constitute the second portion 302, have the same second crystal grain size. This is because the first conductive area 32, the second conductive area 34 and the barrier area 36 are included in the semiconductor layer 30 that is successively formed in the same process, and therefore, the crystal grain size is determined from the average crystal grain size of the entire portion. However, the embodiments of the present invention are not limited thereto. Thus, the first portion 321 of the first conductive area 32, the first portion 341 of the second conductive area 34, and the first portion 361 of the barrier area 36 may have different crystal grain sizes, and the second portion 322 of the first conductive area 32, the second portion 342 of the second conductive area 34, and the second portion 362 of the barrier area 36 may have different crystal grain sizes. Even in this instance, the second portion 322 of the first conductive area 32 may have a crystal grain size greater than the first portion 321, the second portion 342 of the second conductive area 34 may have a crystal grain size greater than the first portion 341, and the second portion 362 of the barrier area 36 may have a crystal grain size greater than the first portion 361.
The first and second conductive areas 32 and 34 and/or the barrier area 36 having the above-described structures may be formed via various methods.
In one example, when forming the first and second conductive areas 32 and 34 of the semiconductor layer 30, a semiconductor layer including a first semiconductor portion (see reference numeral 310 in
Alternatively, after a semiconductor layer including a first semiconductor portion (see reference numeral 310 in
First, as illustrated in
Subsequently, as illustrated in
At this time, in the present embodiment, as illustrated in
At this time, the step of forming the first semiconductor portion 310 and the step of forming the second semiconductor portion 320 may be performed as in-situ processes, which are successively performed in the same equipment merely by changing process conditions. This may simplify the manufacturing process. In addition, when the semiconductor substrate is pulled out of the equipment during the process of forming the first semiconductor portion 310 and the process of forming the second semiconductor portion 320, the semiconductor layer 300 may be contaminated or oxidized by a foreign substance, thus causing an oxide layer to be formed between the first semiconductor portion 310 and the second semiconductor portion 320. In the present embodiment, because the first semiconductor portion 310 and the second semiconductor portion 320, which have different crystal grain sizes, are successively formed in the same equipment, any problem that may occur when the semiconductor layer 300 is exposed to the outside during the formation process thereof may be prevented.
In one example, in the present embodiment, the intrinsic semiconductor layer 300 may be formed via low-pressure chemical vapor deposition. That is, gas (e.g. silane gas) including a semiconductor material, which constitutes the semiconductor layer 300, may be included. In the present embodiment, because the semiconductor layer 300 is deposited to exhibit its intrinsic properties, a gas atmosphere may include only gas including a semiconductor material. Thus, the gas to be supplied may be simplified and the purity of the semiconductor layer 300 that is formed may be improved. However, the embodiments of the present invention are not limited thereto, and another gas may be further used in order to facilitate the deposition of the semiconductor layer 300 or to improve the properties of the semiconductor layer 300. In addition, when a first conductive dopant and a second conductive dopant are doped together in the deposition process of the semiconductor layer 300, gas including the first or second conductive dopant (e.g. B2H6 or PH3) may be further included.
At this time, the first semiconductor portion 310 and the second semiconductor portion 320 may have different crystal grain sizes attributable to different processing temperatures thereof. In one example, the processing temperature in the process of forming the second semiconductor portion 320 may be higher than the processing temperature in the process of forming the first semiconductor portion 310. The high processing temperature may facilitate the growth of crystal grains in the second semiconductor portion 320, thus causing the second semiconductor layer 320 to have a relatively large second crystal grain size. In one example, the processing temperature in the process of forming the second semiconductor portion 320 may be about 10° C. to 300° C. higher than the processing temperature in the process of forming the first semiconductor portion 310. When the temperature difference is below 10° C., differentiating the crystal grain sizes may be limited due to the insufficient temperature difference. In addition, when the temperature difference exceeds 300° C., for example, the time and cost taken to change the temperature are increased and the properties of the first or second semiconductor portion 310 or 320 may be deteriorated.
Alternatively, the first semiconductor portion 310 and the second semiconductor portion 320 may be made to have different crystal grain sizes by differentiating, for example, the amount and kind of raw material gas that is used. In one example, the amount of gas including a semiconductor material in the process of forming the second semiconductor portion 320 may be greater than the amount of gas including a semiconductor material in the process of forming the first semiconductor portion 310. Thus, the relatively large amount of gas including a semiconductor material may facilitate the growth of crystal grains in the second semiconductor portion 320, thus causing the second semiconductor portion 320 to have a relatively large second crystal grain size. Alternatively, the second crystal grain size of the second semiconductor portion 320 may be increased by additionally introducing, for example, another gas including a semiconductor material, in addition to the raw material gas.
Subsequently, as illustrated in
The first doping layer 324 may include a first conductive dopant and may have a pattern corresponding to the first conductive area 32. At this time, the undoped layer 326, which has the same pattern as the first doping layer 324, may be disposed over the first doping layer 324. The first doping layer 324 and the undoped layer 326 are first wholly formed and then patterned. In one example, required portions of the first doping layer 324 and the undoped layer 326 may be removed via etching using an etching paste or an etching mask. However, the embodiments of the present invention are not limited thereto, and the first doping layer 324 and the undoped layer 326 each having a pattern may be formed.
The first doping layer 324 includes a first conductive dopant and serves to supply the first conductive dopant to the semiconductor layer 300 via diffusion in a doping process (this process is illustrated in
The first doping layer 324 may be formed of any of various materials including the first conductive dopant. In addition, the undoped layer 326 may be formed of any of various materials including no first and second conductive dopants. In one example, the first doping layer 324 may include boron silicate glass (BSG), and the undoped layer 326 may include undoped silicate glass (USG). However, the embodiments of the present invention are not limited thereto, and the first doping layer 324 and the undoped layer 326 may include various other materials. In one example, when the first doping layer 324 is of an n-type, the first doping layer 324 may include phosphorous silicate glass (PSG).
The first doping layer 324 and the undoped layer 326 may be formed via various methods, such as, for example, deposition. At this time, in the present embodiment, the first doping layer 324 and the undoped layer 326 may be formed via in-situ processes, which are successively performed in the same equipment. When the first doping layer 324 is formed of boron silicate glass and the undoped layer 326 is formed of undoped silicate glass as described above, deposition is performed to form the first doping layer 324 in the state in which gas including the first conductive dopant is supplied, and after which the supply of the gas including the first conductive dopant is interrupted so as to form the undoped layer 326. Through this change in gas, the first doping layer 324 and the undoped layer 326 may be successively formed, resulting in a simplified process.
The mask layer 328 serves to prevent the dopant from diffusing to the portion on which the mask layer 328 is formed. The mask layer 328 may be formed of any of various undoped materials, which may include no first and second conductive dopants and may prevent diffusion of a dopant. In one example, the mask layer 328 may be formed of a silicon carbide (SiC) film. The silicon carbide film may effectively prevent the diffusion of a dopant. In addition, the silicon carbide film may be easily processed to have a desired shape using a laser, and may be easily removed by an etching solution (e.g. an acid solution, for example, diluted hydrofluoric acid (HF)) after the doping process.
The mask layer 328 may be formed to cover the first doping layer 324 and the undoped layer 326 and to expose a portion corresponding to the second conductive area 34. The mask layer 328 may be patterned to have a desired pattern after it is formed throughout the first doping layer 324, the undoped layer 326, and the back surface of the semiconductor substrate 10. In one example, a desired portion of the mask layer 328 may be removed via laser ablation. When the mask layer 328 is patterned using a laser, an opening corresponding to the portion, on which the second conductive area 34 will be formed, may be formed to have a desired width and interval. However, the embodiments of the present invention are not limited thereto, and the mask layer 328 may be formed such that a pattern has already been formed.
In the present embodiment, the mask layer 328 may include a barrier portion B, which is provided around the first doping layer 324 and the undoped layer 326 so as to cover a portion of the opening formed in the first doping layer 324 and the undoped layer 326. In one example, the barrier portion B may be formed on the edge of the opening formed in the first doping layer 324 so as to extend along the edge of the first doping layer 324. Thus, the area of the opening in the mask layer 328 may be smaller than the area of the opening in the first doping layer 324 and the undoped layer 326. The barrier portion B is used to form the barrier area (see reference numeral 36 in
Subsequently, as illustrated in
More specifically, a first conductive dopant located in the first doping layer 324 diffuses to the semiconductor layer 300, thereby forming the first conductive area 32. In addition, a second conductive dopant diffuses to the semiconductor layer 300 through the opening in the mask layer 328 from the back surface side of the semiconductor substrate 10 via thermal diffusion, thereby forming the second conductive area 34.
Accordingly, in the present embodiment, the first conductive area 32 is formed by doping the first conductive dopant using the first doping layer 324, and the second conductive area 34 is formed via thermal diffusion of the second conductive dopant using the gas including the second conductive dopant. Thereby, the first and second conductive areas 32 and 34 may be formed via a simplified process.
In addition, because the first conductive dopant and the second conductive dopant do not diffuse to a portion of the semiconductor layer 300 corresponding to the barrier portion B, the barrier area 36, which is formed of an intrinsic crystalline semiconductor, is located in the corresponding portion. Thereby, the semiconductor layer 30 including the barrier area 36 may be formed via a simplified process.
Although the present embodiment illustrates the instance where the second conductive area is formed via the thermal diffusion of the second conductive dopant, the embodiments of the present invention are not limited thereto.
In another example, after the mask layer 328 is formed, at least the opening in the mask layer 328 may be filled with a second doping layer (not illustrated) including a second conductive dopant. In one example, the second doping layer may be formed throughout the semiconductor layer 300 and the mask layer 328. In addition, the second doping layer may be formed of phosphorous silicate glass via plasma chemical vapor deposition. In this instance, thermal treatment causes the second conductive dopant included in the second doping layer to diffuse to the semiconductor layer 300 so as to form the second conductive area 34.
At this time, the front surface of the semiconductor substrate 10 may be subjected to texturing so as to form the front-surface field area 130. In one example, after the front surface of the semiconductor substrate 10 is subjected to texturing, thermal treatment to thermally diffuse the second conductive dopant may be performed so that the front-surface field area 130 and the second conductive area 34 are formed together. Alternatively, after the first and second conductive areas 32 and 34 are formed, the front surface of the semiconductor substrate 10 is subjected to texturing and then is doped with the second conductive dopant so as to form the front-surface field area 130. In this instance, the front-surface field area 130 may be formed via a process that is different from the doping process of the second conductive area 34 so as to precisely control the doping profile of the front-surface field area 130. At this time, when, for example, the protective-film layer 20 and the semiconductor layer 300 are also formed on the front surface of the semiconductor substrate 10, these layers may be removed during texturing.
Texturing on the front surface of the semiconductor substrate 10 may be performed via various methods. For example, texturing may be performed by dipping only a front-surface portion of the semiconductor substrate 10 in an alkali solution (e.g. a KOH solution). This process may advantageously reduce the processing time. Alternatively, only the front surface of the semiconductor substrate 10 may be subjected to texturing via, for example, reactive ion etching (RIE), which is a single-sided etching method. Through reactive ion etching, only a single surface may be easily etched and a texturing structure having uniform protrusions may be formed. However, the embodiments of the present invention are not limited thereto.
Subsequently, as illustrated in
The front-surface passivation film 24, the anti-reflection film 26 and/or the back-surface passivation film 40 may be formed via various methods, such as, for example, vacuum deposition, chemical vapor deposition, spin coating, screen printing, or spray coating. In addition, after the first doping layer 324, the undoped layer 326, and the mask layer 328 are removed, the front-surface passivation film 24, the anti-reflection film 26 and/or the back-surface passivation film 40 may be formed. Alternatively, the front-surface passivation film 24 and the anti-reflection film 26 may be formed before the removal of the first doping layer 324, the undoped layer 326, and the mask layer 328, and then, after the first doping layer 324, the undoped layer 326, and the mask layer 328 are removed, the back-surface passivation film 40 may be formed. Thus, the front-surface passivation film 24 and the anti-reflection film 26 may serve as a mask when the first doping layer 324, the undoped layer 326, and the mask layer 328 are removed, thereby preventing damage to the front surface of the semiconductor substrate 10 or deterioration in properties thereof.
Subsequently, as illustrated in
In one example, after the opening 402 and 404 are formed in the back-surface passivation film 40, an electrode layer may be formed over the back-surface passivation film 40 so that the openings 402 and 404 are filled with the electrode layer, thereby forming the first and second electrodes 42 and 44. The electrode layer may be formed via any of various methods, such as, for example, plating or deposition. At this time, the electrode layer may be completely formed and then patterned, or the patterned electrode layer may be formed. The patterning of the electrode layer may be performed via any of various known methods.
Alternatively, after paste for the formation of the first electrode and paste for the formation of the second electrode are respectively applied on the back-surface passivation film 40 via, for example, screen printing, fire-through phenomenon or laser firing contact may be used in order to form the first and second electrodes 42 and 44 having the above-described shape. In this instance, because the openings 402 and 404 are formed during the firing process, no process of forming the openings 402 and 404 is added.
According to the present embodiment, the solar cell 100 having excellent effects may be manufactured via a simplified process and both the efficiency and productivity of the solar cell 100 may be improved. More specifically, the first and second conductive areas 32 and 34 each including the first portion 321 or 341 and the second portion 322 or 342 may be formed by simply differentiating process conditions. Because the first portion 321 or 341 and the second portion 322 or 342 may be formed via in-situ processes that are successively performed in the same equipment, the process may be effectively simplified.
Hereinafter, a method of manufacturing a solar cell according to another embodiment of the present invention will be described in detail with reference to
As illustrated in
Subsequently, as illustrated in
By adjusting, for example, the output, energy density, frequency, and pulse of the laser 330 in consideration of, for example, the thickness and properties of the first semiconductor portion 310, the second semiconductor portion 320 may be formed in the state in which a portion of the first semiconductor portion 310 remains close to the protective-film layer 20. The laser 330 may be a short-wave laser. Because the first semiconductor portion 310 easily absorbs a short-wave laser, only a portion of the first semiconductor portion 310 may be easily crystallized. Thus, the second semiconductor portion 320 may be formed so that the first semiconductor portion 310 remains. In one example, the laser 330 may be an ultraviolet (UV) laser or a green laser.
At this time, as illustrated in
According to the present embodiment, because some of the laser 330 is absorbed by the laser absorption film 320a, a portion of the first semiconductor portion 310 that is close to the protective-film layer 20 may stably remain so that the first portions 321, 341 and 361 are formed. In addition, the thickness of the first portions 321, 341 and 361 may be easily adjusted via adjustment in the thickness of the laser absorption film 320a.
However, the laser absorption film 320a may be not necessary, and the first semiconductor portion 310 may be directly irradiated with the laser 330 without the laser absorption film 320a. In this instance, the process of forming the laser absorption film 320a may be omitted, resulting in a simplified process.
Subsequently, the solar cell 100 may be manufactured via the implementation of the processes illustrated in
With this manufacturing method, the second semiconductor portion 320 may be simply formed using the laser 330. In particular, because a portion in the plane to be irradiated with the laser 330 may be adjusted, a solar cell having the structure illustrated in
Hereinafter, a method of manufacturing a solar cell according to another embodiment of the present invention will be described in detail with reference to
As illustrated in
Subsequently, as illustrated in
Subsequently, as illustrated in
The second doping layer 329 may include a second conductive dopant, and may be formed throughout the semiconductor layer 300, the doping layer 324, the undoped layer 326, and the mask layer 328. The second doping layer 329 including the second conductive dopant serves to supply the second conductive dopant to the semiconductor layer 300 via diffusion in a doping process (i.e. the process illustrated in
The second doping layer 329 may be formed of any of various materials including the second conductive dopant. In one example, the second doping layer 329 may include phosphorous silicate glass (PSG). However, the embodiments of the present invention are not limited thereto, and the second doping layer 329 may include any of various other materials. In one example, when the second doping layer 329 is of a p-type, the second doping layer 329 may be formed of boron silicate glass (PSG). The second doping layer 329 may be formed of any of various methods, such as, for example, deposition.
In the above description and the drawings, the first doping layer 324 has a pattern corresponding to the first conductive area 32, the undoped layer 326 and the mask layer 328 are disposed over the first doping layer 324, and the second doping layer 329 is formed throughout the first doping layer 324, the undoped layer 326 and the mask layer 328. However, the embodiments of the present invention are not limited thereto. In one example, the second doping layer 329 may have a pattern corresponding to the second conductive area 34, the undoped layer 326 and the mask layer 328 may be disposed over the second doping layer 329, and the first doping layer 324 may be formed throughout the second doping layer 329, the undoped layer 326 and the mask layer 328. Alternatively, the first doping layer 324 and the second doping layer 329 may respectively have patterns corresponding to the first conductive area 32 and the second conductive area 34.
Subsequently, as illustrated in
According to the present embodiment, because some of the laser 330 is absorbed by, for example, the first or second doping layer 324 or 329, a portion of the first semiconductor portion 310 that is close to the protective-film layer 20 may stably remain to form the first portions 321, 341 and 361. In addition, the thickness of the first portions 321, 341 and 361 may be easily adjusted via adjustment in the thickness of the first or second doping layer 324 or 329. In addition, when the first or second doping layer 324 or 329 required in the doping process is used as a laser absorption layer, additional processes of forming and removing the laser absorption film may be omitted.
In addition, the front surface of the semiconductor substrate 10 may be subjected to texturing to form the front-surface field area 130. This may be understood from the description with reference to
Subsequently, the solar cell 100 may be manufactured via the implementation of the processes illustrated in
In the present embodiment, thermal treatment for doping using the laser 330 and thermal treatment for the formation of the second portions 322, 342 and 362 having a second crystal grain size may be performed at the same time via a single process. Thereby, the doping process and the process of forming the second portions 322 and 342 may be performed in a simplified manner, resulting in a simplified process.
Hereinafter, solar cells according to other embodiments of the present invention will be described in detail with reference to
Referring to
In addition, the barrier area 36 may include the first portion 361 having the first crystal grain size. Thus, the first portion 361 of the barrier area 36 may be thicker than the first portion 321 of the first conductive area 32, and the thickness of the first portion 361 may be the same as or similar to (e.g. with a difference within 10%) the thickness of the first conductive area 32. In addition, the entire barrier area 36 may have the first crystal grain size and the first crystal grain size of the barrier area 36 may be substantially the same as or similar to (e.g. with a difference within 10%) the first crystal grain size of the first portion 321 of the first conductive area 32, and may be smaller than the second crystal grain size of the second portion 322 of the first conductive area 32.
The solar cell 100 may be easily manufactured by irradiating only a portion corresponding to the first conductive area 32 with the laser 330 in the process of
At this time, the first conductive area 32 including the first portion 321 and the second portion 322 may be of a p-type. When the first conductive area 32 is of a p-type, a dopant may include, for example, boron (B). This is because boron has a very small element size and thus more easily diffuses to the protective-film layer 20 and the semiconductor substrate 10 than, for example, n-type phosphor (P), thus causing deterioration in properties. In consideration of this, the first conductive area 32 is formed to have the first portion 321 and the second portion 322.
However, the embodiments of the present invention are not limited thereto. The first conductive area 32 may be of an n-type. In addition, in some embodiments, the barrier area 36 may include only the first portion 361, or may include the first portion 361 and the second portion 362.
Referring to
At this time, the first conductive area 32 may be formed as a semiconductor layer, which is separate from the semiconductor substrate 10, and may include the first portion 321 and the second portion 322. The above description related to the first portion 321 and the second portion 322 may be directly applied thereto. In addition, the second conductive area 34 may be formed as a doped area, which constitutes a portion of the semiconductor substrate 10. That is, the second conductive area 34 may be formed by doping a portion of the semiconductor substrate 10 with a dopant. The second conductive area 34 may be of a different conductive type from the base area 110, or may be of the same conductive type as the base area 110, but may have a higher doping concentration than the base area 110.
In one example, in the present embodiment, the second conductive area 34 may be of the same conductive type as the base area 110, but may have a higher doping concentration than the base area 110. Thereby, the first conductive area 34, which is of a different conductive type from the base area 110 and functions as an emitter area, may be formed separately from the semiconductor substrate 10 with the protective-film layer 20 interposed therebetween, which may improve passivation properties. In addition, because the first conductive area 32 configured as a separate semiconductor layer is disposed on the back surface and the second conductive area 34 configured as a doped area is disposed on the front surface, it is possible to prevent, for example, light introduced into the front surface from being absorbed by a separate semiconductor layer. This may minimize shading loss.
As described above, only one of the first and second conductive areas 32 and 34 may include the first portion 321 and the second portion 322. Although
Referring to
At this time, the first conductive area 32 and the second conductive area 34 may be formed of semiconductor layers 30a and 30b, which are separated from the semiconductor substrate 10.
However, the embodiments of the present invention are not limited thereto, and at least one of the first and second electrodes 42 and 44, as illustrated in
Hereinafter, the present invention will be described in more detail with reference to manufacturing examples of the present invention. The following manufacturing examples are merely given by way of example, and the embodiments of the present invention are not limited thereto.
A protective-film layer formed of a silicon oxide film was formed on one surface of an n-type monocrystalline semiconductor substrate. A first semiconductor portion, which includes polycrystalline silicon and has a first crystal grain size, was formed over the protective-film layer via low-pressure chemical vapor deposition. A second semiconductor portion was formed by irradiating an intrinsic semiconductor layer with a laser so as to grow crystal grains in a portion of the intrinsic semiconductor layer that is spaced apart from the protective-film layer while remaining the first semiconductor portion in a portion of the semiconductor layer that is close to the protective-film layer. At this time, the first crystal grain size was 50 nm, the second crystal grain size was 250 nm, the difference between the first crystal grain size and the second crystal grain size was 200 nm, and the ratio of the second crystal grain size to the first crystal grain size was 5:1. In addition, an area of the first and second semiconductor portions was doped with a p-type dopant and another area was doped with an n-type dopant so that a semiconductor layer including a first conductive area and a second conductive area each including a first portion and a second portion was formed, whereby a first solar cell was manufactured. The thickness of the second portion relative to the thickness of the entire conductive area was 50%. In addition, second, third and fourth solar cells were manufactured using doping concentrations in the first and second conductive areas that were different from that of the first solar cell of Manufacturing Example 1, but were otherwise manufactured in the same manufacturing method as the first solar cell of Manufacturing Example 1.
A first comparative solar cell was manufactured via the same method as the solar cell of Manufacturing Example 1 except that the laser irradiation process of forming the second semiconductor portion was not performed, and thus the semiconductor layer including the first and second conductive areas includes only the first portion, all of which has the first crystal grain size. In addition, second and third comparative solar cells were manufactured using doping concentrations in the first and second conductive areas that were different from that of the first comparative solar cell, but were otherwise manufactured in the same manufacturing method as the first comparative solar cell.
The cross-sectional photograph of the first solar cell of Manufacturing Example 1 is illustrated in
Referring to
Referring to
A solar cell was manufactured via the same method as the first solar cell of Manufacturing Example 1 except that the first crystal grain size was 50 nm, the second crystal grain size was 58 nm, the difference between the first crystal grain size and the second crystal grain size was 8 nm, and the ratio of the second crystal grain size to the first crystal grain size was 1.16:1.
A solar cell was manufactured via the same method as the first solar cell of Manufacturing Example 1 except that the thickness of the second portion relative to the thickness of the entire conductive area was 10%.
A solar cell was manufactured via the same method as the first solar cell of Manufacturing Example 1 except that the thickness of the second portion relative to the thickness of the entire conductive area was 83%.
A solar cell was manufactured via the same method as the first solar cell of Manufacturing Example 1 except that the thickness of the second portion relative to the thickness of the entire conductive area was 88%.
The relative values of the carrier mobility in the first conductive areas of the first solar cell according to Manufacturing Example 1, the first comparative solar cell according to Comparative Example 1, and the solar cells according to Comparative Example 2 and Manufacturing Examples 2 to 4 are illustrated in
Referring to
The above described features, configurations, effects, and the like are included in at least one of the embodiments of the present invention, and should not be limited to only one embodiment. In addition, the features, configurations, effects, and the like as illustrated in each embodiment may be implemented with regard to other embodiments as they are combined with one another or modified by those skilled in the art. Thus, content related to these combinations and modifications should be construed as including in the scope and spirit of the invention as disclosed in the accompanying claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2016-0003753 | Jan 2016 | KR | national |
