Patent Application
20120325309
The present invention relates to a back contact type solar cell including an n-type semiconductor region and a p-type semiconductor region disposed on a back surface of a semiconductor substrate.
Solar cells are expected to be new energy sources, because the solar cells can convert clean and abundantly supplied solar light energy into electrical energy directly.
There has conventionally been known a solar cell in which an n-type conductivity semiconductor layer and a p-type conductivity semiconductor layer are formed on a back surface of a semiconductor substrate, i.e., a back contact type solar cell. Such a solar cell is disclosed in Japanese Patent Application Publication No. Hei 11-112011, for example. On these semiconductor layers, electrodes are formed to collect photo-generated carriers generated by reception of light.
In a back contact type solar cell, since both an n-type semiconductor layer and a p-type semiconductor layer are formed on the back surface side of a semiconductor substrate, semiconductor layers and electrodes of different conductivity types are likely to come into contact with each other, or positive and negative electrodes are likely to come into contact with each other. A short circuit is caused when such a contact occurs. For this reason, there is used a method in which electrodes are formed using metal masks or a method in which unnecessary semiconductor layers and unnecessary electrode layers are removed after formation of resists by use of screen printing.
Patent Document 1: Japanese Patent Application Publication No. Hei 11-112011
When electrodes are formed or semiconductor layers are removed using the above methods, however, scratches may occur on the semiconductor layers. Specifically, when a metal mask used for electrode formation or a screen pushed by a squeegee in screen printing comes into contact with a semiconductor layer, scratches may occur on the semiconductor layer. Thin film semiconductor layers have been widely used in recent years. In the case of thin film semiconductor layers, scratches may reach semiconductor substrates. Moreover, scratches may occur not only in formation of electrodes but also in handling of solar cells. When scratches occur at a junction portion between a semiconductor layer and a semiconductor substrate, a function of the junction portion deteriorates. When the junction portion having scratches is a p-n junction, conversion efficiency may deteriorate. When a semiconductor layer serving as a passivation layer is provided, the junction portion having scratches cannot prevent recombination of carriers.
The present invention has been made in view of the above circumstances, and an objective thereof is to provide a solar cell capable of preventing scratches from occurring on a junction portion between a semiconductor layer and a semiconductor substrate, and capable of suppressing deterioration of conversion efficiency.
To solve the above-described problem, a solar cell according to the aspect of the present invention is a solar cell comprising a semiconductor substrate having a light receiving surface and a back surface, a first semiconductor region of a first conductivity type and a second semiconductor layer of a second conductivity type, both being disposed on the back surface of the semiconductor substrate, wherein the semiconductor substrate includes a plurality of protruding portions on the back surface, the first semiconductor region is provided in a surface of each of the protruding portions, the second semiconductor layer is provided on the semiconductor substrate located between one protruding portion and another protruding portion adjacent to the one protruding portion among the plurality of protruding portions, and the one protruding portion and the other protruding portion constitute a recessed portion whose bottom portion is formed by the second semiconductor layer.
In the solar cell according to the aspect of the present invention, the second semiconductor layer is formed on the semiconductor substrate located between the one protruding portion and the other protruding portion adjacent to the one protruding portion, and each protruding portion is higher than the second semiconductor layer formed on the semiconductor substrate. For this reason, a metal mask or a screen is less likely to come into contact with the second semiconductor layer formed on the semiconductor substrate located between the one protruding portion and the other protruding portion because the one protruding portion and the other protruding portion block the metal mask or the screen. The same things can be said in handling of solar cells also. For this reason, scratches can be prevented from occurring on the junction portion between the second semiconductor layer and the semiconductor substrate. Moreover, scratches hardly occur on the junction portions between the semiconductor substrate and the first semiconductor regions because the first semiconductor regions are in the same crystal state as the semiconductor substrate.
The depth of the recessed portion is preferably 0.4 μm or more.
An interval between the one protruding portion and the other protruding portion adjacent to the one protruding portion is preferably 5 mm or less.
The semiconductor substrate is preferably of the first conductivity type.
The second semiconductor layer is preferably formed on the first semiconductor region as well.
A solar cell manufacturing method for manufacturing a solar cell according to the aspect of the present invention is a solar cell manufacturing method for manufacturing a solar cell comprising a semiconductor substrate having a light receiving surface and a back surface, a first semiconductor region of a first conductivity type and a second semiconductor layer of a second conductivity type, both being disposed on the back surface of the semiconductor substrate, wherein the method comprises: a step S1 of forming the first semiconductor region of the first conductivity type on the back surface of the semiconductor substrate having the light receiving surface and the back surface; and a step S2 of forming the second semiconductor layer of the second conductivity type on the back surface, the step S1 includes a step of forming the first semiconductor region in a surface of the semiconductor substrate by heating the semiconductor substrate and introducing impurities into the semiconductor substrate, the step S2 includes: a step S21 of exposing part of the semiconductor substrate by removing the first semiconductor region at intervals; and a step S22 of forming the second semiconductor layer on the semiconductor substrate which is exposed by the removal of the first semiconductor region, the first semiconductor region is formed in at least a surface of each of a plurality of protruding portions which are not removed but remain, and the second semiconductor layer forms a bottom portion of a recessed portion formed by one protruding portion and another protruding portion adjacent to the one protruding portion among the plurality of protruding portions.
In the step S22, the second semiconductor layer is formed on the semiconductor substrate and is also formed on the first semiconductor region preferably.
The present invention can provide a back contact type solar cell in which deterioration of conversion efficiency is suppressed.
A solar cell according to an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, identical or similar reference numerals are assigned to identical or similar components. The drawings are schematic, thus it should be noted that the dimensions are not shown to scale. Accordingly, specific dimensions should be recognized in consideration of the following description. Also, there are inevitably included some portions of the drawings between which a dimensional relationship and/or a scale are inconsistent.
(1) Schematic Configuration of Solar Cell 1
Description will be given of a schematic configuration of a solar cell 1 according to an embodiment of the present invention with reference to
The solar cell 1 includes a first conductivity type semiconductor substrate 10, first semiconductor regions 20, a second semiconductor layer 30, electrodes 40n, electrodes 40p, a collector electrode 70n, and a collector electrode 70p.
The semiconductor substrate 10 includes a light receiving surface which receives light, and a back surface which is provided on an opposite side to the light receiving surface. When receiving light on the light receiving surface, the semiconductor substrate 10 generates carriers (electrons and holes). In the solar cell 1 according to the embodiment, the semiconductor substrate 10 is made of n-type single-crystalline silicon. The semiconductor substrate 10 includes a plurality of protruding portions 50 (50a, 50b) on a rear side thereof.
Although unillustrated, unevenness called texture is preferably formed on the light receiving surface of the semiconductor substrate 10. This can prevent reflection of light on the light receiving surface. A passivation layer for preventing recombination of carriers is preferably provided on the light receiving surface. In addition, an antireflection film for preventing reflection of light is preferably provided on the light receiving surface. No structure (such as an electrode, for example) for blocking the entrance of light is provided on the light receiving surface of the semiconductor substrate 10, and thus the semiconductor substrate 10 can receive light on the entire light receiving surface.
The first semiconductor regions 20 are provided to extend in a first direction x, on the back surface of the semiconductor substrate 10. A longitudinal direction of the first semiconductor regions 20 is the first direction x. A plurality of the first semiconductor regions 20 are provided at predetermined intervals in a second direction y which is orthogonal to the first direction x. The first semiconductor regions 20 are formed in at least surfaces of the respective protruding portions 50 provided on the back surface of the semiconductor substrate 10. As shown in
Each first semiconductor region 20 includes a highly concentrated impurity of the same first conductivity type as the semiconductor substrate 10. In the solar cell 1, the conductivity type of the first semiconductor region 20 is an n+-type. The first semiconductor region 20 is made of an n+-type diffusion layer in which an n-type dopant (phosphorus (P), for example) is introduced into n-type single-crystalline silicon.
The first semiconductor region 20 is in the same crystal state as the semiconductor substrate 10. Since the semiconductor substrate 10 in the embodiment is a single crystal, the first semiconductor region 20 is also a single crystal. The first semiconductor region 20 is a diffusion layer formed by thermal diffusion. Thus, an interface between the first semiconductor region 20 and the semiconductor substrate 10 is formed in a deep area which is about 0.5 μm away from a surface thereof. For this reason, scratches hardly occur on a junction portion between the first semiconductor region 20 and the semiconductor substrate 10.
The second semiconductor layer 30 is formed in the first direction x, on the back surface of the semiconductor substrate 10. The second semiconductor layer 30 is formed on the semiconductor substrate 10 located between the one protruding portion 50a and the other protruding portion 50b. Accordingly, on the semiconductor substrate 10 as shown in
The second semiconductor layer 30 is of a second conductivity type different from the first conductivity type. In the solar cell 1, the conductivity type of the second semiconductor layer 30 is a p-type.
The second semiconductor layer 30 includes at least a p-type amorphous semiconductor layer 30p. Preferably, a thin-film i-type amorphous semiconductor layer 30i is inserted between the semiconductor substrate 10 and the p-type amorphous semiconductor layer 30p. The i-type amorphous semiconductor layer 30i preferably has a thickness which does not substantially contribute to power generation, for example, the thickness of several Å to 250 Å. The i-type amorphous semiconductor layer 30i and the p-type amorphous semiconductor layer 30p can be formed from an amorphous semiconductor including hydrogen. Examples of the amorphous semiconductor include amorphous silicon, amorphous silicon carbide, amorphous silicon germanium, and the like. The i-type amorphous semiconductor layer 30i is formed without actively introducing impurities into the amorphous semiconductor. The p-type amorphous semiconductor layer 30p is formed by introducing a p-type dopant (boron (B), for example) into the amorphous semiconductor.
The solar cell 1 according to the embodiment has a structure in which the i-type amorphous semiconductor layer 30i and the p-type amorphous semiconductor layer 30p are sequentially formed on the n-type semiconductor substrate 10 (what is called a “HIT” (registered trademark) structure), and therefore the p-n junction characteristics are improved.
As shown in
In the solar cell 1 as shown in
A depth D of the recessed portion 55 is preferably 0.4 μm or more. With this configuration, scratches can be further prevented from occurring on the junction between the second semiconductor layer 30 and the semiconductor substrate 10. Note that the height of the protruding portion 50 and the depth D of the recessed portion 55 coincide with each other.
An interval L between the one protruding portion 50a and the other protruding portion 50b is preferably 5 mm or less. With this configuration, nothing is likely to enter a space between the one protruding portion 50a and the other protruding portion 50b, and thus scratches can be further prevented from occurring on the junction between the second semiconductor layer 30 and the semiconductor substrate 10.
In the solar cell 1, the height of the protruding portion 50 is preferably five times or more a thickness h of the second semiconductor layer. With this configuration, scratches can be further prevented from occurring on the junction between the second semiconductor layer 30 and the semiconductor substrate 10.
A thickness H of the first semiconductor region 20 is 0.5 μm or more, and the thickness h of the second semiconductor layer is preferably 0.1 μm or less. With this configuration, scratches can be further prevented from occurring on the junction between the second semiconductor layer 30 and the semiconductor substrate 10.
Through the first semiconductor region 20, each electrode 40n collects carriers (electrons) generated in the semiconductor substrate 10. In the embodiment, the electrode 40n includes a connecting layer 41, a barrier layer 43, a foundation layer 45, and a plating layer 47. However, the embodiment is not limited thereto.
The connecting layer 41 is provided to collect photo-generated carriers from the first semiconductor region 20. The connecting layer 41 is formed such that the second semiconductor layer 30 is altered by irradiation of a laser beam, for example, to have low resistance. Alternatively, when a groove is provided in the second semiconductor layer 30 formed on the first semiconductor region 20, the connecting layer 41 is formed from the same material as the barrier layer 43. The second semiconductor layer 30 formed on the first semiconductor region 20 serves as a passivation layer. From a viewpoint of widening the area of the passivation layer, the width of the connecting layer 41 in the second direction y is preferably small. To be specific, the width of the connecting layer 41 is preferably one tenth or less of the width of the protruding portion 50 in the second direction y. Instead of forming the connecting layer 41 in a line shape in the first direction x, the connecting layer 41 may be formed at predetermined intervals in the first direction x.
The barrier layer 43 is provided so that a metal constituting the foundation layer 45 can be prevented from diffusing into the second semiconductor layer 30 formed on the first semiconductor region 20. Titanium (Ti) is used for the barrier layer 43, for example. A transparent electrode (TCO) may be used for the barrier layer 43.
The foundation layer 45 is provided as a foundation to form the plating layer 47. Cu, Cu alloy, Ag, or Ni is used for the foundation layer 45, for example.
The plating layer 47 is provided to reduce resistance loss of the electrode 40n. The plating layer 47 may be formed to be multi-layered. With this formation, the electrode 40n can be handled easily. The same material as the foundation layer 45 is used for the plating layer 47, for example. When the plating layer 47 is formed to be multi-layered, a plurality of materials may be selected from the same materials used for the foundation layer 45.
Through the second semiconductor layer 30, each electrode 40p collects photo-generated carriers (holes) generated in the semiconductor substrate 10. In the embodiment, the electrode 40p includes the barrier layer 43, the foundation layer 45, and the plating layer 47. However, the embodiment is not limited thereto. The configurations of the barrier layer 43, the foundation layer 95, and the plating layer 47 are the same as those of the electrode 40n.
The collector electrode 70n further collects photo-generated carriers (electrons) collected in the plurality of electrodes 40n. As shown in
(2) Method for Manufacturing Solar Cell 1
Description will be given of a method for manufacturing the solar cell 1 with reference to
As shown in
Step S1 is a step of forming the first semiconductor regions 20 of the first conductivity type, on a back surface side of the semiconductor substrate 10. First of all, the semiconductor substrate 10 is prepared. The semiconductor substrate 10 is an n-type single-crystalline silicon substrate. Etching with acid or alkaline solution has been performed on the semiconductor substrate 10 to remove dirt on a surface of the semiconductor substrate 10. The prepared semiconductor substrate 10 is heated in an atmosphere containing n-type impurities to introduce the n-type impurities into the surface of the semiconductor substrate 10. Thereby, the first semiconductor region 20 is formed in the surface of the semiconductor substrate 10, as shown in
Step S2 is a step of forming the second semiconductor layer 30 of a second conductivity type, on the back surface of the semiconductor substrate 10. Step S2 includes Step S21 and Step S22.
Step S21 is a step of removing the first semiconductor region 20 at intervals. First of all, as shown in
Next, the first semiconductor region 20 is removed by etching. Hydrofluoric acid and nitric acid mixture is used as the etching liquid for removing the first semiconductor region 20, for example. As shown in
Step S22 is a step of forming the second semiconductor layer 30 on the surface of the semiconductor substrate 10 which is exposed by removal of the first semiconductor region 20. By using CVD, the i-type amorphous semiconductor layer 30i is formed on the surface of the semiconductor substrate 10 which is exposed by removal of the first semiconductor region 20. Moreover, the p-type amorphous semiconductor layer 30p is formed on the i-type amorphous semiconductor layer 30i. Thereby, the second semiconductor layer 30 forms the bottom portion 57 of the recessed portion 55 formed by the one protruding portion 50a and the other protruding portion 50b. Since the second semiconductor layer 30 is the bottom portion 57 of the recessed portion 55, the height of the protruding portion 50 needs to be larger than the second semiconductor layer 30 formed on the semiconductor substrate 10. Hence, the second semiconductor layer 30 is preferably formed so that the thickness h of the second semiconductor layer 30 can be one fifth or less of the height of the protruding portion 50. In addition, the thickness h of the second semiconductor layer 30 is preferably 0.1 μm or less.
An example of a method of forming the i-type amorphous semiconductor layer 30i and the p-type amorphous semiconductor layer 30p includes chemical vapor deposition (CVD) such as plasma chemical vapor deposition. As shown in
Step S3 is a step of forming the electrodes 40n and the electrodes 40p. First of all, the connecting layer 41 is formed by altering the second semiconductor layer 30 on the first semiconductor region 20, or by removing the second semiconductor layer 30. An example of a method of altering the second semiconductor layer 30 includes a method using a laser. Carriers are outputted to an external circuit through the portions of the altered second semiconductor layer 30, i.e. the connecting layer 41. An example of a method of removing the second semiconductor layer 30 includes a method using a laser as well. Degrees of alteration or degrees of removal change depending on wavelength, power and the like of the laser. Other examples include: a method of removing part of the second semiconductor layer 30 formed on the first semiconductor regions 20 by etching, with use of etching paste or resist; and a method of mechanically grinding part of the second semiconductor layer 30 formed on the first semiconductor regions 20. Thereby, grooves having the first semiconductor regions 20 as their bottom surfaces are formed. In this case, when the barrier layer 43 is formed, a material constituting the barrier layer 43 enters the grooves. In other words, the connecting layer 41 and the barrier layer 43 are formed together by the same material.
In the solar cell 1, the second semiconductor layer 30 formed on the first semiconductor regions 20 as well serves as a passivation layer. For this reason, the width of the connecting layer 41 is preferably small. To be specific, the width of the connecting layer 41 is preferably one tenth or less of the width of the protruding portion 50 in the second direction y.
Next, as shown in
Subsequently, the resist 60 is applied to the foundation layer 45 by screen printing. The foundation layer 45 to which the resist 60 is applied becomes part of the electrodes 40n and the electrodes 40p. For this reason, the resist 60 is applied to positions where the electrodes 40n and the electrodes 40p are to be formed. A material having resistance against etching liquid for etching the barrier layer 43 and the foundation layer 45 is used for the resist 60.
In a conventional solar cell, a screen pushed by a squeegee may come into contact with a semiconductor layer, in applying the resist 60. When a thin semiconductor layer and a semiconductor substrate are joined together, such a contact may cause scratches on their junction portion. In contrast, according to the solar cell 1 of the embodiment, the thin second semiconductor layer 30 is formed between the one protruding portion 50a and the other protruding portion 50b adjacent to the one protruding portion 50a. For this reason, in printing the resist 60, a screen is less likely to come into contact with the second semiconductor layer 30 because the one protruding portion 50a and the other protruding portion 50b block the screen. As a result, scratches can be prevented from occurring on the junction portion between the second semiconductor layer 30 and the semiconductor substrate 10.
Next, the barrier layer 43 and the foundation layer 45 are removed by etching. In order to remove the barrier layer 43 and the foundation layer 45, ferric chloride and hydrofluosilicic acid are used for etching liquid, for example. As shown in
(3) Operation and Effect
In the solar cell 1, the plurality of protruding portions 50 are formed on the back surface of the semiconductor substrate 10. The second semiconductor layer 30 is formed on the semiconductor substrate 10 located between the one protruding portion 50a and the other protruding portion 50b adjacent to the one protruding portion 50a. The recessed portions 55 having the second semiconductor layer 30 as the bottom portions 57 thereof are each formed by the one protruding portion 50a and the other protruding portion 50b. For this reason, in printing the resist 60, a metal mask or a screen is less likely to come into contact with the second semiconductor layer 30 because the one protruding portion 50a and the other protruding portion 50b block the metal mask or the screen. As a result, scratches can be prevented from occurring on the junction portion between the second semiconductor layer 30 and the semiconductor substrate 10. Not only the metal mask or the screen but also another physical contact in handling of the solar cell 1 can be prevented. The first semiconductor regions 20 are formed in the protruding portions 50. Moreover, the first semiconductor regions 20 are in the same crystal state as the semiconductor substrate 10, and their junction is located at a portion deeper than a surface thereof. For this reason, scratches hardly occur on the junction portions between the semiconductor substrate 10 and the first semiconductor regions 20.
In the solar cell 1, the depth D of each recessed portion 55 is 0.4 μm or more. In addition, the interval L between the one protruding portion 50a and the other protruding portion 50b is 5 mm or less. For this reason, the one protruding portion 50a and the other protruding portion 50b are likely to block an external physical contact with the second semiconductor layer 30. Scratches can be further prevented from occurring on the junction between the second semiconductor layer 30 and the semiconductor substrate 10.
In the solar cell 1, the semiconductor substrate 10 is of the first conductivity type. For this reason, the semiconductor substrate 10 and the second semiconductor layer 30 are of different conductivity types from each other. Accordingly, the junction between the semiconductor substrate 10 and the second semiconductor layer 30 is a p-n junction. Deterioration of conversion efficiency can be suppressed which would otherwise occur when scratches occur on the junction portion between the semiconductor substrate 10 and the second semiconductor layer 30.
In the solar cell 1, the second semiconductor layer 30 is formed on the first semiconductor regions 20 as well. The second semiconductor layer 30 on the first semiconductor regions 20 serves as a passivation layer. Hence, recombination of carriers can be prevented.
In the method for manufacturing the solar cell 1, Step S1 includes a step in which the semiconductor substrate 10 is heated to introduce impurities into the semiconductor substrate 10 whereby the first semiconductor regions 20 are formed in the surface of the semiconductor substrate 10. Step S2 includes Step S21 in which the semiconductor substrate 10 is exposed by removing the first semiconductor region 20 at intervals, and Step S22 in which the second semiconductor layer 30 is formed on the semiconductor substrate 10 exposed by removal of the first semiconductor region 20. The first semiconductor regions 20 are formed in the plurality of protruding portions 50 which are not removed but remain. The bottom portion 57 of each recessed portion 55 formed by the one protruding portion 50a and the other protruding portion 50b adjacent to the one protruding portion 50a is the second semiconductor layer 30. Thereby, the solar cell 1 can be manufactured.
In the method for manufacturing the solar cell 1, in Step S22, while the second semiconductor layer 30 is formed on the semiconductor substrate 10, the second semiconductor layer 30 is formed on the first semiconductor regions 20 as well. Thereby, the step of manufacturing the solar cell 1 can be simplified.
(4) Other Embodiments
As described above, the details of the present invention have been disclosed by using the embodiment of the present invention. However, it should not be understood that the description and drawings which constitute part of this disclosure limit the present invention.
In the embodiment of the present invention, the semiconductor substrate 10 is an n-type, the first semiconductor region 20 is an n+-type, and the second semiconductor layer 30 is a p-type. However, the embodiment is not limited thereto. For example, the semiconductor substrate 10 maybe an n-type, the first semiconductor regions 20 may be a p-type, and the second semiconductor layer 30 may be an n-type. In this case, scratches can be prevented from occurring on the junction portion between the semiconductor substrate 10 and the second semiconductor layer 30 serving as a BSF layer provided to prevent recombination of carriers on the back surface.
In addition, the semiconductor substrate 10 may be a p-type, the first semiconductor regions 20 may be a p+-type, and the second semiconductor layer 30 may be an n-type. In this case, as in the case of the solar cell 1, scratches can be prevented from occurring on a p-n junction portion which is the junction between the second semiconductor layer 30 and the semiconductor substrate 10. As in the case of the solar cell 1, the second semiconductor layer 30 maybe formed on the first semiconductor regions 20 as well. The second semiconductor layer 30 on the first semiconductor regions 20 serves as a passivation layer. Thereby, recombination of carriers can be prevented.
In addition, the semiconductor substrate 10 may be a p-type, the first semiconductor region 20 may be an n-type, and the second semiconductor layer 30 may be a p-type. In this case, scratches can be prevented from occurring on the junction portion between the semiconductor substrate 10 and the second semiconductor layer 30 serving as a BSF layer provided to prevent recombination of carriers on the back surface.
Moreover, although the semiconductor substrate 10 is made of single-crystalline silicon, the embodiment is not limited thereto. The semiconductor substrate 10 may be made of polycrystalline silicon.
Furthermore, although the second semiconductor layer 30 is formed of the i-type amorphous semiconductor layer 30i and the p-type amorphous semiconductor layer 30p, the i-type amorphous semiconductor layer 30i is not always necessary. In other words, the second semiconductor layer 30 may be formed of the p-type amorphous semiconductor layer 30p.
As described above, the present invention includes various embodiments which are not described herein. Accordingly, the technical scope of the present invention should be determined only by the matters to define the invention in the scope of claims regarded as appropriate based on the description.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2010-017369 | Jan 2010 | JP | national |
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2011/051561 | Jan 2011 | US |
| Child | 13559777 | US |
