The present invention relates to a solar cell element and a solar cell module.
As a type of a solar cell element, a back-contact type solar cell element is known (for example, see Patent Document 1).
The solar cell element includes a semiconductor substrate that exhibits one conductivity type, a opposite conductivity type layer that exhibits a conductivity type opposing that of the semiconductor substrate, a first electrode, and a second electrode having a polarity different from that of the first electrode. The semiconductor substrate includes a plurality of through holes that penetrate between a light-receiving surface and a rear surface. The opposite conductivity type layer includes a first opposite conductivity type layer formed on the light-receiving surface of the semiconductor substrate, a second opposite conductivity type layer formed on an internal surface of each of the through holes of the semiconductor substrate, and a third opposite conductivity type layer formed on a rear surface of the semiconductor substrate. The first electrode includes a light-receiving surface electrode part formed on the light-receiving surface of the semiconductor substrate, a through hole electrode part formed in each of the through holes, and a bus bar electrode part formed on the rear surface of the semiconductor substrate. The light-receiving surface electrode part, the through hole electrode part, and the bus bar electrode part are electrically connected to each other. The second electrode is formed on a portion where the third opposite conductivity type layer is not formed on the rear surface of the semiconductor substrate.
Patent Document 1: WO 2008/078741
A solar cell module using the solar cell element described above is required to improve conversion efficiency of sunlight with a simple configuration in the context in which the solar cell module is expected to be more popularized. With respect to the improvement of the conversion coefficient, it is important that a loss of photovoltaic power be reduced.
The present invention has been made in consideration of the above problem and has as its object to provide an efficient solar cell element and an efficient solar cell module with simple configurations.
A solar cell element according to one embodiment of the present invention comprises a semiconductor substrate, a first electrode, and a second electrode. The semiconductor substrate comprises a first surface and a second surface on the rear side of the first surface and exhibits one conductivity type. The first electrode comprises a plurality of linear main electrode parts aligned on the first surface and a plurality of first output taking parts electrically connected to the main electrode parts and aligned on the second surface in a direction different from a longitudinal direction of the main electrode parts. The second electrode comprises one pair of collection parts arranged on the second surface to sandwich the first output taking parts, and a connection part arranged on the second surface and electrically connects the one pair of collection parts. The plurality of main electrode parts comprise a first electrode group including the main electrode parts aligned at first intervals D in a direction orthogonal to the longitudinal direction of the main electrode parts and a second electrode group including the main electrode parts aligned at second intervals E in the direction orthogonal to the longitudinal direction of the main electrode parts. In an alignment direction of the first output taking parts, a third interval F between the first electrode group and the second electrode group is larger than the first intervals D and the second intervals E. The connection part, in a planar perspective view from the first surface, is located at a position corresponding to the third interval F on the second surface.
According to the solar cell element described above, since an area for forming the connection part of the second electrode can be increased, an ohmic loss of the connection part can be reduced, and output characteristics of the solar cell element can be improved.
a) is a sectional schematic diagram when viewed from a section A-A in
a) is a sectional schematic diagram when viewed from a section J-J in
Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.
A solar cell element 10 according to a first embodiment of the present invention will be described below with reference to
The semiconductor substrate 1 includes a first surface 1F (upper surface side in
As the semiconductor substrate 1, a crystalline silicon substrate such as a single-crystal silicon substrate or a poly-crystal silicon substrate that contains a predetermined dopant element (impurity for controlling a conductivity type) and exhibits one conductivity type (for example, p type) is used. The thickness of the semiconductor substrate 1 can be set to, for example, 250 μm or less, and, furthermore, 150 μm or less. The shape of the semiconductor substrate 1 is not limited to a specific shape. However, the shape may be rectangular in terms of manufacturing processes.
In the embodiment, as the semiconductor substrate 1, a crystalline silicon substrate that exhibits a p-type conductivity type is used. When the semiconductor substrate 1 comprised of a crystalline silicon substrate is designed to exhibit a p type, as a dopant element, for example, boron or gallium can be used.
On the first surface 1F of the semiconductor substrate 1, as shown in
The semiconductor substrate 1, as shown in
The opposite conductivity type layer 2 is a layer that exhibits a conductivity type opposing that of the semiconductor substrate 1. The opposite conductivity type layer 2 includes a first layer 2a formed on the first surface 1F of the semiconductor substrate 1, the second layer 2b formed on the internal surface of the through hole 3, and a third layer 2c formed on the second surface 1S of the semiconductor substrate 1. When a silicon substrate that exhibits a p-type conductivity type is used as the semiconductor substrate 1, the opposite conductivity type layer 2 is formed to exhibit an n-type conductivity type.
The first layer 2a, for example, is formed to be of an n+ type having a sheet resistance of about 60 to 300 Ω/□. When the value of the sheet resistance is set in the range, an increase in surface recombination and an increase in surface resistance on the first surface 1F can be reduced. The first layer 2a, for example, is formed on the first surface 1F of the semiconductor substrate 1 to have a thickness of about 0.2 μm to 0.5 μm.
The second layer 2b is formed in the through hole 3. The second layer 2b may have a sheet resistance equal to that of the first layer 2a. The second layer 2b may have a sheet resistance lower than the sheet resistance of the first layer 2a. In this case, the increase in surface resistance can be more reduced.
The third layer 2c is formed in a forming area of the first electrode 4 and a peripheral portion thereof on the second surface 1S of the semiconductor substrate 1.
When the opposite conductivity type layer 2 is arranged, in the solar cell element 10, a p-n junction is formed between an area of one conductivity type and the opposite conductivity type layer 2 in the semiconductor substrate 1.
The semiconductor layer 6 is a layer formed to form an internal electric field inside the solar cell element 10 (to obtain a so-called BSF effect (Back Surface Field Effect)). In this manner, a decrease in power generation efficiency caused by recombination of carriers near the second surface 1S of the semiconductor substrate 1 can be reduced.
The semiconductor layer 6 is formed on an almost entire surface except for an area in which the third layer 2c is formed on the second surface 1S of the semiconductor substrate 1. More specifically, the semiconductor layer 6 is formed on the second surface 1S not to be in contact with the third layer 2c. A concrete forming pattern of the semiconductor layer 6 varies depending on a forming pattern of the first electrode 4. A p-n isolation area is formed between the third layer 2c and the semiconductor layer 6 and on a peripheral portion of the second surface 1S of the semiconductor substrate 1. The p-n isolation area includes an area of one conductivity type of the semiconductor substrate 1.
The semiconductor layer 6 exhibits the same conductivity type as that of the semiconductor substrate 1. A concentration of a dopant contained in the semiconductor layer 6 is higher than a concentration of a dopant contained in the semiconductor substrate 1. More specifically, in the semiconductor layer 6, a dopant element is present at a concentration higher than a concentration of a dopant element doped to cause the semiconductor substrate 1 to exhibit one conductivity type. The semiconductor layer 6 is formed by diffusing, for example, a dopant element such as boron or aluminum into the second surface 1S when the semiconductor substrate 1 exhibits a p-type. At this time, a concentration of a dopant element contained in the semiconductor layer 6 can be set to about 1×1018 to 5×1021 atoms/cm3. In this manner, the semiconductor layer 6 exhibits a p+-type conductivity type containing a dopant having a concentration higher than that of a p-type conductivity type exhibited by the semiconductor substrate 1, and forms a preferable ohmic contact with a first collection part 5b (will be described later).
The semiconductor layer 6, for example, may be formed to occupy 70% or more of the entire area of the second surface 1S when the second surface 1S of the semiconductor substrate 1 is planarly viewed. In this case, the BSF effect that improves output characteristics of the solar cell element 10 can be obtained.
The semiconductor layer 6 is not a necessary configuration in the embodiment, and may be formed as needed.
The antireflective layer 7 is formed on the first surface 1F of the semiconductor substrate 1. The antireflective layer 7 has a role to reduce reflection of incident light on the surface (first surface 1F) of the semiconductor substrate 1, and is formed on the first layer 2a. The antireflective layer 7 can be made of a silicon nitride film, an oxide material film, or the like. A preferable thickness of the antireflective layer 7 varies depending on construction materials. However, the thickness is set to a value at which a reflection-free condition is realized for incident light. For example, when a silicon substrate is used as the semiconductor substrate 1, the antireflective layer 7 may be formed by a material having a refraction index of about 1.8 to 2.3 to have a thickness of about 500 to 1200A.
The antireflective layer 7 is not necessarily arranged in the embodiment, and may be arranged as needed.
The first electrode 4 includes a plurality of main electrode parts 4a, a plurality of conduction parts 4b, and a plurality of first output taking part 4c. As shown in
The main electrode parts 4a has a function of collecting carriers generated on the first surface 1F side. The conduction part 4b has a function of guiding the carriers collected by the main electrode part 4a to the first output taking part 4c arranged on the second surface 1S. The first output taking part 4c functions as a wiring connection part connected to a wire that electrically connects adjacent solar cell elements to each other.
The conduction part 4b, as shown in
In the embodiment, the plurality of conduction parts 4b are arranged in a predetermined direction. In the solar cell element 10, as shown in
In the solar cell element 10, the conduction parts 4b are arranged to be aligned in a plurality of straight lines (3 lines in
The main electrode part 4a connects the conduction parts 4b belonging to different columns to each other on the first surface 1F of the semiconductor substrate 1. The main electrode part 4a is linear. In the embodiment, the linear main electrode part 4a, for example, as shown in
The width of the main electrode part 4a can be set to about 50 to 200 μm, and an interval between the main electrode parts 4a can be set to about 1 to 3 mm.
In the embodiment, the number of conduction parts 4b aligned in a direction along the reference side BS is equal to the number of main electrode parts 4a. In this manner, an increase in ohmic loss of a light-receiving surface electrode part can be reduced while keeping a light-receiving area on the first surface 1F.
The first electrode 4, as shown in
The first electrode 4, as shown in
In the solar cell element 10 described above, when a portion formed on the first surface 1F side serving as the light-receiving surface of the first electrode 4 is used as a light-receiving surface electrode part, a proportion of the light-receiving surface electrode part to the entire area of the first surface 1F serving as a light-receiving surface is very low. For this reason, high light-receiving efficiency is realized. Furthermore, since the light-receiving surface electrode part is uniformly formed on the first surface 1F, carriers generated on the first surface 1F can be efficiently collected.
Furthermore, the first electrode 4, as shown in
The first output taking parts 4c are sequentially aligned in a direction (alignment direction of the conduction parts 4b in the embodiment) different from the longitudinal direction of the main electrode parts 4a, and formed to have long-sheet shapes having a longitudinal direction in the alignment direction. In the embodiment, one of the first output taking parts 4c and the plurality of conduction parts 4b are connected to each other. Specifically, as shown in
The first output taking parts 4c are formed in a plurality of columns (3 columns in
On the other hand, the second electrode 5 has a polarity different from that of the first electrode 4, and is arranged to be insulated from the first electrode 4. The second electrode 5 described above, as shown in
The second output taking part 5a is formed on the second surface 1S. One pair of first collection parts 5b are arranged on both sides that sandwich the first output taking part 4c when the second surface 1S is planarly viewed. One pair of second collection parts 5c, as shown in
The second collection part 5c is not necessarily arranged in the embodiment, and may be arranged as needed. Thus, when the second collection parts 5c are not formed, the connection part 5d, when the second surface 1S is planarly viewed, electrically connects one pair of first collection parts 5b to sandwich the first output taking part 4c, or electrically connects one of the first collection parts 5b to the second output taking part 5a located on an opposite side through the first output taking part 4c.
The first collection part 5b is formed on the semiconductor layer 6 arranged on the second surface 1S of the semiconductor substrate 1, and collects carriers generated on the second surface 1S side. The first collection part 5b is formed on an almost entire surface of the second surface 1S except for the first output taking part 4c, the peripheral portion thereof, and a part of an area in which the second output taking part 5a is formed. In other words, the first collection parts 5b are paired with each other to sandwich the first output taking part 4c when the second surface 1S is planarly viewed.
In this case, the “almost entire surface” is a surface of 70% or more of the entire area of the second surface 1S when the second surface 1S of the semiconductor substrate 1 is planarly viewed. When the first collection part 5b is formed on an almost entire surface except for an area in which the first electrode 4 is formed on the second surface 1S, a moving distance of carriers collected by the first collection part 5b can be shortened. For this reason, since the number of carriers taken out of the second output taking part 5a can be increased, the output characteristics of the solar cell element 10 can be improved.
The second output taking part 5a roles as a wiring connection part connected to a wire that electrically connects adjacent solar cell elements to each other. The second output taking part 5a may include at least a part overlapping the first collection part 5b. For this reason, the carriers collected by the first collection part 5b can be output to the outside. For this reason, the second output taking part 5a, as shown in
The second output taking part 5a is arranged in parallel to the plurality of first output taking parts 4c, and has a long-sheet shape having a longitudinal direction in an alignment direction like the first output taking parts 4c. In the embodiment, the plurality of second output taking parts 5a, as described above, are formed along the alignment direction of the first output taking parts 4c. However, one belt-like second output taking part 5a may be formed.
The lengths of the first output taking part 4c and the second output taking part 5a along the reference side BS may be equal to each other or different from each other.
As shown in
The connection part 5d is formed in an area in which the first output taking part 4c is not formed on the second surface 1S. The solar cell element 10 having the connection part 5d can efficiently guide carriers collected by the second electrode 5 (the first collection part 5b and the second collection parts 5c) formed on the opposite side of the second output taking part 5a through the first output taking part 4c adjacent to the second output taking part 5a to the second output taking part 5a.
The first collection part 5b may be comprised of aluminum for example. The second output taking part 5a, the second collection parts 5c, and the connection part 5d can be comprised of silver, for example. The connection part 5d, for example, may be comprised of aluminum or a material obtained by forming silver on aluminum.
In the embodiment, as shown in
The numbers of first electrode groups 4a1 and second electrode groups 4a2 are not limited to specific numbers, and may be changed depending on arrangements of the connection parts 5d (will be described later).
In the embodiment, as shown in
The first electrode groups 4a1 and the second electrode group 4a2 that are adjacent to each other are formed on the first surface 1F at third intervals F in an alignment direction of the first output taking parts 4c. The third intervals F in the alignment direction of the first output taking parts 4c are larger than the first intervals D and the second intervals E. Furthermore, in the embodiment, the connection parts 5d are arranged at positions corresponding to the third intervals F on the second surface 1S when viewed through in plan view from the first surface 1F.
According to the embodiment, since a wide space can be formed between the first output taking part 4c connected to the first electrode group 4a1 and the first output taking part 4c connected to the second electrode group 4a2, the connection part 5d can have a large width. In this manner, an electric power collected by the first collection part 5b can be efficiently guided to the second output taking part 5a.
When the first intervals D and the second intervals E, for example, are set 1 mm to 2.8 mm, the third intervals F can be set to be larger than the first intervals D and the second intervals E and set to 1.05 mm to 3 mm.
In the embodiment, as shown in
The conductor area 4c1 is arranged to cover some of the plurality of conduction parts 4b. The taking area 4c2, as shown in
Since the conductor area 4c1 need only be electrically connected to the conduction part 4b, the conductor area 4c1 may have a shape that partially covers the conduction part 4b.
The taking area 4c2, on the second surface 1S, is adjacent to each of the conductor areas 4c1 and connected to each of the conductor area portions 4c1. The taking area 4c2 is arranged between the conductor area 4c1 and the first collection part 5b. The taking area 4c2, like the conductor area 4c1, has a long-sheet shape having a longitudinal direction along the alignment direction of the conduction parts 4b. The taking areas 4c2, as shown in
The conductor areas 4c1 and the taking areas 4c2 are formed in a plurality of columns (3 columns in
In the embodiment, as shown in
In this manner, in the embodiment, since the semiconductor layer 6 is also formed between the first output taking parts 4c that are adjacent to each other in the alignment direction of the first output taking parts 4c, the forming area of the semiconductor layer 6 on the second surface 1S can be increased. As a result, since the BSF effect occurring in the interface between the semiconductor substrate 1 and the semiconductor layer 6 can be enhanced, the output characteristics of the solar cell element 10 can be improved.
Furthermore, in the embodiment, the first collection part 5b is formed on the extending portion 6a of the semiconductor layer 6 located between the taking areas 4c2 in the alignment direction of the first output taking parts 4c. In this manner, on the second electrode 5 formed on the second surface 1S, an area in which only the narrow connection part 5d is present can be reduced in size. As a result, the ohmic loss of the second electrode 5 is reduced, and the output characteristics of the solar cell element 10 can be improved.
The length (size along the alignment direction of the first output taking parts 4c) of the conductor area 4c1 in the longitudinal direction of the conductor areas 4c1 may be set to cover the plurality of conduction parts 4b and may be set to 8 to 15 mm, for example.
The width (size along the direction orthogonal to the alignment direction of the first output taking parts 4c) of the conductor area 4c1 may be set to cover the conduction parts 4b and may be set to 0.1 to 1 mm, for example.
The length (size along the alignment direction of the first output taking parts 4c) of the taking area 4c2 in the longitudinal direction is a length at which the wiring material 15 that connect s the adjacent solar cell elements to each other can connect with the taking area 4c2, need only be shorter than that of the conduction part 4b, and can be set to 4 to 10 mm, for example.
The width (size along a direction orthogonal to the alignment direction of the first output taking parts 4c) of the taking area 4c2 may be equal to or larger than the width of the wiring material 15 (will be described later), and can be set to 1.5 to 4 mm, for example.
Furthermore, as shown in
As described above, in the embodiment, the first output taking part 4c includes a flared portion. However, the flared portion need not be formed.
Next, a solar cell element 30 according to a second embodiment of the present invention will be described below with reference to
In the embodiment, the arrangement of the conduction part 4b adjacent to the connection part 5d is different from that in the first embodiment. Specifically, in the embodiment, as shown in
With the above configuration, a space between the first output taking part 4c connected to the first electrode group 4a1 and the first output taking part 4c connected to the second electrode group 4a2 can be more increased. In this manner, the width of the connection part 5d can be more increased. As a result, an electric power collected by the first collection part 5b can be efficiently guided to the second output taking part 5a.
In this case, the distance G, as shown in
The distance H, as shown in
In the first embodiment, the conduction part 4b is arranged immediately below the main electrode part 4a to cause the center line of the main electrode part 4a to overlap the center of the conduction part 4b. For this reason, a distance between the adjacent main electrode parts 4a is equal to a distance between the adjacent conduction parts 4b. Thus, in the first embodiment, the distance G is equal to the distance H.
In the embodiment, a pad electrode part 4e1 that is proximate to the third intervals F of the plurality of pad electrode parts 4e, as shown in
Next, a solar cell element 40 according to a third embodiment of the present invention will be described below with reference to
In the embodiment, the arrangement of the main electrode parts 4a is different from that in the first embodiment. Specifically, in the embodiment, as shown in
In the solar cell module (will be described later), light irregularly reflected by a rear-surface protective material may be reflected by a transparent substrate and incident on an outer peripheral side of the first surface 1F of the semiconductor substrate 1. According to the embodiment including the third electrode group 4a3, an amount of light received on the outer peripheral side of the solar cell element 10 (semiconductor substrate 1) can be increased. For this reason, the output characteristics of the solar cell element 10 can be improved.
Each of the fourth intervals I can be set to 1.5 to 3 mm, for example. As shown in
As shown in
When differences between the intervals (the first intervals D, the second intervals E, and the fourth intervals I) of the adjacent main electrode parts 4a in the electrode groups and the third intervals F are set to be 0.2 mm or less, it appears that the main electrode parts 4a are arranged at equal intervals. For this reason, a preferable appearance can be obtained.
Next, a solar cell element 50 according to a fourth embodiment of the present invention will be described below with reference to
The embodiment is different from the first embodiment in the shape of the second electrode 5. Specifically, in the first embodiment, the connection part 5d is connected to the second output taking part 5a through the second collection part 5c. On the other hand, in the embodiment, as shown in
The solar cell element 10 according to the first embodiment described above can be singularly used. However, the solar cell element 10 is also used as an element configuring a solar cell module. More specifically, the solar cell element 10 is arranged to be adjacent to the plurality of solar cell elements 10 each including the same structure. Furthermore, the solar cell elements 10 can be connected in series with each other to configure a module. A solar cell module 20 according to the fifth embodiment of the present invention will be described below with reference to
The solar cell module 20 includes the plurality of solar cell elements 10 according to the first embodiment arranged to be adjacent to each other and the wiring material 15 that electrically connects the adjacent solar cell elements 10 to each other.
The solar cell module 20, as shown in
The plurality of solar cell elements 10, as shown in
a) shows only a schematic section. However, in the solar cell module 20, as shown in
For descriptive convenience, in the following description, in
As shown in
As the wiring material 15, for example, a material obtained by cutting a belt-like copper foil including the entire surface of which is covered with a solder material with a predetermined length in the longitudinal direction can be used. When the wiring material 15 covered with the solder material is used, the first output taking part 4c and the second output taking part 5a of the solar cell elements 10 are soldered by using hot air, a soldering copper, or the like or by using a reflow furnace or the like. The wiring material 15, for example, can be set to about 0.1 to 0.4 mm in thickness and about 2 mm in width.
In the embodiment, as shown in
The wiring material 15 may have a shape separated from the semiconductor substrate 1 in a non-contact area that is an area except for a contact area with the plurality of first output taking parts 4c and the plurality of second output taking parts 5a. For example, the wiring material 15 may have an uneven shape including a convex portion that is far from the non-contact area. In this case, since the second electrode 5 and the wiring material 15 are not in contact with each other between the first output taking parts 4c, short-circuits can be reduced.
As the rear-surface protective material 14, a white material or the like having a high reflectance can be used. In this manner, light irradiated on between the solar cell elements 10 is irregularly reflected by the rear-surface protective material 14 to illuminate the solar cell elements 10. As a result, an amount of light received in the solar cell element 10 can be more increased. As the material of the rear-surface protective material 14, for example, white PET or the like can be used.
Next, a solar cell module 60 according to the embodiment will be described below with reference to
First, a solar cell element 70 in the solar cell module 60 according to the sixth embodiment will be described below with reference to
The solar cell element 70 according to the embodiment is different from the solar cell elements 10 according to the first embodiment in the shape of the first output taking part 4c. The shape of the first output taking part 4c according to the embodiment will be described below in detail with reference to
The solar cell element 70, as shown in
The first area 4g is an area located on the conduction part 4b exposed on the second surface 1S of the semiconductor substrate 1, and the second area 4h is an area located on the second surface 1S of the semiconductor substrate 1 except for on the conduction part 4b. Specifically, the first area 4g indicates an area overlapping the conduction part 4b and forms an almost circular shape as shown in
Next, the solar cell module 60 using the solar cell element 70 will be described below in detail with reference to
The solar cell module 60 according to the embodiment is different from the solar cell module 20 in a mode of connection between the first output taking part 4c and the wiring material 15. Specifically, in the embodiment, as shown in
In the above configuration, since the first area 4g located on the conduction part 4b is not bonded to the wiring material 15, the conduction part 4b is not easily influenced by expansion and contraction of the wiring material 15 caused by daily temperature cycling. As a result, damage such as cracks in the conduction part 4b can be reduced, and long-term reliability can be improved. Since the wiring material 15 can be arranged along the longitudinal direction of the first output taking part 4c such that the wiring material 15 is located immediately above the first area 4g of the first output taking part 4c, the electrode on the second surface 1S side of the solar cell element can be formed by a simple shape. As a result, an ohmic loss or the like of the solar cell module caused by a complex electrode shape on the second surface 1S can be reduced.
The embodiment, as a concrete embodiment in which the wiring material 15 described above is bonded to only the second area 4h of the first output taking part 4c, includes the following mode.
As shown in
As long as the protective layer 9 can suppress bonding between the first area 4g and the wiring material 15, the protective layer 9 is not limited, and may be comprised of an insulating material or a conductive material. For example, the material of the protective layer 9, a metal, for example, aluminum having low wettability to a solder can be used.
When aluminum is used as the protective layer 9 and the first collection parts 5b, after the first output taking part 4c is formed in advance, the protective layer 9 and the first collection part 5b are formed in the same step to make it possible to improve productivity. In this manner, the conductive protective layer 9 is formed, and the wiring material 15 and the protective layer 9 are brought into contact with each other to make it possible to electrically connect the first area 4g to the wiring material 15 through the protective layer 9.
When materials such as polyimide having low wettability to a solder are used as the protective layer 9 and the insulating layer 8, the protective layer 9 and the insulating layer 8 are formed in the same step to make it possible to improve productivity.
In the embodiment, although described a case when the protective layer 9 is arranged on the solar cell element 70 side in the solar cell module 60, specifically, on the first output taking part 4c side, the protective layer 9 may be arranged on the wiring material 15 side in advance. More specifically, by using the wiring material 15 including the protective layer 9, the plurality of solar cell elements 70 may be connected.
In the embodiment, the protective layer 9 is formed to cover not only the first area 4g but also, as shown in
The protective layer 9 may be formed by, for example, applying and heat-treating an aluminum paste, or may be formed by applying and hardening an ultraviolet curing or thermosetting solder resist.
Next, a solar cell module 80 according to the seventh embodiment of the present invention will be described below with reference to
The solar cell module 80 according to the embodiment is different from the solar cell module 60 in the shape of the wiring material 15. Specifically, the wiring material 15 is located on the first area 4g of the first output taking part 4c and arranged to be separated from the first area 4g. More specifically, as shown in
The bent portion 15a is a part of the wiring material 15 located immediately above the first area 4g and has a convex shape. The flat portion 15b is a part of the wiring material 15 except for the bent portion 15a. As shown in
By the wiring material 15 having the above shape, the first area 4g of the first output taking part 4c can be prevented from being bonded to the wiring material 15. At this time, in the embodiment, as shown in
Also in the embodiment, the wiring material 15 is arranged to separate the wiring material 15 from the first area 4g of the first output taking part 4c, and, as in the embodiment described above, the protective layer 9 may be arranged on the first area 4g.
Next, a solar cell module 90 according to an eighth embodiment of the present invention will be described below with reference to
The solar cell module 90 according to the embodiment is different from the solar cell module 80 in the shape of the wiring material 15. Specifically, as shown in
In the sixth to eighth embodiments, the mode of connection between the wiring material 15 and the first output taking part 4c has been described. Specifically, the configuration including the protective layer 9 has been described as the sixth embodiment, and a configuration including the wiring material 15 including the bent portion 15a and the flat portion 15b has been described as the seventh and eighth embodiments. The configuration in which the wiring material 15 is separated from the first area 4g and brought into contact with the second area 4h is not limited to the above. For example, when the wiring material 15 and the first output taking part 4c are bonded to each other by the conductive adhesive, the conductive adhesive is placed only in the second area 4h to make it possible to bond the wiring material 15 in the second area 4h without bonding the first area 4g and the wiring material 15 to each other.
Next, a method of manufacturing a solar cell element will be described below. Specifically, a method of manufacturing the solar cell element 10 will be described.
First, the semiconductor substrate 1 that exhibits a p-type conductivity type is prepared.
When a single-crystal silicon substrate is used as the semiconductor substrate 1, a single-crystal ingot is sliced into a predetermined thickness so as to make it possible to obtain the semiconductor substrate 1. A single-crystal silicon ingot manufactured by the known manufacturing method such as an FZ method or a CZ method can be used. When the poly-crystal silicon substrate is used as the semiconductor substrate 1, the semiconductor substrate 1 can be obtained by slicing a poly-crystal silicon ingot into a predetermined thickness. A poly-crystal silicon ingot manufacturing by the known manufacturing method such as a casting method, an in-cast solidification method, or the like can be used.
The following explanation will be made by exemplifying a case in which a crystalline silicon substrate that exhibits a p-type conductivity type and in which B (boron) or Ga (gallium) is doped as a dopant element at about 1×1015 to 1×1017 atoms/cm3 is used as the semiconductor substrate 1.
A mechanical damaged layer or a contaminated layer formed on the surface layer of the semiconductor substrate 1 by cutting (slicing) is removed in advance. For example, the surface parts on a surface side and a rear surface side of the semiconductor substrate 1 may be etched in about 10 to 20 μm with NaOH, KOH, or a liquid mixture of a hydrofluoric acid and a nitric acid, and then cleaned with pure water or the like. In this manner, an organic component and a metal component is removed in advance.
Next, the through hole 3 is formed between the first surface 1F and the second surface 1S of the semiconductor substrate 1.
The through hole 3 can be formed by using a mechanical drill, a water jet, a laser machining device, or the like. The through hole 3 is formed such that the semiconductor substrate 1 is processed from the second surface 1S side to the first surface 1F side without damaging the first surface 1F serving as a light-receiving surface. However, when the semiconductor substrate 1 is less damaged by processing, processing may be performed from the first surface 1F to the second surface 15.
Next, a texture structure 1a including a small projection (convex portion) 1b is formed on a light-receiving surface side of the semiconductor substrate 1 in which the through hole 3 is formed. The texture structure 1a, as described above, is to effectively reduce an optical reflectance.
As a method of forming the texture structure 1a, a wet etching method with an alkaline aqueous solution such as NaOH or KOH or a dry etching method using an etching gas having the property of etching silicon serving as a material of the semiconductor substrate 1 can be used.
Next, the opposite conductivity type layer 2 is formed. More specifically, the first layer 2a is formed on the first surface 1F of the semiconductor substrate 1, the second layer 2b is formed on the internal surface of the through hole 3, and the third layer 2c is formed on the second surface 1S.
When a crystalline silicon substrate that exhibits a p-type conductivity type is used as the semiconductor substrate 1, the opposite conductivity type layer 2 exhibits an n type. As an n-doping element to form the opposite conductivity type layer 2, P (phosphorous) can be used.
The opposite conductivity type layer 2 can be formed by using, for example, the following method. As the first method, an applying thermal diffusion method that applies a P2O5 paste on a forming target position of the opposite conductivity type layer 2 on the semiconductor substrate 1 to perform thermal diffusion is known. As a second method, a gas-phase thermal diffusion method that diffuses a POCl3 (phosphorous oxychloride) gas as a diffusion source into a forming target position is known. As a third method, an ion implantation method that directly diffuses phosphorous by causing an ion beam to be incident on a forming target position is used. By using the gas-phase diffusion method, on the forming target positions on both the major surfaces of the semiconductor substrate 1 and the internal surface of the through hole 3, the opposite conductivity type layers 2 can be formed in the same step.
In the condition in which a diffusion area is also formed at a position except for the forming target position, after an anti-diffusion layer is formed at the position in advance, and the opposite conductivity type layer 2 may be formed. In this manner, diffusion in a position except for the forming target position can be reduced. A diffusion region formed at a position except for the forming target position may be removed by etching without forming the anti-diffusion layer.
After the opposite conductivity type layer 2 is formed, as will be described later, when the semiconductor layer 6 is formed by an aluminum paste, aluminum serving as a p-type dopant element can be diffused in a sufficient depth at a sufficient concentration. For this reason, in this case, the presence of a shallow diffusion area formed in advance can be neglected. More specifically, in this case, the opposite conductivity type layer 2 that is present at a forming target position of the semiconductor layer 6 need not be specially removed.
With respect to a circumference of the area in which the first electrode 4 is formed and the peripheral portion of the second surface 1S of the semiconductor substrate 1, p-n isolation may be performed by the known method such as laser irradiation.
Next, the antireflective layer 7 may be formed on the first layer 2a.
As a method of forming the antireflective layer 7, a PECVD method, a vapor deposition method, a sputtering method, or the like can be used. For example, when the antireflective layer 7 comprised of an SiNx film is to be formed by the PECVD method, 500° C. is set in a reaction chamber, and the antireflective layer 7 is formed by producing a plasma by glow discharge decomposition using a gas mixture of silane (Si3H4) and ammonia (NH3) that are thinned with nitrogen (N2). The antireflective layer 7 may also be formed on the second layer 2b.
Next, the semiconductor layer 6 is formed on the second surface 1S of the semiconductor substrate 1.
When boron is used as a dopant element, formation can be performed at a temperature of about 800 to 1100° C. by a thermal diffusion method using BBr3 (boron tribromide) as a diffusion source. In this case, prior to the formation of the semiconductor layer 6, on an area except for the forming target position of the semiconductor layer 6, for example, on the opposite conductivity type layer 2 or the like that has been formed, an anti-diffusion layer comprised of an oxide film or the like may be formed, and then removed after the semiconductor layer 6 is formed.
When aluminum is used as a dopant element, after an aluminum paste containing aluminum powder, an organic vehicle, and the like is applied to the second surface 1S of the semiconductor substrate 1 by a printing method and heat-treated (baked) at a temperature of about 700 to 850° C. to diffuse aluminum toward the semiconductor substrate 1 to make it possible to form the semiconductor layer 6. In this case, the semiconductor layer 6 serving as a desired diffusion area can be formed on only the second surface 1S serving as a printed surface of the aluminum paste. Furthermore, a layer comprised of aluminum formed on the second surface 1S after the firing can be directly used as the first collection part 5b without being removed.
Next, light-receiving surface electrode parts (main electrode part 4a and pad electrode part 4e) of the first electrode 4 and the conduction part 4b are formed.
The light-receiving surface electrode part and the conduction part 4b are formed by using an applying method, for example. Specifically, a conductive paste is applied to the first surface 1F of the semiconductor substrate 1 in a forming pattern for the light-receiving surface electrode part shown in
In this case, when the conductive paste is filled in the through hole 3 during the conductive paste is applied, in the same step as the step of forming a light-receiving surface electrode part, the conduction part 4b can also be formed. However, the conductive paste need not be sufficiently filled in the through hole 3 when the conductive paste is applied to the first surface 1F. This is because, as will be described later, the conductive paste is applied from the second surface 1S side also when the first output taking part 4c is formed, and, at this time, the conductive paste is also filled in the through hole 3 again and then fired.
After the conductive paste is applied, prior to firing, a solvent in the applied film may be evaporated at a predetermined temperature to dry the applied film. The light-receiving surface electrode part (including the main electrode parts 4a) and the conduction part 4b may be formed by separately performing applying and firing. Specifically, the conductive paste is filled in the through hole 3 in advance and dried. Thereafter, as in the above case, the conductive paste may be applied in a pattern of the light-receiving surface electrode part (including the main electrode part 4a) shown in
As described above, when the antireflective layer 7 is formed prior to the formation of the light-receiving surface electrode part (including the main electrode part 4a), the light-receiving surface electrode part may be formed in a patterned area, or the light-receiving surface electrode part may be formed by a fire-through method.
On the other hand, after the light-receiving surface electrode part is formed, the antireflective layer 7 may be formed. In this case, the antireflective layer 7 need not be patterned, and the fire-through method need not be used. For this reason, forming conditions for the light-receiving surface electrode part become moderate. In the steps described above, for example, even though firing is not performed at a high temperature of about 800° C., the light-receiving surface electrode part can be formed. As a result, heat damage to the semiconductor substrate 1 can be reduced.
Subsequently, on the second surface 1S of the semiconductor substrate 1, the first collection part 5b is formed.
The first collection parts 5b can also be formed by the applying method. Specifically, a conductive paste is applied to the second surface 1S of the semiconductor substrate 1 in a forming pattern of the first collection part 5b shown in
Furthermore, on the second surface 1S of the semiconductor substrate 1, the first output taking part 4c, the second output taking part 5a, the second collection part 5c, and the connection part 5d are formed.
The first output taking part 4c, the second output taking part 5a, the second collection part 5c, and the connection part 5d can be formed in one step by using an applying method, for example. Specifically, a conductive paste is applied to the second surface 1S of the semiconductor substrate 1 in an electrode pattern as shown in
The respective configurations may be formed in different steps, and may be formed by using conductive pastes having different compositions. When the semiconductor layer 6 and the first collection part 5b are formed in one step by using an aluminum paste, a part of the second output taking part 5a is formed on the third layer 2c without causing a specific problem.
The solar cell element 10 according to the embodiment can be manufactured by the above procedures.
As needed, a solder area (not shown) may be formed on the first output taking part 4c and the second output taking part 5a by a solder dip process.
The insulating layer 8, for example, may be formed by using a thin-film forming technique such as a CVD method, may be formed by applying and firing an insulating paste comprised of a resin paste, or may be formed by sticking a commercially available insulating tape. When the insulating paste is fired, the formation can be performed in the same step when the electrode is formed.
Next, a method of manufacturing the solar cell module 20 by using the solar cell element 10 formed as described above will be described below.
First, the wiring material 15 is manufactured in advance by cutting a material obtained by coating the entire surface of a copper foil having a thickness of about 0.1 to 0.4 mm and a width of about 2 mm with a solder material into a predetermined length in a longitudinal direction.
Then, as shown in
Thereafter, on the transparent member 11, the surface-side filler 12, the plurality of solar cell elements 10 connected to each other by the wiring material 15, the rear-side filler 13, and the rear-surface protective material 14 are sequentially laminated to manufacture a module base substance. The module base substances are integrated with each other by degassing, heating, and depressing to manufacture the solar cell module 20.
Then, as shown in
With the above procedures, the solar cell module 20 according to the embodiment can be obtained.
A solar cell module according to another embodiment can be manufactured by the same procedures as described above.
For example, the solar cell module 80 according to the seventh embodiment may be manufactured by using the wiring material 15 having the shape shown in
Then, as shown in
The solar cell module 90 according to the eighth embodiment can be manufactured by the same method as the manufacturing method of the solar cell module 80 according to the seventh embodiment.
In manufacturing of the solar cell module 60 according to the sixth embodiment, as described above, the wiring material 15 may be connected by using a cold-setting conductive adhesive. For example, when the conductive adhesive is heat-treated at about 150 to 250° C. after the wiring material 15 is brought into contact with on the second area 4h of the first output taking part 4c and the second output taking part 5a, the wiring material 15 can be connected to the first output taking part 4c and the second output taking part 5a. In this manner, the wiring material 15 is separated from the first area 4g of the first output taking part 4c and brought into contact with the second area 4h. As the conductive adhesive, for example, a conductive filler such as silver, nickel, or carbon containing an epoxy resin, a silicon resin, a polyimide resin, a polyurethane resin, or the like as a binder can be used.
The embodiments of the present invention have been described while illustrating the concrete configurations. However, the present invention is not limited to the embodiments, as a matter of course.
For example, in the solar cell element 10, as long as the alignment state is satisfied and the connection manner by the wiring material 15 can be realized, the first output taking part 4c and the second output taking part 5a may have shapes (for example, a trapezoidal shape, a circular shape, an oval shape, a semicircular shape, a sectorial shape, a composite shape thereof, or the like) different from the shapes described above.
When the solar cell element 10 is divided and used, a dividing position is set at a position near the connection part 5d to make it possible to reduce overlapping between the dividing position and the main electrode part 4a.
Number | Date | Country | Kind |
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2009-245513 | Oct 2009 | JP | national |
2009-246843 | Oct 2009 | JP | national |
2009-269805 | Nov 2009 | JP | national |
Filing Document | Filing Date | Country | Kind | 371c Date |
---|---|---|---|---|
PCT/JP2010/068982 | 10/26/2010 | WO | 00 | 4/25/2012 |