Embodiments of the present invention are in the field of renewable energy and, in particular, methods of fabricating solar cell emitter regions using N-type doped silicon nano-particles and the resulting solar cells.
Photovoltaic cells, commonly known as solar cells, are well known devices for direct conversion of solar radiation into electrical energy. Generally, solar cells are fabricated on a semiconductor wafer or substrate using semiconductor processing techniques to form a p-n junction near a surface of the substrate. Solar radiation impinging on the surface of, and entering into, the substrate creates electron and hole pairs in the bulk of the substrate. The electron and hole pairs migrate to p-doped and n-doped regions in the substrate, thereby generating a voltage differential between the doped regions. The doped regions are connected to conductive regions on the solar cell to direct an electrical current from the cell to an external circuit coupled thereto.
Efficiency is an important characteristic of a solar cell as it is directly related to the capability of the solar cell to generate power. Likewise, efficiency in producing solar cells is directly related to the cost effectiveness of such solar cells. Accordingly, techniques for increasing the efficiency of solar cells, or techniques for increasing the efficiency in the manufacture of solar cells, are generally desirable. Some embodiments of the present invention allow for increased solar cell manufacture efficiency by providing novel processes for fabricating solar cell structures. Some embodiments of the present invention allow for increased solar cell efficiency by providing novel solar cell structures.
Methods of fabricating solar cell emitter regions using N-type doped silicon nano-particles and the resulting solar cells are described herein. In the following description, numerous specific details are set forth, such as specific process flow operations, in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known fabrication techniques, such as lithography and patterning techniques, are not described in detail in order to not unnecessarily obscure embodiments of the present invention. Furthermore, it is to be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
Disclosed herein are methods of fabricating solar cells. In one embodiment, a method of fabricating an emitter region of a solar cell includes forming a plurality of regions of N-type doped silicon nano-particles on a first surface of a substrate of the solar cell. A P-type dopant-containing layer is formed on the plurality of regions of N-type doped silicon nano-particles and on the first surface of the substrate between the regions of N-type doped silicon nano-particles. At least a portion of the P-type dopant-containing layer is mixed with at least a portion of each of the plurality of regions of N-type doped silicon nano-particles. In another embodiment, a method of fabricating an emitter region of a solar cell includes forming a plurality of regions of N-type doped silicon nano-particles on a first surface of a substrate of the solar cell. A P-type dopant-containing layer is formed on the plurality of regions of N-type doped silicon nano-particles and on the first surface of the substrate between the regions of N-type doped silicon nano-particles. An etch resistant layer is formed on the P-type dopant-containing layer. A second surface of the substrate, opposite the first surface, is etched to texturize the second surface of the substrate. The etch resistant layer protects the P-type dopant-containing layer during the etching.
Also disclosed herein are solar cells. In one embodiment, an emitter region of a solar cell includes a plurality of regions of N-type doped silicon nano-particles disposed on a first surface of a substrate of the solar cell. Corresponding N-type diffusion regions are disposed in the substrate. A P-type dopant-containing layer is disposed on the plurality of regions of N-type doped silicon nano-particles and on the first surface of the substrate between the regions of N-type doped silicon nano-particles. Corresponding P-type diffusion regions are disposed in the substrate, between the N-type diffusion regions. An etch resistant layer is disposed on the P-type dopant-containing layer. A first set of metal contacts is disposed through the etch resistant layer, the P-type dopant-containing layer and the plurality of regions of N-type doped silicon nano-particles, and to the N-type diffusion regions. A second set of metal contacts is disposed through the etch resistant layer and the P-type dopant-containing layer, and to the P-type diffusion regions.
In a first aspect, one or more specific embodiments are directed to approaches for printing n-type silicon (Si) nano-particles and subsequently depositing a B2O3 oxide layer using boron tribromide (BBr3) as a precursor. The BBr3 precursor can be used to convert the Si nano-particles into a borophosphosilicate glass (BPSG) layer for use as a phosphorous diffusion source. Additionally, B2O3 is deposited in non-printed regions for use as a boron diffusion source. The approach can be used reduce or eliminate patterning and dopant deposition operations for solar cells having emitter regions formed in a bulk substrate or above a bulk substrate.
More specifically, in such fabrication process schemes, a patterned dopant source can be used for efficient doping. To achieve a useful pattern, a blanket deposition is typically followed by mask and etch lithography steps. Instead, one or more embodiments described herein involves patterning of a dopant source directly during deposition. Earlier attempts at direct patterning have included inkjet dopant formation. Other alternatives have involved inkjet and screenprint dopants that are oxide based, rather than Si nano-particle based. The materials for the earlier approaches can prove difficult to develop. In yet another earlier attempt, Si nano-particles are printed and a borosilicate glass (BSG) layer is formed on the Si nano-particles by APCVD. However, in such an approach, the nano-particles do not form a dense cohesive layer, and minimal phosphorous is available for being driven into an underlying substrate.
More generally, in the first aspect, one or more embodiments are directed to approaches for forming doped layers or regions in or above a substrate. In the case of forming doped diffusion regions in a bulk crystalline substrate, the ultimately formed emitter regions can be formed in, e.g., a bulk single crystalline silicon substrate. In the case of forming doped layers above a substrate, the ultimately formed emitter regions can be formed in, e.g., a polycrystalline or silicon layer. In either case, n-type Si nano-particles are printed on a region to be doped. The printing can be performed by screen-printing, inkjet printing, extrusion printing or aerosol jet printing, or other like approaches. Subsequent to printing, the receiving substrate can be placed in a diffusion furnace. A BBr3 deposition is performed to grow B2O3 on the wafer. The B2O3 layer fills in the voids in the Si nano-particle film, creating a densely networked layer. On the non-printed region, a typical B2O3 layer is deposited. After BBr3 deposition, the wafers are annealed in a high temperature diffusion step, which drives boron into the substrate from the B2O3 regions. In the Si nano-particle-printed regions, the phosphorous-doped Si is consumed by the B2O3 to form a silicate glass. The silicate glass layer is doped with both a heavy concentration of phosphorous and a more dilute concentration of boron, due to the smaller volume of voids than nano-particles. The result is a boron and phosphorous doped silicate glass (BPSG) layer. The BPSG layers can be used to preferentially drive phosphorous into silicon. Accordingly, the diffusion step involves a dominant phosphorous diffusion into the substrate from the BPSG (printed) area (with possibly some boron as well), and a boron diffusion from the B2O3, non-printed, regions.
As an example,
Referring to
In an embodiment, the plurality of regions of N-type doped silicon nano-particles 102 is formed by printing or spin-on coating phosphorous-doped silicon nano-particles on the first surface 101 of a substrate 100. In one such embodiment, the phosphorous-doped silicon nano-particles have an average particles size approximately in the range of 5-100 nanometers and a porosity approximately in the range of 10-50%. In a specific such embodiment, the phosphorous-doped silicon nano-particles are delivered in the presence of a carrier solvent or fluid which can later evaporate or be burned off. In an embodiment, when using a screen print process, it may be preferable to use a liquid source with high viscosity for delivery since using a low viscosity liquid may lead to bleeding, and hence resolution reduction of defined regions.
Referring to
In an embodiment, the P-type dopant-containing layer 104 is formed by depositing a layer of boron oxide (B2O3) on the plurality of regions of N-type doped silicon nano-particles 102 and on the first surface 101 of the substrate 100 between the regions of N-type doped silicon nano-particles 102. In one such embodiment, the layer of B2O3 is formed by reacting boron tribromide (BBr3) and oxygen (O2).
Referring to
In an embodiment, the mixing is performed by heating the substrate 100. In one such embodiment, the mixing is performed by heating at a temperature approximately in the range of 700-1100 degrees Celsius for a duration approximately in the range of 1-100 minutes. In an embodiment, the N-type doped silicon nano-particles 102 are phosphorus-doped silicon nano-particles, the P-type dopant-containing layer 104 is a boron-containing layer, and mixing the P-type dopant-containing layer 104 with the regions of N-type doped silicon nano-particles 102 involves forming corresponding regions of borophosphosilicate glass (BPSG) 106. In an embodiment, the mixing densifies the N-type doped silicon nano-particles 102 to provide a less porous or non-porous BPSG layer.
Referring to
In an embodiment, the diffusing is performed by heating the substrate 100. In one such embodiment, the heating for diffusing is performed in a same process operation as heating to mix the P-type dopant-containing layer 104 with the regions of N-type doped silicon nano-particles 102. In an alternative such embodiment, however, the heating for diffusing is performed in a different process operation as heating to mix the P-type dopant-containing layer 104 with the regions of N-type doped silicon nano-particles 102. In an embodiment, as described briefly above, diffusing N-type dopants from the regions of N-type doped silicon nano-particles 106 further includes diffusing an amount of P-type dopants from the doped silicon nano-particles 106. As such, the corresponding N-type diffusion regions 108 ultimately include that amount of P-type dopants.
Referring to
In a second aspect, one or more specific embodiments are directed to providing a bottom anti-reflective coating (bARC) deposition of silicon nitride (SiNx) before a random texturing (rantex) operation. In such an approach, the SiNx layer can be used as an etch-resist during the rantex etch. Generally, in developing a screen-printable dopant for bulk substrate solar cell fabrication, one technical issues involves having a dopant source material survive a rantex etch intact, so that it will be present for a subsequent dopant drive (e.g., P-drive) diffusion operation. Earlier attempts have included using a thick APCVD USG layer to prevent etching and moving the texture etch to a single-sided etching following a damaging etch. Other approaches for etch resistance in dopant sources have included reformulating the material to add etch resistance, densifying the film prior to APCVD deposition, and the use of single-sided rantex techniques. These approaches, however, take time to develop and some require new tools, rendering them non-ideal for retrofitting into existing fabs.
More specifically, one or more embodiments in the second aspect address a need for increasing rantex resistance for dopant film stacks. In a particular embodiment, a plasma-enhanced chemical vapor deposited (PECVD) SiNx is used since the layer has a low (undetectable) etch rate in, e.g., KOH. Furthermore, since PECVD SiNx can be used as a bARC layer in bulk substrate based solar cell, existing toolsets and architectures can be maintained while increasing the etch resistance of the film stack by moving the bARC deposition after atmospheric pressure chemical vapor deposition (APCVD) and before rantex. The resulting improved etch resistance may be particularly important for dopant material film stack that readily etches in KOH. Furthermore, the SiNx layer can provide an added advantage of defect fill-in for formed APCVD layers, where present defects are covered and sealed by the SiNx layer.
Although, for example, an undoped silicate glass (USG) layer formed by APCVD has a lower etch rate than Si, close to 2000 Angstroms of USG are typically etched in the rantex process. With SiNx on top of the film stack, the thickness (and therefore operating cost) of the USG layer can be reduced. The inclusion of an SiNx layer can add a degree of robustness to a standard film stack as well. Modifications of the current processing to allow for operation reduction can, in an embodiment, further include deposition of a doped layer (e.g., BSG or PSG) by PECVD instead of APCVD. Another option is to use doped SiNx:B or SiNx:P layers as dopant sources for diffusion. These layers can be formed to be thinner, due to the low etch rate of SiNx in KOH, while eliminating the APCVD tool in favor of using the PECVD bARC tool. In one such embodiment, a PECVD SiNx layer can be implemented along with other approaches to increase rantex resistance, such as dopant film densification.
As an example,
Referring to
In an embodiment, the plurality of regions of N-type doped silicon nano-particles 202 is formed by printing or spin-on coating phosphorous-doped silicon nano-particles on the first surface 201 of a substrate 200. In one such embodiment, the phosphorous-doped silicon nano-particles have an average particles size approximately in the range of 5-100 nanometers and a porosity approximately in the range of 10-50%. In a specific such embodiment, the phosphorous-doped silicon nano-particles are delivered in the presence of a carrier solvent or fluid which can later evaporate or be burned off. In an embodiment, when using an ink jet process, it may be preferable to use a liquid source with low viscosity for porous layer since using a high viscosity liquid may lead to bleeding, and hence resolution reduction, or defined regions.
Referring to
Referring to
Referring to
Referring to
In an embodiment, the heating is performed at a temperature approximately in the range of 850-1100 degrees Celsius for a duration approximately in the range of 1-100 minutes. In one such embodiment, the heating is performed subsequent to the etching used to provide texturized second surface 222 of the substrate 200, as depicted in
Referring to
Referring to
In another embodiment, not depicted, remaining portions of the N-type doped silicon nano-particles 202, the P-type dopant-containing layer 204, and the etch resistant layer 206 are removed prior to formation of contacts 212 in openings of the insulator layer 214. In one specific such embodiment, the remaining portions of the N-type doped silicon nano-particles 202, the P-type dopant-containing layer 204, and the etch resistant layer 206 are removed with a dry etch process. In another specific such embodiment, the remaining portions of the N-type doped silicon nano-particles 202, the P-type dopant-containing layer 204, and the etch resistant layer 206 are removed with a wet etch process. In an embodiment, the dry or wet etch process is mechanically aided.
Referring again to
In an embodiment, the solar cell 250 further includes a texturized second surface 222 of the substrate 200, opposite the first surface 201. In one such embodiment, the first surface 201 of the substrate 200 is a back surface of the solar cell 250, and the second surface 222 of the substrate 200 is a light receiving surface of the solar cell 250. In an embodiment, the solar cell further includes an anti-reflective coating layer 230 disposed on the texturized second surface 222 of the substrate 200. In an embodiment, region of N-type doped silicon nano-particles 202 is composed of phosphorous-doped silicon nano-particles having an average particles size approximately in the range of 5-100 nanometers. In an embodiment, the P-type dopant-containing layer 204 is a layer of borosilicate glass (BSG). In an embodiment, the etch resistant layer 206 is a silicon nitride layer. In an embodiment, the substrate 200 is a single crystalline silicon substrate.
More generally, referring to
Overall, although certain materials are described specifically above, some materials may be readily substituted with others with other such embodiments remaining within the spirit and scope of embodiments of the present invention. For example, in an embodiment, a different material substrate, such as a group III-V material substrate, can be used instead of a silicon substrate. Furthermore, it is to be understood that, where N+ and P+ type doping is described specifically, other embodiments contemplated include the opposite conductivity type, e.g., P+ and N+ type doping, respectively.
Thus, methods of fabricating solar cell emitter regions using N-type doped silicon nano-particles and the resulting solar cells have been disclosed. In accordance with an embodiment of the present invention, a method of fabricating an emitter region of a solar cell includes forming a plurality of regions of N-type doped silicon nano-particles on a first surface of a substrate of the solar cell. A P-type dopant-containing layer is formed on the plurality of regions of N-type doped silicon nano-particles and on the first surface of the substrate between the regions of N-type doped silicon nano-particles. At least a portion of the P-type dopant-containing layer is mixed with at least a portion of each of the plurality of regions of N-type doped silicon nano-particles. In one embodiment, subsequent to mixing the P-type dopant-containing layer with the regions of N-type doped silicon nano-particles, diffusing N-type dopants from the regions of N-type doped silicon nano-particles and forming corresponding N-type diffusion regions in the substrate, and diffusing P-type dopants from the P-type dopant-containing layer and forming corresponding P-type diffusion regions in the substrate, between the N-type diffusion regions.