Patent Application
20150144184
The present invention relates to the field of solar cells, and particularly of high efficiency crystalline silicon solar cells. More particularly, the present invention relates to a solar cell comprising a semiconductor wafer, an emitter formed by at least one emitter region which comprises at least a first layer of a first conductivity type and a first contact layer allowing a carrier extraction or injection, a backcontact comprising at least a second layer of a second conductivity type opposite of said first conductivity type and a second contact layer allowing a carrier extraction or injection, electrical contacts which are connected to said emitter regions and said backcontact respectively and designed to transport an electrical current out of the solar cell.
A particularly advantageous application of the present invention is for the production of photovoltaic cells intended for generating electrical energy, but the invention also applies, more generally, to any structure in which light radiation is converted into an electrical signal, such as photodetectors.
A classical photovoltaic solar cell comprises typically on its front side a metal grid pattern. The contact fingers are made out of a metal. The busbars are usually contacted (soldered, welded or attached with a conductive glue or adhesive) with a highly conductive metal band to extract the current that is generated homogeneously over the optically active area (i.e. not covered by the contact grid) and collected by the thin fingers or grid contact.
When metal contacts touch directly a semiconductor, the excess minority carriers (which should be collected by the junction) in the semiconductor tend to recombine at this contact. Hence classical solar cells need to minimize the contact area between the metal and the semiconductor. In advanced solar cells, if such a contact is present, a higher doping is attempted below the contact to “screen” the metal. The rest of the cell is usually coated by a layer that allows an electronic passivation of the solar cells.
Another approach to make better electrical contacts is the use of layer stacks that allow at the same time a current extraction (current created by collecting the photogenerated carriers) and a passivation of contact. This is the case with the so called amorphous silicon/crystalline silicon heterojunction concept. As shown by
At the back an n-layer 6 covers the i-layer 5 and a TCO 7 covers the n-layer 6. In the present description, the i-n-TCO stack is called “backcontact”. The current can flow through this contact (because the i-layer is thin), but a good electronic passivation is ensured. At the frontside of the solar cell, the electrical current is transported out of the solar cell by metallic conductors 8 (for the front side), named grid fingers, that join then busbars, whereas the backside can either have a similar pattern as the front side, or be covered by a metal layer 9 that will conduct the current to busbars at the back. The metal at the front and at the back are required because the lateral conductivity of the TCO is not high enough to allow a transport without resistive losses, as soon as the distance exceeds typically a few mm. This configuration is called Front SHJ. The TCO layer 4 acts also as an antireflection coating.
The TCO at the front side has a high conductance (a sheet resistance in the range of 20 to 200 Ohm/sq) to allow a lateral transport of the electrical current collected by the emitter to the next contact fingers. The stack i-p-TCO covers the full front of the solar cell at the exception of the edges to avoid short circuits.
A particularity of these devices is the achievement of high open-circuit voltage typically 710 to 750 mV, higher than standard diffused crystalline solar cells, in which the direct contact between the semiconductor and the TCO (or equivalently the metal), leads to lower voltage.
In another configuration as shown by
In order to collect most efficiently the photogenerated carrier in the cell, so far, all authors have maximized the coverage of the solar cell with emitter. In the Front SHJ configuration, close to 100% of the front surface is covered with the emitter, and in the IBC-SHJ configuration it is typically 50 to 70% of the backside that is covered with the emitter, whereas the rest is covered with the back-contact.
Even though the schemes described above can lead to high efficiencies (today's certified efficiencies reported of 23.7% in case of Front-SHJ and 20.2% in the case of IBC-SHJ), these solar cells work as solar cell operating under standard 1 sun illumination, not allowing one to take advantage of concentration effects that can lead to higher performance of the cells. Concentration is usually achieved using lens or mirror that increases the cells Voc and the efficiency (providing no high series resistance are present).
Another disadvantage is that the i-layer, the p and n layers, and the TCO (on both sides of the cells) lead to parasitic light absorption that cannot be used by the solar cell. This is especially the case of the Front-SHJ, in which strong absorption in the blue green part of the spectrum occurs in the i and p layers, and of the TCO which creates free carrier absorption in the red part of the spectrum. The layers lead to minor absorption in the case of the IBC-SHJ. However in this case a precise patterning at the backside is required, in order to have the TCO 4 or 7 or the TCO/metal stack 4+9 or 7+9 come as close as possible to the edge of the regions with the p and n layers, making it difficult to manufacture.
The present invention provides a solar cell which allows to avoid the disadvantages of the prior art.
Accordingly, the present invention relates to a solar cell comprising:
According to the present invention, the area of the emitter covers between 0.5% to 15%, preferably between 1% and 10% and more preferably between 2% and 5% of the area of a side of the wafer on which the emitter regions are provided, the rest of the area of said side of the wafer being covered by first passivating regions which comprise at least a first passivating layer and at least one first optional additional layer which makes that the first passivating layer does not allow a carrier extraction or injection, said first passivating regions being not fully covered by the first layer of the first conductivity type of the emitter regions. Preferably, the first layer of the first conductivity type of the emitter regions may cover at most 10% of the surface of a first passivating region.
In some embodiments, the emitter is provided on a front side of the solar cell. The backcontact may be of a classical type or the backcontact may be formed by at least one backcontact region which comprises at least a second layer of the second conductivity type and a second contact layer allowing a carrier extraction or injection, the area of the backcontact covering between 0.5% to 15%, preferably between 1% and 10% and more preferably between 2% and 5% of the area of the backside of the wafer, the rest of the area of the backside of the wafer being covered by second passivating regions which comprise at least a second passivating layer and at least one second optional additional layer which makes that the second passivating layer does not allow a carrier extraction or injection, said second passivating regions being not fully covered by the second layer of the second conductivity type of the backcontact regions. Preferably, the second layer of the second conductivity type of the backcontact regions may cover at most 10% of the surface of a second passivating region.
In other embodiments, the emitter may be provided on a back side of the solar cell as well, the backcontact is formed by at least one backcontact region which comprises at least a second layer of the second conductivity type and a second contact layer allowing a carrier extraction or injection, and the areas of the emitter and of the backcontact cover between 0.5% to 15%, preferably between 1% and 10% and more preferably between 2% and 5% of the area of the back side of the wafer, the rest of the area of the backside of the wafer being covered by third passivating regions which comprise at least a third passivating layer and at least one third optional additional layer which makes that the third passivating layer does not allow a carrier extraction or injection, said third passivating regions being not fully covered by the first layer of the first conductivity type of the emitter regions or by the second layer of the second conductivity type of the backcontact regions, the backcontact regions being provided alternatively with the emitter regions, and a third passivating region being provided between an emitter region and a backcontact region. Preferably, the first layer of the first conductivity type of the emitter regions or the second layer of the second conductivity type of the backcontact regions may cover at most 10% of the surface of a third passivating region.
In some embodiments, the backcontact regions may be disconnected one from each other.
In other embodiments, the backcontact regions may be all connected to each other.
In a preferred embodiment, each backcontact region is formed by a continuous surface having an area of at least of 0.09 mm2.
Preferably, the backcontact region may comprise, from the inside to the outside of the solar cell, an intrinsic layer, the second layer of the second conductivity type, and the second contact layer allowing a carrier extraction or injection.
Said second contact layer may be selected from a transparent conductive oxide layer, a metallic layer, and a combination thereof.
In some embodiments, the front side of the solar cell may comprise a front passivation surface.
In some embodiments, the emitter regions may be disconnected one from each other.
In other embodiments, the emitter regions may be all connected one to each other.
In a preferred embodiment, each emitter region is formed by a continuous surface having an area of at least 0.09 mm2.
Preferably, the emitter region may comprise, from the inside to the outside of the solar cell, an intrinsic layer, the first layer of the first conductivity type, and the first contact layer allowing a carrier extraction or injection.
Said first contact layer is selected from a transparent conductive oxide layer, a metallic layer, and a combination thereof.
Preferably, the first, second or third passivating layer may comprise at least an intrinsic layer.
In some embodiments, the intrinsic layers may be made of hydrogenated amorphous silicon.
Advantageously, the intrinsic layer of the third passivating layer is the same as the intrinsic layer of the emitter regions and of the backcontact regions.
In other embodiments, the first, second or third passivating layer may be a non-absorbing layer selected from a SiNx layer, a Al2O3 layer, a stack SiOx/SiNy, a layer comprising Si, O and N, and a combination thereof.
Preferably, the first, second or third optional additional layer is a protective layer.
Advantageously, the first layer of the first conductivity type or the second layer of the second conductivity type may comprise hydrogenated amorphous silicon which is able to contain a phase of silicon with up to 80% of Raman Si crystalline fraction.
The hydrogenated amorphous silicon may be alloyed with atoms selected from O, N, C, and Ge, the fraction of Si atoms remaining at 30% of the atoms in the layer, without counting the H atoms present.
In the present description, everything which is described for a n-type wafer also applies to p-doped wafer and to intrinsic wafer, with the role of the n and p layers being reversed.
In the present description, the same references are used to design the same elements.
A solar cell according to the invention comprises a semiconductor wafer, an emitter formed by at least one emitter region which comprises at least a first layer of a first conductivity type and a first contact layer allowing a carrier extraction or injection, a backcontact comprising at least a second layer of a second conductivity type opposite of said first conductivity type and a second contact layer allowing a carrier extraction or injection. Electrical contacts are connected to said emitter regions and said backcontact respectively are designed to transport an electrical current out of the solar cell. According to the present invention, the area of the emitter covers between 0.5% to 15%, preferably between 1% and 10% and more preferably between 2% and 5% of the area of a side of the wafer on which the emitter regions are provided, the rest of the area of said side of the wafer being covered by first passivating regions comprising at least a first passivating layer and at least one first optional additional layer which makes that the first passivating layer does not allow a carrier extraction or injection and is not contacted electrically to the contacts, said first passivating regions being not fully covered by the first layer of the first conductivity type of the emitter regions.
If the solar cell comprises several emitter regions 20, corresponding to the most usual cases, the area of the emitter corresponds to the sum of the areas of each emitter region 20 which covers said side of the wafer.
In the configuration of
In the front side of the solar cell, the emitter regions 20 comprises, as defined above a stack i-layer 2/p-layer 3/a front TCO layer 4, from the inside to the outside of the solar cell. According to the invention said emitter regions 20 do not cover the full front surface of the wafer 1 but only a small fraction of it, typically 1 to 10% only. The metal fingers 8 contact the remaining emitter regions 20 but can either cover fully the front TCO layer 4 or only partially. When no emitter is present at the front, and more particularly no p-layer which could contribute to collecting the current, this part of the device is a first passivating region 40 called “the front passivating part” comprising the passivating layer 12. That means that a first passivating region 40 comprising said passivating layer 12 is provided between two emitter regions 20. The length of this part is called Lpass,front. Such passivating layer 12 could be an i-layer or an ip stack in the easiest configuration in such a case the p-layer has little lateral conductivity (>10 kOhm square) and cannot contribute to collecting the photogenerated current. Typically no TCO with a significant lateral conductivity is contacting the passivating layer 12. A protective additional layer 13, which corresponds to a dielectric with optical properties useful for creating an antireflection effect, is typically present on top of the passivating layer 12. The function of layers 12 and 13 can also be merged.
In
In the front side of the solar cell, the emitter regions 20 are the same as shown by
According to the invention, the area of the backcontact covers between 0.5% to 15%, preferably between 1% and 10% and more preferably between 2% and 5% of the area of the backside of the wafer 1, the rest of the area of the backside of the wafer 1 being covered by the second passivating regions 50 comprising the passivating layer 14.
If the solar cell comprises several backcontact regions 30, corresponding to the most usual cases, the area of the backcontact corresponds to the sum of the areas of each backcontact region 30 which covers said backside of the wafer.
Such embodiment allows to enhance the desired effect, the current having to flow through the back-contact area which is also smaller than the backside surface.
In these embodiments, the emitter regions are provided on the back side of the solar cell, and the areas of the emitter and of the backcontact cover between 0.5% to 15%, preferably between 1% and 10% and more preferably between 2% and 5% of the area of the back side of the wafer, the rest of the area of the back side of the wafer being covered by third passivating regions which comprise a passivating layer.
The solar cell of
The solar cell comprises also metal fingers 9.
The areas of the emitter and of the backcontact (that means the sum of the areas of the emitter regions and the sum of the areas of the backcontact regions) cover between 0.5% to 15%, preferably between 1% and 10% and more preferably between 2% and 5% of the area of the backside of the wafer, the rest of the area of the back side of the wafer being covered by said third passivating regions 60 comprising the passivating layer 16.
As defined above, the emitter region 20 comprises a stack i-layer 2/p-layer 3/a TCO layer 4, and the backcontact region 30 comprises a stack i-layer 5/n-layer 6/a TCO layer 7, from the inside to the outside of the solar cell.
The solar cell of
In this embodiment, the TCO layers 4 or 7 which defines the length Lemitter and Lback does not need to cover the full i-p stack or the full i-n stack, allowing for easier processing.
All these configurations have remarkable advantages, especially when wafers with a good lifetime are used (typically 1 millisecond and more for n-type wafer).
Indeed, as the heterojunction works at high injection level (because of the high voltage at the operating point of the cell, the point where the voltage x current product of the device under illumination is the largest), the passivating layer 12, 14, 16 present around the wafer ensures a very good electronic passivation and even if a wafer with high resistivity is used, a high conductivity is ensured because of the high number of carriers present. This allows a transport of current both with little resistive loss and with little recombination, because the diffusion length can be as long as a few mm if a wafer with sufficient lifetime is used. The carriers are then extracted through a limited area, but the current is generated over a large area. This creates at the working point of the solar cell conditions of concentration. This condition leads to a higher extracted power (and consequently fill factor of the solar cell).
For instance in the geometry of
Advantageously, for a typical cell geometry, in a cross section through the side and through the contact grid, the typical pitch (Lemitter+Lpass,front) or Lback+Lback, pass for the front SHJ cell, or Lemitter+Lback+Lback, pass for the IBC-SHJ cell is in the range of 100 microns to 1.5 mm, preferably between 300 microns and 1.0 mm.
For the sake of clarity, it is assumed that the described lengths are proportional to the covered area (assuming in a 2D geometry that the figure extends in the third dimension).
In some embodiments each emitter region 20 is formed by discontinuous points and each backcontact region 30 is formed by discontinuous points, each region having typically an area comprised between 20×20 μm2 and 100×100 μm2. Such a configuration is schematically shown in
In other preferred embodiment, said emitter regions 20 and said backcontact regions 30 are formed respectively by at least one substantially continuous surface. Such a configuration is schematically shown in
In such case, said emitter region or backcontact region in contact with silicon has at least an area of 0.09 mm2, with typical dimensions of 30 μm×3 mm at least. Such dimensions are those of the continuous surfaces formed on the cell and viewed from the top or the bottom of the cell, as shown by
In some embodiments, each emitter region 20 may be disconnected from each other and each backcontact region 30 may be disconnected from each other.
In other preferred embodiments, all emitter regions 20 of the solar cell are connected to each other or all backcontact regions 30 are connected to each other. Such an embodiment is shown by
Another advantage of the configuration is that, as a large fraction of the solar cells been not covered by the emitter region, it is possible to optimize separately the properties of layers 10, 12 and 13, or 14 and 15 or 16, 17 and 20 for improved passivation properties and for a reduction of the optical parasitic absorption. For instance in these parts, the TCO layer may be replaced by a SiNx layer and the p-layer thickness can be reduced or the p-layer can be totally suppressed if an i-p stacks was constituting the layer 12 or 16. Conversely, as the area of the emitter becomes similar to the area of the contact fingers, it becomes even possible to use TCO with adapted properties (e.g. with higher doping), or to use much thinner TCO if a metal is directly on top, thereby avoiding losses. It is even to suppress completely the TCO, replacing it by a metal or metal alloy that makes directly a contact to the p-type amorphous layer.
When applied to IBC-SHJ scheme, as shown by
In the present description, all represented i, n and p layers are based on hydrogenated amorphous silicon and can also contain several percents of O, N, C or Ge, the fraction of silicon atoms remaining at 30% of the atoms in the layer, without counting the H atoms present. Preferably the amount of O, N, C or Ge is equal to 0-20%, more preferably equal to 0-10% and more preferably equal to 0-5%.
The p and n layers can contain a phase of silicon, up to 80% Raman silicon crystalline fraction.
The emitter region consists typically in a-Si layer having a thickness comprised between 4 nm and 10 nm, a p-layer having a thickness comprised between 3 nm and 15 nm and a TCO contact layer having a thickness comprised between 10 nm and 80 nm, or between 10 nm and 300 nm if the emitter is located at the back.
The backcontact region consists typically in a-Si layer having a thickness comprised between 4 nm and 10 nm, a n-layer having a thickness comprised between 3 nm and 15 nm, and a TCO layer having a thickness comprised between 10 nm and 300 nm.
For simplicity of manufacturing, layer 12 (front passivating layer), can be an i-layer or an i-p stack (with possibly a thinner p layer) or even an i-n stack. The thickness of the front passivating layer is higher than 5 nm. It could also be a non-absorbing layer such SiNx or Al2O3 or a stack SiOx/SiNy or a layer comprising in general Si, O and N, or a combination thereof.
For simplicity of manufacturing, layer 14 (back passivating layer), can be an i-layer or an i-n stack (with possibly a thinner n layer) or even an i-p stack. The thickness of the back passivating layer is higher than 5 nm. It could also be a non-absorbing layer such SiNx or Al2O3 or a stack SiOx/SiNy or a layer comprising in general Si, O and N, or a combination thereof. In such a case it might possible to omit layer 17.
The optical and electrically insulating layer 13, 15 or 17 can be a thin stack of hydrogenated amorphous silicon layers covered by a SiNx layer or SiNOx layer stack or by a weakly absorbing layer.
The front passivation and antireflection surface 10 is known from one skilled in the art and may be for example a very thin intrinsic hydrogenated amorphous silicon layer (3-10 nm), possibly covered by 1-5 nm of doped amorphous Si covered by a SiNx layer or SiNyOx layer or a stack of layer comprising Si, O and N, or a weakly doped TCO layer (carrier concentration<1020 cm−3). The thickness of these layers is selected to obtain a antireflection effect. Typically one can use a SiNx layer with a refractive index comprised between 1.8 and 2 and a thickness of 70 nm.
The layers 10 and 13, 15 or 17 that play a role of optical layer, of electrically insulating layer to prevent injection or extraction of carrier and that can possibly be used as masking layer for plating process can be tuned with grading refractive index between, as they do not need to be electrically active.
For devices where a large fraction of the surface is active for carrier extraction, the use of TCO's is requested with sufficient in-plane conductivity (20 to 200 Ohm sq) for the front and providing antireflection at the front and index matching at the back, but it is possible to suppress the TCO layer and replace it with a direct metallic contact. This requires then that the emitter region has the same size as the grid finger in the Front-SHJ.
The TCO layer is known from one skilled in the art and may be typically made of ITO (Indium Tin Oxides) doped with tin (In2O3:Sn) or other metal dopants or with hydrogen In2O3:H, or a stack of these layers, with carrier concentration comprised between 1019 cm−3 and 2×1021 cm−3. The TCO layer may be also made of doped ZnO or other TCO containing In, Zn and Sn. The thickness of the TCO layer is comprised between 10 nm and 300 nm, typically between 70 nm and 90 nm when present at the front and between 80 nm to 300 nm when present at the backside.
The wafer used in the solar cell has typically a size comprised between 2×2 cm2 and 22×22 cm2.
The front surface of the wafer has a texture to reduce the reflection and trap the light inside the wafer, as known for one skilled in the art.
The following example illustrates the present invention without however limiting the scope.
For this experiment, first a regular Front-SHJ device of 20×20 mm2 was prepared with a 80 nm thick ITO layer, and with finger spacing (Lemitter+Lpass, front) after processing of around 1 mm was prepared. Then the contact fingers and part of the ITO were protected by a photoresist. The photoresist was etched away and then the ITO was simply etched away where the photoresist was opened. A dielectric was then deposited where the ITO has been removed to ensure suitable antireflection conditions. Various coverage ratio of the ITO were tested.
The solar cells of the invention have a potential to be almost perfect photovoltaic device. Even though no optical lens is used, the cell structure can create a strong effective concentration that can push the efficiency of crystalline solar cell well beyond the current world record of 25%, allowing in principle to come close to 29-30%, closer to the theoretical limit for crystalline silicon solar cells.
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/EP2012/062776 | 6/29/2012 | WO | 00 | 12/23/2014 |
