Patent Application
20100191896
(1) Field of the Invention
This invention relates generally to an electronic memory controller and relates more specifically to a Solid State Drive controller controlling data transfer between a host and flash memory using non-volatile RAM (NVRAM) for buffer memory.
(2) Description of the Prior Art
As flash memory density gets higher and cost lower, Solid State Drive (SSD) becomes more widely used. A major component in a SSD controller is a buffer memory, which interfaces fast disk drive protocols and slow write and read cycles of NAND flash memory. In prior art volatile RAM, e.g. Static Random Access Memory (SRAM) is used for such a buffer memory as disclosed by Lee et al. U.S. Patent Application Publication U.S. 2007/0106836.
A major disadvantage of the prior art implementations of a SSD controller is that data in the buffer is lost when the memory is not powered. It is a challenge for the designers of such systems to overcome this disadvantage.
There are patents or patent publications known dealing with Solid State Drive controllers:
U.S. Patent Application Publication (U.S. 2008/0126682 to Zhao et al.) proposes a solid state disk with multi flash controller channels, which is small in size, light in weight, low in power consumption and has no operating noise. In one embodiment, a flash memory based storage device comprises a hard disk protocol unit, a flash hard disk controller circuit and flash memories. The flash hard disk controller includes a protocol module, buffers, a logical circuit, a CPU, a controller interface and flash controllers. The CPU manages as many flashes as it can through multi flash controller channels. Each flash controller connects with a flash memory group and communicates with buffers and the CPU by SD/MMC/MS interface or a self-defined interface. The flash memory based storage device meets the specification specifically defined for a traditional hard disk, and communicates with a host by hard disk standard protocols and can reach or outperform the required performance.
U.S. Patent Application Publication (U.S. 2008/0059694 to Lee) discloses a hybrid hard disk drive including a hard disk drive controller to receive a plurality of write commands from a host, a buffer to receive and store write data, which are input through the hard disk drive controller and correspond to each of the plurality of write commands, a command history tracker to receive the plurality of write commands and analyze a pattern of the plurality of write commands, and a CPU to control storage of the write data, which correspond to each of the plurality of write commands, on a disk or in a flash memory device based on the analysis result by the command history tracker. The drive may determine whether to store write data on the disk or in the flash memory device without operation system support.
U.S. patent (U.S. Pat. No. 6,016,530 to Auclair et al.) discloses a solid-state flash electrically erasable and programmable read-only-memory (“flash EEPROM”) system combined with a rotating disk drive memory to provide mass program and data storage in a computer system. A common memory controller directs system generated memory addresses in a disk format to either the EEPROM system or disk memory. The blocks of data handled by the EEPROM system have the same size and other attributes as sectors of data handled by the disk system, thereby making it transparent to the computer system processor as to whether it is accessing the EEPROM or disk portion of the storage system. A particular program or data file may then be stored in the portion of the memory system best suited to handle it, and thus take advantage of the different features and characteristics of EEPROM and magnetic media disk memory.
A principal object of the present invention is to achieve a Solid State drive controller supporting data transfer been a host and flash memories.
A further object of the present invention is that data are kept in a buffer memory when the buffer memory is not powered
A further object of the present invention is to implement non-volatile tables holding information about address translation, defective sector information and/or SSD configuration parameters.
In accordance with the objects of this invention a method to achieve a SSD controller supporting data transfer between a host and flash memory wherein data are kept in a buffer memory when the buffer memory is not powered has been achieved. The method invented comprises the steps of (1) providing a SSD controller comprising a CPU, a CPU bus, a disk interface, a NVRAM cache buffer, a first-in-first-out buffer (FIFO), and a flash interface, (2) implementing in said CPU NVRAM control code, (3) implementing said NVRAM for buffer cache memory, and (4) operating said SSD.
In accordance with the objects of this invention a system for a SSD controller supporting data transfer between a host and flash memory, wherein data are kept in a buffer memory when the buffer memory is not powered, has been achieved. The system invented comprises, first, a CPU, a CPU bus, connected to the CPU, a disk interface, a NVRAM cache buffer memory, a first-in-first out buffer, clock generators, and a flash interface, and said disk interface, supporting disk protocols, connected to said NVRAM cache buffer memory. The key component of the invention is said NVRAM buffer cache memory, connected to said first-in-first-out buffer. Furthermore the system invented comprises said first-in-first-out buffer, connected to a flash interface, said flash interface, and said clock generators, connected to said CPU bus, said disk interface, said NVRAM cache buffer, said first-in-first-out buffer (FIFO), and to said flash interface.
In the accompanying drawings forming a material part of this description, there is shown:
The preferred embodiments disclose a Solid State Drive controller having a significantly improved performance by using for a buffer memory fast non-volatile memories, such as MRAM or Phase Change RAM.
The disk interface 202 supports the data transfer to and from a host with disk drive protocols, such as ATA, SATA, SCSI, etc The data transferred are buffered in an MRAM cache buffer 203. Alternatively other fast non-volatile memories as e.g. Phase-Change RAM could be used instead of MRAM.
Replacing the SRAM cache buffer of prior art with an MRAM buffer having non-volatile tables as shown in
Non-volatile tables, i.e. stored in a non-volatile RAM (NVRAM), can also be implemented using MRAM memory or other fast non-volatile memory, such as Phase Change RAM. Such tables can store the dynamic logical or physical address translation to improve endurance of the flash memory and/or defective sector information and spare sectors and/or SSD configuration parameters.
Step 30 of the method of
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.
