BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A is a diagram illustrating one example of a circuit configuration of a solid-state image pickup device according to a first embodiment of the present invention;
FIG. 1B is a diagram illustrating another example of a circuit configuration of a solid-state image pickup device according to the first embodiment;
FIG. 1C is a diagram illustrating a cross-sectional view of a pixel disposed in a central portion of a pixel array region;
FIG. 1D is a schematic diagram explaining incidence of light into the pixels disposed in the central and a peripheral portions of the pixel array region;
FIG. 2A is a schematic diagram illustrating a layout of microlenses formed in the pixel array region in the solid-state image pickup device according to the first embodiment;
FIG. 2B is a diagram illustrating an enlarged view of the portion “P” shown in FIG. 2A;
FIG. 3 is a diagram showing a relationship between an image height and an optimum incidence angle for each pixel having each image height;
FIG. 4A is a schematic diagram showing displacement amounts of the microlenses in detail;
FIG. 4B is a schematic diagram showing displacement amounts of color filters in detail;
FIG. 4C is a schematic diagram showing displacement amounts of second metal films in detail;
FIG. 5A is a schematic diagram illustrating a layout of the microlenses in a solid-state image pickup device according to a second embodiment of the present invention;
FIG. 5B is a diagram illustrating an enlarged view of the portion “Q” shown in FIG. 5A;
FIG. 6 is a diagram illustrating a cross-sectional view of a pixel disposed in a central portion of a pixel array region;
FIG. 7 is a diagram showing a relationship between an image height and an optimum incidence angle for pixels;
FIG. 8 is a schematic diagram illustrating a layout of microlenses in a solid-state image pickup device according to a third embodiment of the present invention;
FIG. 9 is a diagram showing a relationship between an image height and an optimum incidence angle for pixels;
FIG. 10A is a schematic diagram illustrating a layout of microlenses in a solid-state image pickup device according to a fourth embodiment of the present invention;
FIG. 10B is a diagram illustrating a second metal film in the solid-state image pickup device according to the fourth embodiment;
FIG. 11A is a diagram illustrating an enlarged view of one example of the portion “R” shown in FIG. 10B;
FIG. 11B is diagram illustrating an enlarged view of another example of the portion “R” shown in FIG. 10B;
FIG. 12A is a schematic diagram showing displacement amounts of the microlenses in detail;
FIG. 12B is a schematic diagram showing displacement amounts of color filters in detail;
FIG. 12C is a schematic diagram showing displacement amounts of second metal films in detail;
FIG. 13A is a diagram showing a relationship between an image height and an angle of a light beam passing through an opening of the second metal film;
FIG. 13B is a diagram showing a relationship between an image height and a displacement amount of a light-shielding film;
FIG. 13C is a diagram showing a relationship between an image height and a coupling capacitance between the first metal film and the second metal film;
FIG. 13D is a schematic diagram illustrating a cross-sectional view of a pixel disposed in a peripheral portion of a pixel array region;
FIG. 14 is a schematic diagram illustrating a configuration of a general amplifying solid-state image pickup device;
FIG. 15A is a schematic diagram illustrating a plane view of a pixel disposed in a central portion of a pixel array region;
FIG. 15B is a schematic diagram illustrating a plane view of a pixel disposed in a peripheral portion in the pixel array region;
FIG. 15C is a schematic diagram illustrating a cross-sectional view of the pixel shown in FIG. 15A;
FIG. 15D is a schematic diagram illustrating a cross-sectional view of the pixel shown in FIG. 15B;
FIG. 16 is a schematic diagram explaining incidence of light into the pixels disposed in the central and peripheral portions of the pixel array;
FIG. 17 is a schematic diagram showing a conventional shrink method.