Patent Grant
11217612
The present technology relates to a solid-state image sensing device and an electronic device, and particularly to a solid-state image sensing device and an electronic device capable of reducing noises.
There has been conventionally proposed a backside irradiation-type solid-state image sensing device in a global shutter system in which a floating diffusion region in which charges accumulated in a photodiode are transferred is substantially covered by a horizontal light blocking part and a vertical light blocking part is formed between adjacent pixels (see Patent Document 1, for example).
Patent Document 1: Japanese Patent Application Laid-Open No. 2013-98446
However, the technique described in Patent Document 1 is not enough in light blocking on an opposite surface to a light receiving surface of the photodiode. Thus, there is a problem that charges generated by a light not absorbed in but transmitted through the photodiode invade in a floating diffusion region and a noise can occur.
The present technology is disclosed in terms of such a situation, and is directed for reducing noises.
A solid-state image sensing device according to a first aspect of the present technology includes: a photoelectric conversion unit; a charge holding unit for holding charges transferred from the photoelectric conversion unit; a first transfer transistor for transferring charges from the photoelectric conversion unit to the charge holding unit; and a light blocking part including a first light blocking part and a second light blocking part, in which the first light blocking part is arranged between a second surface opposite to a first surface as a light receiving surface of the photoelectric conversion unit and the charge holding unit, and covers the second surface, and is formed with a first opening, and the second light blocking part surrounds the side surface of the photoelectric conversion unit.
A cross section of the first light blocking part can be tapered from a connection part with the second light blocking part toward the first opening.
A third light blocking part for covering at least an opposite surface of the charge holding unit to a surface opposing the first light blocking part can be further provided at a position away from the first light blocking part from a device forming surface where the first transfer transistor is formed.
A gate electrode of the first transfer transistor can be provided with a first electrode part parallel with the first light blocking part and a second electrode part vertical to the first light blocking part and extending from the first light blocking part closer to the charge holding unit toward the photoelectric conversion unit via the first opening.
There can be further provided a fourth light blocking part connected to the first light blocking part and at least partially arranged at a position closer to the charge holding unit than to the first light blocking part and different from the second light blocking part in parallel with the second surface.
The photoelectric conversion unit can be formed on a first semiconductor substrate, the charge holding unit can be formed on a second semiconductor substrate, the first transfer transistor can be formed over the first semiconductor substrate and the second semiconductor substrate, and a joining interface between the first semiconductor substrate and the second semiconductor substrate can be formed in a channel of the first transfer transistor.
The joining interface can be formed closer to a drain end of the transfer transistor than to a source end thereof.
The second light blocking part can be formed from the second surface of the photoelectric conversion unit, and there can be further provided a fifth light blocking part formed from the first surface of the photoelectric conversion unit and connected to the second light blocking part.
The photoelectric conversion unit, the charge holding unit and the first transfer transistor can be made of monocrystal silicon.
The photoelectric conversion unit can be provided with a protruded part on the second surface extending from the first light blocking part toward the charge holding unit via the first opening.
The protruded part can be spread in parallel with the second surface closer to the charge holding unit side than to the first light blocking part.
A charge discharging unit for discharging charges accumulated in the photoelectric conversion unit is further provided, and the charge discharging unit can be arranged at a position where a light with a predetermined incident angle is incident in a case where the light passes through the first opening.
The charge discharging unit can be arranged between mutually-adjacent first and second pixels, and can be shared by the first pixel and the second pixel.
The first openings can be arranged near the charge discharging unit in the first pixel and the second pixel, respectively, a second opening with substantially the same size as the first opening can be formed in the first pixel at a position corresponding to the first opening in the second pixel, and a third opening with substantially the same size as the first opening can be formed in the second pixel at a position corresponding to the first opening in the first pixel.
A sacrifice film for forming the first light blocking part can be made of SiGe, and an alignment mark made of the not-removed sacrifice film can be further provided.
A cross section of the first light blocking part can be rounded at the first opening.
A charge voltage conversion unit, and a second transfer transistor for transferring charges held in the charge holding unit to the charge voltage conversion unit can be further provided, and the first light blocking part can be arranged between the second surface of the photoelectric conversion unit, and the charge holding unit and the charge voltage conversion unit.
An electronic device according to a second aspect of the present technology includes a solid-state image sensing device, the device including: a photoelectric conversion unit; a charge holding unit for holding charges transferred from the photoelectric conversion unit; a first transfer transistor for transferring charges from the photoelectric conversion unit to the charge holding unit; and a light blocking part including a first light blocking part and a second light blocking part, in which the first light blocking part is arranged between a second surface opposite to a first surface as a light receiving surface of the photoelectric conversion unit and the charge holding unit, covers the second surface, and is formed with a first opening, and the second light blocking part surrounds the side surface of the photoelectric conversion unit.
A solid-state image sensing device according to a third aspect of the present technology includes: a photoelectric conversion unit; a charge holding unit for holding charges transferred from the photoelectric conversion unit; a transfer transistor for transferring charges from the photoelectric conversion unit to the charge holding unit; and a light blocking part including a first light blocking part formed with an opening, and a second light blocking part, in which the first light blocking part is arranged in parallel with a light receiving surface of the photoelectric conversion unit and between the photoelectric conversion unit and the charge holding unit, and covers the photoelectric conversion unit except the opening, and the second light blocking part surrounds the side surface of the photoelectric conversion unit.
According to the first to third aspects of the present technology, a light passing through the photoelectric conversion unit is blocked by the first light blocking part, and a light from an adjacent pixel is blocked by the second light blocking part.
According to the first to third aspects of the present technology, it is possible to reduce noises.
Additionally, the effects described herein are not necessarily limited, and any of the effects described in the present disclosure may be obtained.
Modes for carrying out the present technology (which will be called embodiments below) will be described below. Additionally, the description will be made in the following order.
A first embodiment of the present technology will be first described with reference to
{Exemplary Configuration of Solid-State Image Sensing Device 101a}
The solid-state image sensing device 101a is a backside irradiation-type image sensor in a global shutter system configured of a complementary metal oxide semiconductor (CMOS) image sensor or the like, for example. The solid-state image sensing device 101a receives and photoelectrically converts a light from a subject, and generates an image signal thereby to shoot an image.
The global shutter system is a system for performing global light exposure of starting light exposure at all the pixels basically at the same time and finishing the light exposure at all the pixels at the same time. Here, all the pixels are all of the pixels in a part appearing on an image, and dummy pixels and the like are excluded. Further, the global shutter system includes a system for moving over regions to be subjected to global light exposure while performing global light exposure in units of rows (such as several tens of rows) not at all the pixels at the same time if a temporal difference or image distortion is small enough to be ignored. Further, the global shutter system includes a system for performing global light exposure on pixels in a predetermined region not all the pixels in a part appearing on an image.
The backside irradiation-type image sensor is an image sensor configured such that a photoelectric conversion unit such as photodiode for receiving a light from a subject and converting it into an electric signal is provided between a light receiving surface in which a light from a subject is incident and a wiring layer provided with a wiring of a transistor or the like for driving each pixel.
Additionally, the present technology is not limited to applications to CMOS image sensors.
The solid-state image sensing device 101a includes a pixel array part 111, a vertical drive unit 112, a ramp wave module 113, a clock module 114, a data storage unit 115, a horizontal drive unit 116, a system control unit 117, and a signal processing unit 118.
The pixel array part 111 is formed on a semiconductor substrate (not illustrated) in the solid-state image sensing device 101a. The surrounding circuits such as the vertical drive unit 112 to the signal processing unit 118 may be formed on the same semiconductor substrate as the pixel array part 111, for example, or may be formed on a logic layer stacked on the semiconductor substrate. Further, for example, some of the surrounding circuits may be formed on the same semiconductor substrate as the pixel array part 111, and the rest of them may be formed on the logic layer.
Additionally, in a case where the surrounding circuits are formed on the same semiconductor substrate as the pixel array part 111, each of the devices such as transistors configuring the surrounding circuits can be in a mesa structure.
The pixel array part 111 is formed of pixels each having a photoelectric conversion device for generating and accumulating charges depending on the amount of light incident from a subject. The pixels (not illustrated) configuring the pixel array part 111 are two-dimensionally arranged in the lateral direction (row direction) and in the longitudinal direction (column direction). For example, in the pixel array part 111, pixel drive lines (not illustrated) are wired in the row direction per row of pixels arranged in the row direction, and vertical signal lines (not illustrated) are wired in the column direction per column of pixels arranged in the column direction.
The vertical drive unit 112 is formed of a shift register, an address decoder, or the like, and supplies a signal or the like to each pixel via the pixel drive lines thereby to drive all the pixels in the pixel array part 111 at the same time or in units of row.
The ramp wave module 113 generates a ramp wave signal used for analog/digital (A/D) converting a pixel signal and supplies it to a column processing unit (not illustrated). Additionally, the column processing unit is configured of a shift register, an address decoder, or the like, for example, and performs a noise cancellation processing, a correlated double sampling processing, an A/D conversion processing, and the like thereby to generate a pixel signal. The column processing unit supplies the generated pixel signal to the signal processing unit 118.
The clock module 114 supplies an operation clock signal to each unit in the solid-state image sensing device 101a.
The horizontal drive unit 116 selects a unit circuit corresponding to a column of pixels in the column processing unit in turn. With the selective scanning by the horizontal drive unit 116, a pixel signal, which is processed per unit circuit in the column processing unit, is output to the signal processing unit 118 in turn.
The system control unit 117 is configured of a timing generator for generating various timing signals, or the like. The system control unit 117 drives and controls the vertical drive unit 112, the ramp wave module 113, the clock module 114, the horizontal drive unit 116, and the column processing unit on the basis of the timing signals generated by the timing generator.
The signal processing unit 118 performs a signal processing such as calculation processing on a pixel signal supplied from the column processing unit and outputs an image signal configured of each pixel signal while temporarily storing data in the data storage unit 115 as needed.
{Exemplary Configuration of Pixel}
An exemplary circuit configuration of pixels formed in the pixel array part 111 in
In the example, each of the pixels in the pixel array part 111 includes a photoelectric conversion unit (PD) 151, a first transfer transistor (TRX) 152, a second transfer transistor (TRM) 153, a charge holding unit (MEM) 154, a third transfer transistor (TRG) 155, a charge voltage conversion unit (FD) 156, a discharging transistor (OFG) 157, a reset transistor (RST) 158, an amplification transistor (AMP) 159, and a select transistor (SEL) 160.
Further, in the example, each of the TRX 152, the TRM 153, the TRG 155, the OFG 157, the RST 158, the AMP 159, and the SEL 160 is configured of an N type MOS transistor. Then, the gate electrodes of the TRX 152, the TRM 153, the TRG 155, the OFG 157, the RST 158, and the SEL 160 are supplied with the drive signals TRX, TRM, TRG, OFG, RST, and SEL, respectively. The drive signals are pulse signals which are in the active state (on state) as high level state and in the non-active state (off state) as low level state. Additionally, putting a drive signal in the active state will be denoted below as turning a drive signal on, and putting a drive signal in the non-active state will be denoted below as turning a drive signal off.
The PD 151 is a photoelectric conversion device formed of a PN-junction photodiode, for example, which receives a light from a subject, and generates and accumulates charges depending on the amount of received light by photoelectric conversion.
The TRX 152 is connected between the PD 151 and the TRM 153, and transfers the charges accumulated in the PD 151 to the MEM 154 in response to the drive signal TRX applied to the gate electrode.
Additionally, as described below, at least two semiconductor substrates are applied and a joining interface as the applied surface is formed in a channel of the TRX 152 in the solid-state image sensing device 101a. Then, parasitic resistance Rp parallel to the PD 151 is generated on the joining interface in the TRX 152.
The TRM 153 controls a potential of the MEM 154 in response to the drive signal TRM applied to the gate electrode. For example, when the drive signal TRM is turned on and the TRM 153 is turned on, the potential of the MEM 154 is deeper, and when the drive signal TRM is turned off and the TRM 153 is turned off, the potential of the MEM 154 is shallower. Then, for example, when the drive signal TRX and the drive signal TRM are turned on and the TRX 152 and the TRM 153 are turned on, the charges accumulated in the PD 151 are transferred to the MEM 154 via the TRX 152 and the TRM 153.
The MEM 154 is a region for temporarily holding the charges accumulated in the PD 151 in order to realize the global shutter function.
The TRG 155 is connected between the TRM 153 and the FD 156, and transfers the charges held in the MEM 154 to the FD 156 in response to the drive signal TRG applied to the gate electrode. For example, when the drive signal TRM is turned off, the TRM 153 is turned off, the drive signal TRG is turned on, and the TRG 155 is turned on, the charges held in the MEM 154 are transferred to the FD 156 via the TRM 153 and the TRG 155.
The FD 156 is a floating diffusion region for converting the charges transferred from the MEM 154 via the TRG 155 into an electric signal (such as voltage signal), and outputting the electric signal. The FD 156 is connected with the RST 158, and is connected with a vertical signal line VSL via the AMP 159 and the SEL 160.
A drain of the OFG 157 is connected to a power supply VDD, and a source thereof is connected between the TRX 152 and the TRM 153. The OFG 157 initializes (resets) the PD 151 in response to the drive signal OFG applied to the gate electrode. For example, when the drive signal TRX and the drive signal OFG are turned on and the TRX 152 and the OFG 157 are turned on, the potential of the PD 151 is reset at the level of the power supply voltage VDD. That is, the PD 151 is initialized.
Further, the OFG 157 forms an overflow path between the TRX 152 and the power supply VDD, and discharges the charges overflowed from the PD 151 to the power supply VDD.
A drain of the RST 158 is connected to the power supply VDD, and a source thereof is connected to the FD 156. The RST 158 initializes (resets) each region of the MEM 154 to the FD 156 in response to the drive signal RST applied to the gate electrode. For example, when the drive signal TRG and the drive signal RST are turned on and the TRG 155 and the RST 158 are turned on, the potentials of the MEM 154 and the FD 156 are reset at the level of the power supply voltage VDD. That is, the MEM 154 and the FD 156 are initialized.
A gate electrode of the AMP 159 is connected to the FD 156, a drain thereof is connected to the power supply VDD, and the AMP 159 serves as an input unit of a source follower circuit for reading the charges obtained by photoelectric conversion in the PD 151. That is, a source of the AMP 159 is connected to the vertical signal line VSL via the SEL 160 thereby to configure the source follower circuit with a constant current source connected to one end of the vertical signal line VSL.
The SEL 160 is connected between the source of the AMP 159 and the vertical signal line VSL, and the gate electrode of the SEL 160 is supplied with the drive signal SEL as select signal. The SEL 160 is in the conducted state when the drive signal SEL is turned on, and the pixel provided with the SEL 160 is in the selected state. When the pixel enters the selected state, the pixel signal output from the AMP 159 is read by the column processing unit (not illustrated) via the vertical signal line VSL.
Further, in each pixel, the pixel drive lines (not illustrated) are wired per row of pixels, for example. Then, the drive signals TRX, TRM, TRG, OFG, RST, and SEL are supplied from the vertical drive unit 112 via the pixel drive lines to the pixels.
Additionally, the pixel circuit in
Additionally, the symbols “P” and “N” in the Figure indicate a P type semiconductor region and an N type semiconductor region, respectively. Further, “+” and “−” at the ends of the symbols “P++,” “P+,” “P−,” “P−−” as well as “N++,” “N+,” “N−,” “N−−” indicate the concentrations of impurities in a P type semiconductor region and an N type semiconductor region, respectively. A larger number of “+” indicate a higher impurity concentration, and a larger number of “−” indicate a lower impurity concentration. This is applicable to the following Figures.
Further, the lower side in
The solid-state image sensing device 101a is in a three-layer structure in which a first semiconductor substrate 201, a second semiconductor substrate 202, and a logic layer 203 are stacked.
An insulative film 214, a planarizing film 212, and a micro lens 211 are stacked on the lower surface of an N−− type semiconductor region 215 in the first semiconductor substrate 201.
An N− type semiconductor region 216 is formed above the micro lens 211 inside the N−− type semiconductor region 215. A P+ type semiconductor region 217 is stacked on the N− type semiconductor region 216. The hole-accumulation diode (HAD, registered trademark) type PD 151 is configured of the N− type semiconductor region 216 and the P+ type semiconductor region 217.
A light incident in the light receiving surface of the solid-state image sensing device 101a is photoelectrically converted by the PD 151, and the charges generated by the photoelectric conversion are accumulated in the N− type semiconductor region 216.
A P− type semiconductor region 218 is formed around a part where a vertical terminal (electrode) part 152AB of a gate terminal (electrode) 152A of the TRX 152 is inserted above the N− type semiconductor region 216.
A light blocking film 213 is formed between the PDs 151 (the N− type semiconductor region 216 and the P+ type semiconductor region 217) in adjacent pixels on the lower surface of the insulative film 214. The light blocking film 213 is arranged to extend over a plurality of pixels in the column direction between columns of pixels adjacent in the row direction in the pixel array part 111, for example. Further, the light blocking film 213 is arranged to extend over a plurality of pixels in the row direction between rows of pixels adjacent in the column direction in the pixel array part 111, for example.
Further, the upper surfaces and the side surfaces of the PDs 151 (the N− type semiconductor region 216 and the P+ type semiconductor region 217) are surrounded by a light blocking film 219. More specifically, the light blocking film 219 is configured of a horizontal light blocking part 219A and a vertical light blocking part 219B.
The horizontal light blocking part 219A has a planar shape parallel to the light receiving surface of the solid-state image sensing device 101a. The horizontal light blocking part 219A covers the top surfaces of the N− type semiconductor region 216 and the P+ type semiconductor region 217 configuring the PD 151 except an opening 219C. Further, the horizontal light blocking part 219A is arranged over the entire region of the pixel array part 111 except the opening 219C in each pixel like a horizontal light blocking part 804A according to a tenth embodiment described below with reference to
The vertical light blocking part 219B has a wall shape vertical to the light receiving surface of the solid-state image sensing device 101a. The vertical light blocking part 219B is formed to surround the side surfaces of the N− type semiconductor region 216 and the P+ type semiconductor region 217 configuring the PD 151. Further, the vertical light blocking part 219B is arranged to extend over a plurality of pixels in the column direction between columns of pixels adjacent in the row direction in the pixel array part 111 like a vertical light blocking part 804B according to the tenth embodiment described below with reference to
The opening 219C is provided for inserting the vertical terminal (electrode) part 152AB of the gate terminal (electrode) 152A of the TRX 152 into the N− type semiconductor region 216 and transferring the charges accumulated in the N− type semiconductor region 216 to an N+ type semiconductor region 231.
A light, which is not absorbed in the PD 151 and passes therethrough, is reflected on the horizontal light blocking part 219A, and is prevented from invading in an upper layer than the horizontal light blocking part 219A. Thereby, for example, the charges generated by the light passing through the PD 151 are prevented from invading in the N+ type semiconductor region 231 configuring the MEM 154 or an N++ type semiconductor region 230 configuring the FD 156, and a noise is prevented from occurring. Further, the vertical light blocking part 219B prevents a light incident from an adjacent pixel from leaking into the PD 151, and a noise such as mixed color from occurring.
The light blocking film 213 limits an oblique light incident in the PD 151 (the N− type semiconductor region 216).
Additionally, the opening 219C is desirably as small as possible to prevent a light passing through the PD 151 from passing. Further, the opening 219C is desirably arranged at an end of the pixel (near the vertical light blocking part 219B) in order to prevent an oblique light with a large incident angle from passing.
The light blocking film 213 and the light blocking film 219 are made of a material containing specific metal, metal alloy, metal nitride, or metal silicide, for example. The light blocking film 219 is made of tungsten (W), titanium (Ti), tantalum (Ta), nickel (Ni), molybdenum (Mo), chromium (Cr), iridium (Ir), platiniridium, titanium nitride (TiN), tungsten silicon compound, or the like, for example. Additionally, the materials making the light blocking film 213 and the light blocking film 219 are not limited thereto. For example, a substance with a light blocking property other than metals may be employed.
The light blocking film 219 is covered with an insulative film 220. The insulative film 220 is made of a silicon oxide film (SiO), for example. The insulative film 220 is covered with a P++ type semiconductor region 221. An N++ type semiconductor region 222 is formed between the insulative film 220 and the P++ type semiconductor region 221 on the lower surface of the horizontal light blocking part 219A and around the vertical light blocking part 219B. A gettering effect is caused by the N++ type semiconductor region 222. A stopper film 223 is formed between the insulative film 220 and the P++ type semiconductor region 221 above the horizontal light blocking part 219A. The stopper film 223 is made of a SiN film or SiCN film, for example.
The gate terminal (electrode) 152A of the TRX 152, the gate terminal (electrode) 153A of the TRM 153, the gate terminal (electrode) 155A of the TRG 155, and the gate terminal (electrode) 157A of the OFG 157 are formed on the upper surface of a P− type semiconductor region 224 in the second semiconductor substrate 202 via an insulative film 232. The gate terminals (electrodes) 153A, 155A, and 157A are arranged above the horizontal light blocking part 219A, and the gate terminal (electrode) 152A is arranged above the opening 219C of the light blocking film 219.
Additionally, there is illustrated in the Figure an example in which each device of the transistors and the like configuring a pixel in the solid-state image sensing device 101a is planar. The planar structure is employed so that terminal electrodes can be formed on the same plane and a current path can be shortened.
The TRX 152 is in a vertical gate structure in which the gate terminal (electrode) 152A is configured of a horizontal terminal (electrode) part 152AA and the vertical terminal (electrode) part 152AB. The horizontal terminal (electrode) part 152AA is parallel to the horizontal light blocking part 219A and is formed on the upper surface of the P− type semiconductor region 224 via the insulative film 232 like the gate terminals (electrodes) of other transistors. The vertical terminal (electrode) part 152AB is vertical to the horizontal light blocking part 219A and extends vertically downward from the horizontal terminal (electrode) part 152AA. The vertical terminal (electrode) part 152AB then penetrates through the second semiconductor substrate 202 from the side closer to the N+ type semiconductor region 231 (the MEM 154) than to the horizontal light blocking part 219A, and extends into the N− type semiconductor region 216 via the opening 219C of the light blocking film 219. Further, the vertical terminal (electrode) part 152AB is covered with the insulative film 232. Therefore, the gate terminal (electrode) 152A contacts the N− type semiconductor region 216 via the insulative film 232.
Additionally,
Further, though not illustrated, the gate terminal (electrode) of the RST 158 is formed between a P++ type semiconductor region 225 and an N++ type semiconductor region 226 on the upper surface of the P− type semiconductor region 224 via the insulative film 232. Further, a sidewall is formed on the side surface of each gate terminal (electrode).
Additionally, a surface on which the gate terminal (electrode) and the like of each transistor configuring a pixel in the solid-state image sensing device 101a are formed (such as the upper surface of the P− type semiconductor region 224) will be denoted below as device forming surface.
The P++ type semiconductor region 225, the N++ type semiconductor region 226, an N+ type semiconductor region 227, a P type semiconductor region 228, an N+ type semiconductor region 229, and the N++ type semiconductor region 230 are formed near the surface of the P− type semiconductor region 224 in the second semiconductor substrate 202 above the horizontal light blocking part 219A.
The P++ type semiconductor region 225 is arranged on the left of the gate terminal (electrode) of the RST 158 (not illustrated) thereby to configure a charge discharging unit.
The N++ type semiconductor region 226 is arranged on the left of the gate terminal (electrode) 155A of the TRG 155 thereby to configure the FD 156.
The N+ type semiconductor region 227 is arranged on the left of the gate terminal (electrode) 155A of the TRG 155 and adjacently on the right of the N++ type semiconductor region 226.
The P type semiconductor region 228 spreads from around the left side of the gate terminal (electrode) 155A of the TRG 155 toward around the right side of the gate terminal (electrode) 157A of the OFG 157. Further, the P type semiconductor region 228 surrounds the vertical terminal (electrode) part 152AB of the TRX 152 except the tip thereof via the insulative film 232.
The N+ type semiconductor region 229 is arranged on the right of the gate terminal (electrode) 157A of the OFG 157.
The N++ type semiconductor region 230 is arranged adjacently on the right of the N+ type semiconductor region 229 thereby to configure the charge discharging unit.
The N+ type semiconductor region 231 is formed inside the P type semiconductor region 228 above the horizontal light blocking part 219A. The N+ type semiconductor region 231 spreads from around the left end of the gate terminal (electrode) 155A toward around the right end of the gate terminal (electrode) 153A. The horizontal light blocking part 219A is arranged between the N+ type semiconductor region 231 and the upper surface (opposite surface to the light receiving surface) of the N− type semiconductor region. The N+ type semiconductor region 231 configures the HAD-type MEM 154.
A wiring layer, an interlayer insulative film, and the like are formed between the insulative film 232 in the second semiconductor substrate 202 and the logic layer 203.
Each surrounding circuit in the solid-state image sensing device 101a is arranged on either the second semiconductor substrate 202 or the logic layer 203, for example. In a case where a surrounding circuit is formed on the second semiconductor substrate 202, each device configuring the surrounding circuit is formed in a mesa structure on the device forming surface of the second semiconductor substrate 202, for example.
Additionally, only the wirings for the surrounding circuits in horizontally-long rectangles are illustrated in the logic layer 203 in
Here, the first semiconductor substrate 201 and the second semiconductor substrate 202 are applied to each other and an applied surface between the two substrates is assumed as joining interface S in the solid-state image sensing device 101a.
Therefore, the joining interface S is vertical to a direction of current flowing between the source and the drain of the TRX 152. Further, the joining interface S can be arbitrarily set at a position in the vertical direction in the Figure. Thus, a distance between the joining interface S and the drain end of the TRX 152 can be adjusted. Further, a distance between the joining interface S and the drain end of the TRX 152 can be made identical for all the pixels in the solid-state image sensing device 101a.
Incidentally, a band gap is caused in the joining interface S, which easily prevents transfer of charges. Further, a crystalline direction changes around the joining interface S, and a crystal grain boundary occurs. A new lattice defect may be formed in crystal at the crystal grain boundary, and a lattice defect concentration is higher around the crystal grain boundary. Thus, the electric field is higher and hot carriers easily occur around the joining interface S, which easily causes a deterioration in transistor performance.
If a position with a higher potential than the potential of the source end is present in the channel, charges cannot be transferred from the source to the drain. Further, if the potential is higher at any position in the channel, a trap is formed and the charge transfer performance easily deteriorates.
As illustrated in
As illustrated in
Thus, in a case where a joining interface is formed in the TFT channel, the joining interface is desirably formed near the drain end (near peak P3 in the Figure) while the drain end (peak P1 in the Figure) is avoided. That is, in a case where a joining interface is formed in the TFT channel, the joining interface is ideally formed in an oval in a dotted line in
Thus, the joining interface S is formed near the drain end of the TRX 152 in the solid-state image sensing device 101a. The joining interface S is formed substantially closer to the drain end of the TRX 152 than to the source end thereof.
The gate terminal (electrode) 152A of the TRX 152, the gate terminal (electrode) 153A of the TRM 153, the gate terminal (electrode) 155A of the TRG 155, and the gate terminal (electrode) 158A of the RST 158 are arranged in line in the lateral direction in the Figure. The gate terminal (electrode) 159A of the AMP 159 and the gate terminal (electrode) 160A of the SEL 160 are arranged in line in the lateral direction in the Figure to oppose the line of the gate terminal (electrode) 152A, the gate terminal (electrode) 153A, the gate terminal (electrode) 155A, and the gate terminal (electrode) 158A. The gate terminal (electrode) 152A of the TRX 152 and the gate terminal (electrode) 157A of the OFG 157 are arranged in line in the longitudinal direction in the Figure. Each gate terminal (electrode) is arranged on the upper surface of the P type semiconductor region 228 via the insulative film 232 (not illustrated), and is connected in series via an N++ type semiconductor region 272.
The gate terminal (electrode) 152A, the gate terminal (electrode) 153A, the gate terminal (electrode) 155A, the gate terminal (electrode) 157A, the gate terminal (electrode) 158A, and the gate terminal (electrode) 160A are applied with the drive signals TRX, TRM, TRG, OFG, RST, and SEL via the metal wiring, respectively. The FD 156 and the gate terminal (electrode) 159A are connected via the metal wiring. The power supply voltage VDD is applied between the gate terminal (electrode) 158A and the gate terminal (electrode) 159A in the N++ type semiconductor region 272 via the metal wiring. The right side of the gate terminal (electrode) 160A in the N++ type semiconductor region 272 in the Figure is connected to the vertical signal line VSL via the metal wiring.
Further, a P-well contact 271 is formed substantially at the center of the arranged gate terminals (electrodes) of the respective transistors. The P-well contact 271 is connected to the ground via the metal wiring, for example.
The TRM 153 is in a planar structure similarly to each transistor in a pixel. Specifically, the P type semiconductor region 228 is arranged below the gate terminal (electrode) 153A of the TRM 153 in the P− type semiconductor region 224 via the insulative film 232. The N+ type semiconductor region 231 configuring the MEM 154 is then formed in the P type semiconductor region 228. Thereby, the MEM 154 in the HAD structure is formed.
{Method for Manufacturing Solid-State Image Sensing Device 101a}
An exemplary method for manufacturing the solid-state image sensing device 101a will be described below with reference to
The first semiconductor substrate 201 is first prepared as illustrated in
A SiO2 film 301 is then formed on the surface of the first semiconductor substrate 201 by thermal oxidization or chemical vapor deposition (CVD) as illustrated in
P− type ions are then implanted and the P− type semiconductor region 218 is formed between the N−− type semiconductor region 215 and the SiO2 film 301 as illustrated in
Part of the surface of the SiO2 film 301 is then masked by photoresist 302 as illustrated in
Part of the surface of the SiO2 film 301 is then masked by photoresist 303 as illustrated in
The part not masked by the photoresist 303 in the P− type semiconductor region 218 is then removed down to a predetermined depth by dry etching as illustrated in
The SiO2 film 301 and the photoresist 303 are then removed as illustrated in
A SiO film 304 is then formed on the surface of the first semiconductor substrate 201 (the P− type semiconductor region 218) as illustrated in
The SiO film 304 is then patterned and an opening 304A is formed on the SiO film 304 as illustrated in
A trench 201A is then formed below the opening 304A of the SiO film 304 by dry etching as illustrated in
Then, the SiO film 304 is totally removed as illustrated in
The insulative film 220 made of SiO is then formed on the surface of the first semiconductor substrate 201 by oxidization, for example, as illustrated in
Part of the surface of the first semiconductor substrate 201 is then masked by photoresist 305 as illustrated in
Part of the top of the convex part of the P− type semiconductor region 218 in the surface of the first semiconductor substrate 201 is then masked by the photoresist 306 as illustrated in
Here, the P++ type semiconductor region 221 around the trench 201A is formed by obliquely implanting P++ions in the trench 201A. Then, the P++ type semiconductor region 221 is almost uniform in thickness without unevenness in the horizontal direction around the trench 201A. Thus, the N− type semiconductor region 216 side surfaces of which are surrounded by the P++ type semiconductor region 221 and configuring the PD 151 can be wider in the horizontal direction and can be increased in the area of its light receiving surface. Consequently, sensitivity of the pixel is enhanced. Further, the thickness of the P++ type semiconductor region 221 is almost uniform, and thus a potential trap does not occur and the design of surface pinning is facilitated.
On the other hand, for example, in a case where the P++ type semiconductor region 221 is to be formed by implanting ions from the surface of the first semiconductor substrate 201 without the formation of the trench 201A, the thickness of the P++ type semiconductor region 221 is non-uniform in the horizontal direction, and is wider at a deeper position. Thus, the N− type semiconductor region 216 configuring the PD 151 is narrower in the horizontal direction, and is smaller in the area of its light receiving surface. Consequently, sensitivity of the pixel lowers. Further, the thickness of the P++ type semiconductor region 221 is non-uniform, and thus a potential trap occurs, which is a cause of charge transfer failure and makes the design of surface pinning more difficult.
The convex part of the P− type semiconductor region 218 in the surface of the first semiconductor substrate 201 is then masked by photoresist 307 as illustrated in
The light blocking film 219 is then formed on the surface of the first semiconductor substrate 201 by CVD as illustrated in
The part except around the convex part of the P− type semiconductor region 218 in the surface of the first semiconductor substrate 201 is then masked by photoresist 308 as illustrated in
A SiO film is then formed on the surface of the first semiconductor substrate 201 by CVD as illustrated in
The stopper film 223 is then formed on the surface of the first semiconductor substrate 201 as illustrated in
A SiO film 309 is then formed on the surface of the stopper film 223 by CVD as illustrated in
The surface of the first semiconductor substrate 201 is then planarized by chemical mechanical polishing (CMP) as illustrated in
A silicon film 310 is then formed on the surface of the first semiconductor substrate 201 by epitaxial growth as illustrated in
Additionally, the silicon film 310 may be formed in a method other than epitaxial growth, for example. Further, amorphous silicon may be formed instead of the polysilicon 3106, for example. Furthermore, silicon may be directly joined with other silicon without epitaxial growth, for example.
The surface of the silicon film 310 is then polished by CMP as illustrated in
P− type ions and P++ type ions are then implanted in the silicon film 310 as illustrated in
The second semiconductor substrate 202 is then applied to the upper surface of the first semiconductor substrate 201 as illustrated in
Here, the second semiconductor substrate 202 employs a P− type monocrystal silicon substrate with crystal orientation of Si(111), for example. Mobility in a channel is higher with the crystal orientation (111) than with (100) plane, for example, and thus the transfer property is enhanced when charges are transferred from the PD 151 to the MEM 154. Additionally, the crystal orientation is not limited to (111), and joining can be performed in any orientation.
Further, a method for applying the first semiconductor substrate 201 and the second semiconductor substrate 202 is not particularly limited, and a technique used for applying a silicon on insulator (SOI) substrate may be employed, for example. For example, methods such as plasma joining, direct joining using van der Waals binding, joining under vacuum atmosphere, and thermal annealing processing after application may be employed.
Further, a surface processing method before the first semiconductor substrate 201 and the second semiconductor substrate 202 are applied is not particularly limited, and a processing is performed to be hydrophilic or hydrophobic, thereby reducing voids on the joining interface S and enhancing the joining intensity.
For example, there may be employed a method in which the respective surfaces of the first semiconductor substrate 201 and the second semiconductor substrate 202 are immersed in a hydrofluoric acid solution, dried, and then joined, the respective surfaces thereof are immersed in a solution of ammonia and hydrogen peroxide water, dried and then joined, the respective surfaces thereof are immersed in a solution of hydrochloric acid or sulfuric acid and hydrogen peroxide water, dried, and then joined, the respective surfaces thereof are subjected to plasm irradiation under vacuum, and then joined, or the respective surfaces thereof are subjected to plasm irradiation under ammonium or hydrogen atmosphere, and then joined.
Further, the inside of the second semiconductor substrate 202 may be previously a SOI substrate such that the thickness of the second semiconductor substrate 202 can be adjusted when being polished later. For example, the second semiconductor substrate 202 is made of a SOI substrate, thereby preventing the second semiconductor substrate 202 from being excessively polished.
A thermal annealing processing is then performed as illustrated in
The surface of the second semiconductor substrate 202 (the surface of the P− type semiconductor region 224) is then polished by CMP as illustrated in
A SiO film 311 is then formed on the surface of the second semiconductor substrate 202 as illustrated in
P type ions are then implanted and the P type semiconductor region 228 is generated as illustrated in
The SiO film 311 is then patterned as illustrated in
A trench 312 is then formed below the opening 311A of the SiO film 311 by dry etching as illustrated in
The SiO film 311 is then removed as illustrated in
The surfaces of the second semiconductor substrate 202 and the trench 312 are then oxidized and the insulative film 232 is formed as illustrated in
Polysilicon is then formed on the surface of the second semiconductor substrate 202 and inside the trench 312 by CVD as illustrated in
The P++ type silicon film 313 is then machined by dry etching and the gate terminal (electrode) of each transistor is generated as illustrated in
A lightly doped drain (LDD) is then generated as illustrated in
A sidewall is then formed on the side surface of the gate terminal (electrode) of each transistor as illustrated in
N++ type ions and P++ type ions are then implanted as illustrated in
An interlayer insulative film and a wiring layer are then formed on the upper layer of the device forming surface of the second semiconductor substrate 202 as illustrated in
The logic layer 203 is then applied to the upper surface of the second semiconductor substrate 202 as illustrated in
The lower surface of the first semiconductor substrate 201 is then polished and planarized by CMP as illustrated in
The lower surface of the first semiconductor substrate 201 is then machined and the solid-state image sensing device 101a is completed as illustrated in
Further, the planarizing film 212 is generated on the lower surface of the insulative film 214. Further, the micro lens 211 and the like are formed on the lower surface of the planarizing film 212 and the solid-state image sensing device 101a is completed.
As described above, in the solid-state image sensing device 101a, a light is blocked between pixels by the vertical light blocking part 219B so that a light leaked from an adjacent pixel is prevented from being incident in the PD 151, and a noise such as mixed color is prevented from occurring.
Further, a light which is not absorbed in the PD 151 and passes therethrough is blocked by the horizontal light blocking part 219A and is prevented from invading in an upper layer than the horizontal light blocking part 219A. Thereby, the charges generated by the light passing through the PD 151 are prevented from invading in the MEM 154 or the FD 156, and a noise is prevented from occurring. The effect is larger as the charges are accumulated in the MEM 154 or the FD 156 for a longer time.
Further, the horizontal light blocking part 219A prevents an electric field occurring in a transistor configuring each pixel from influencing the PD 151. That is, a dark current caused due to an electric field of each transistor is prevented from flowing into the PD 151, and a noise is prevented from occurring.
Further, in the solid-state image sensing device 101a, the joining interface S between the first semiconductor substrate 201 and the second semiconductor substrate 202 can be arranged only at any position in the channel of the TRX 152 for all the pixels. Further, in an image sensor with more than hundreds of thousands of pixels, the joining interface S can be arranged at the same position in the channel of the TRX 152 for all the pixels. Further, a joining interface may not be formed inside the PD 151, inside the MEM 154, inside the FD 156, and inside the transistors other than the TRX 152.
Further, the joining interface S can be formed near the drain end of the channel of the TRX 152 in the solid-state image sensing device 101a. Thereby, a deterioration in charge transfer performance is restricted and life of devices or resistance of gate oxide films can be enhanced.
Further, parasitic resistance is caused in the joining interface S, and the parasitic resistance is to be a cause of leak current. The parasitic resistance is represented by parasitic resistance Rp in
Here, in a case where the TRX 152 is off, a current does not flow into the parasitic resistance Rp, and a noise does not occur. On the other hand, in a case where the TRX 152 is on, a noise due to the parasitic resistance Rp can occur in a signal by the charges transferred from the PD 151 to the MEM 154. However, the channel of the TRX 152 is configured in the HAD structure or the switching speed of the TRX 152 is further increased so that the signal transferred from the PD 151 to the MEM 154 is sufficiently larger for a noise caused due to the parasitic resistance Rp. Thus, a solution such as improving the channel structure of the TRX 152 or the switching speed can sufficiently decrease the effects of noises due to the leak current.
Further, in the solid-state image sensing device 101a, each transistor configuring each pixel, the MEM 154, and the FD 156 are formed in the second semiconductor substrate 202 as monocrystal substrate. Therefore, the excellent I-V property compatible with fine pixel signals can be obtained, thereby restricting a variation in performance per pixel.
A second embodiment of the present technology will be described below with reference to
The solid-state image sensing device 101b in
As described above with reference to
A third embodiment of the present technology will be described below with reference to
The solid-state image sensing device 101c in
Additionally, the light blocking film 401 is made of the same material as the light blocking film 219, for example.
Further, the light blocking film 401 is formed by forming the insulative film 214 in the step in
That is, the light blocking film 401 is formed from the light receiving surface side of the N− type semiconductor region 216 configuring the PD 151, and the vertical light blocking part 219B is formed from the upper surface side of the N− type semiconductor region 216, which are finally joined.
A fourth embodiment of the present technology will be described below with reference to
The solid-state image sensing device 101d in
The light blocking film 411 prevents a light emitted when a transistor in the logic layer 203 is operated from being incident in the device forming surface of the second semiconductor substrate 202, for example. Thereby, for example, a light from a transistor in the logic layer 203 is prevented from being incident in the P type semiconductor region 228, charges are prevented from being generated, the generated charges are prevented from being mixed into the N+ type semiconductor region 231, and a noise is prevented from occurring. Further, a noise due to an electric field caused by the logic layer 203 can be prevented.
A fifth embodiment of the present technology will be described below with reference to
The solid-state image sensing device 101e in
The solid-state image sensing device 101e is lower in the light blocking performance between adjacent pixels than the solid-state image sensing device 101b due to the absence of the vertical light blocking part 219B. However, an incident light into an adjacent pixel can be sufficiently blocked only by the insulative film 220, thereby restricting noises such as mixed color from occurring.
A sixth embodiment of the present technology will be described below with reference to
The sixth embodiment is different from the first embodiment and the like described above in that the configuration of the cross section of a pixel is different.
{Exemplary Configuration of Solid-State Image Sensing Device 101f}
The insulative film 214, the planarizing film 212, and the micro lens 211 are stacked on the lower surface of an N− type semiconductor region 451 in the first semiconductor substrate 201. A P+ type semiconductor region 452 is formed on the N− type semiconductor region 451. The PD 151 is configured of the N− type semiconductor region 451 and the P+ type semiconductor region 452.
A light incident in a light receiving surface of the solid-state image sensing device 101f is photoelectrically converted by the PD 151, and charges generated by the photoelectric conversion are accumulated in the N− type semiconductor region 451.
The light blocking film 213 is formed between the PDs 151 in adjacent pixels (the N− type semiconductor region 451 and the P+ type semiconductor region 452) on the lower surface of the insulative film 214.
Further, the upper surface and the side surface of the PD 151 (the N− type semiconductor region 451 and the P+ type semiconductor region 452) are surrounded by a light blocking film 453. The light blocking film 453 is made of the same material as the light blocking film 219 in
The horizontal light blocking part 453A has a planar shape parallel to the light receiving surface of the solid-state image sensing device 101f. The horizontal light blocking part 453A covers the upper surfaces of the N− type semiconductor region 451 and the P+ type semiconductor region 452 configuring the PD 151 except an opening 453C. Further, the horizontal light blocking part 453A is arranged over the entire region of the pixel array part 111 except the opening 453C in each pixel like the horizontal light blocking part 453A according to the tenth embodiment described below with reference to
The vertical light blocking part 453B has a wall shape vertical to the light receiving surface of the solid-state image sensing device 101f. The vertical light blocking part 453B is formed to surround the side surfaces of the N− type semiconductor region 451 and the P+ type semiconductor region 452 configuring the PD 151. Further, the vertical light blocking part 453B is arranged to extend over a plurality of pixels in the column direction between columns of pixels adjacent in the row direction in the pixel array part 111 like the vertical light blocking part 804B according to the tenth embodiment described below with reference to
The opening 453C is provided for inserting the vertical terminal (electrode) part 152AB of the gate terminal (electrode) 152A of the TRX 152 into the N− type semiconductor region 451 and transferring the charges accumulated in the N− type semiconductor region 451 to an N+ type semiconductor region 468.
A light which is not absorbed in the PD 151 and passes therethrough is reflected on the horizontal light blocking part 453A, and is prevented from invading in an upper surface than the horizontal light blocking part 453A. Thereby, for example, the charges generated by the light passing through the PD 151 are prevented from invading in the N+ type semiconductor region 468 configuring the MEM 154 or an N++ type semiconductor region 462 configuring the FD 156, and a noise is prevented from occurring. Further, the vertical light blocking part 453B prevents a light incident from an adjacent pixel from leaking into the PD 151, and a noise such as mixed color from occurring.
Additionally, the opening 453C is desirably as small as possible such that a light passing through the PD 151 does not pass. Further, the opening 453C is desirably arranged at an end of the pixel (near the vertical light blocking part 453B) in order to prevent an oblique light with a large incident angle from passing.
The light blocking film 453 is covered with an insulative film 454. The insulative film 454 is made of a silicon oxide film (SiO), for example. The insulative film 454 is covered with a P++ type semiconductor region 455. An N++ type semiconductor region 456 is formed between the insulative film 454 and the P++ type semiconductor region 455 below the horizontal light blocking part 453A and around the vertical light blocking part 453B. A gettering effect is caused by the N++ type semiconductor region 456. A stopper film 457 is formed between the insulative film 454 and the P++ type semiconductor region 455 above the horizontal light blocking part 453A. The stopper film 457 is made of a SiN film or SiCN film, for example.
The gate terminal (electrode) 152A of the TRX 152, the gate terminal (electrode) 153A of the TRM 153, the gate terminal (electrode) 155A of the TRG 155, the gate terminal (electrode) 157A of the OFG 157, and the gate terminal (electrode) 158A of the RST 158 are formed on the device forming surface of the second semiconductor substrate 202 via an insulative film 469. The gate terminals (electrodes) 153A, 155A, 157A, and 158A are arranged above the horizontal light blocking part 453A, and the gate terminal (electrode) 152A is arranged above the opening 453C of the light blocking film 453.
The gate terminal (electrode) 152A of the TRX 152 is configured of the horizontal terminal (electrode) part 152AA and the vertical terminal (electrode) part 152AB. The horizontal terminal (electrode) part 152AA is formed on the device forming surface of the second semiconductor substrate 202 via the insulative film 469 like the gate terminals (electrodes) of other transistors. The vertical terminal (electrode) part 152AB extends vertically downward from the horizontal terminal (electrode) part 152AA, penetrates through the second semiconductor substrate 202, and extends into the N− type semiconductor region 451 via the opening 453C of the light blocking film 453. Further, the vertical terminal (electrode) part 152AB is covered with the insulative film 469. Thus, the gate terminal (electrode) 152A contacts the N− type semiconductor region 451 via the insulative film 469.
An N++ type semiconductor region 459, an N+ type semiconductor region 460, an N+ type semiconductor region 461, the N++ type semiconductor region 462, an N+ type semiconductor region 463, a P−− type semiconductor region 464, a P− type semiconductor region 465, an N+ type semiconductor region 466, and an N++ type semiconductor region 467 are formed around the surface of the P-type semiconductor region 458 in the second semiconductor substrate 202 above the horizontal light blocking part 453A.
The P type semiconductor region 458 is arranged at least from around the right end of the horizontal terminal (electrode) part 152AA of the TRX 152 to around the right end of the gate terminal (electrode) 155A of the TRG 155. Therefore, the P type semiconductor region 458 is arranged at least immediately below the gate terminal (electrode) 153A of the TRM 153 and immediately below the gate terminal (electrode) 155A of the TRG 155.
The N++ type semiconductor region 459 is arranged on the right of the gate terminal (electrode) 158A of the RST 158 thereby to configure the charge discharging unit.
The N+ type semiconductor region 460 is arranged on the right of the gate terminal (electrode) 158A of the RST 158 and adjacently on the left of the N++ type semiconductor region 459.
The N+ type semiconductor region 461 is arranged on the left of the gate terminal (electrode) 158A of the RST 158.
The N++ type semiconductor region 462 is arranged adjacently on the left of the N+ type semiconductor region 461 thereby to configure the FD 156.
The N+ type semiconductor region 463 is arranged on the right of the gate terminal (electrode) 155A of the TRG 155 and adjacently on the left of the N++ type semiconductor region 462.
The P−− type semiconductor region 464 is arranged immediately below the gate terminal (electrode) 152A of the TRX 152. Further, the P−− type semiconductor region 464 surrounds the vertical terminal (electrode) part 152AB of the TRX 152 except the tip thereof via the insulative film 469.
The P− type semiconductor region 465 is arranged from around the left side of the gate terminal (electrode) 152A to around the right end of the gate terminal (electrode) 157A.
The N+ type semiconductor region 466 is arranged on the left of the gate terminal (electrode) 157A and adjacently on the left of the P− type semiconductor region 465.
The N++ type semiconductor region 467 is arranged adjacently on the left of the N+ type semiconductor region 466 thereby to configure the charge discharging unit.
The N+ type semiconductor region 468 is formed inside the P type semiconductor region 458 above the horizontal light blocking part 453A. The N+ type semiconductor region 468 spreads from around the left end of the gate terminal (electrode) 155A to around the left end of the gate terminal (electrode) 153A. The N+ type semiconductor region 468 configures the HAD-type MEM 154.
{Example of How to Drive Solid-State Image Sensing Device 101f}
How to drive the solid-state image sensing device 101f will be described below with reference to the potential diagram of
At first, the TRX 152 and the OFG 157 are turned on, and the TRM 153, the TRG 155, and the RST 158 are turned off. The charges accumulated in the PD 151 (the N− type semiconductor region 451) are then transferred to the N++ type semiconductor region 467 as charge discharging unit via the TRX 152 and the OFG 157 to be discharged to the outside. Thereby, the PD 151 is reset.
Then, the TRX 152 and the OFG 157 are turned off, and the TRG 155 and the RST 158 are turned on. The charges accumulated in the MEM 154 (the N+ type semiconductor region 468) and the FD 156 (the N++ type semiconductor region 462) are then transferred to the N++ type semiconductor region 459 as charge discharging unit via the TRG 155 and the RST 158 to be discharged to the outside. Thereby, the MEM 154 and the FD 156 are reset.
Then, the TRG 155 and the RST 158 are turned off and a light exposure period starts. During the light exposure period, the PD 151 (the N− type semiconductor region 451) generates and accumulates the charges depending on the amount of received light. Here, a potential difference due to a difference in impurity concentration is between the P type semiconductor region 458 and the P− type semiconductor region 465, and thus when the TRX 152, the TRM 153, and the OFG 157 are off, the potential of the channel of the OFG 157 is slightly lower than the potential of the channel of the TRM 153 closer to the TRX 152. Thereby, an overflow path is formed between the PD 151 (the N− type semiconductor region 451) and the N++ type semiconductor region 467 as charge discharging unit. Thus, the charges overflowed from the PD 151 (the N−type semiconductor region 451) are discharged to the N++ type semiconductor region 467 via the overflow path without leaking into the MEM 154 (the N+ type semiconductor region 468).
Then, the TRX 152 and the TRM 153 are turned on and the light exposure period ends. Here, a potential difference due to a difference in impurity concentration is between the P−− type semiconductor region 464 and the N+ type semiconductor region 468, and thus when the TRX 152 and the TRM 153 are turned on, the potential of the channel of the TRM 153 is lower than the potential of the channel of the TRX 152. Thereby, the charges accumulated in the PD 151 (the N− type semiconductor region 451) during the light exposure period are transferred to and held in the MEM 154 (the N+ type semiconductor region 468) via the TRX 152 and the TRM 153.
Then, the TRX 152 and the TRM 153 are turned off and the TRG 155 is turned on. Thereby, the charges held in the MEM 154 (the N+ type semiconductor region 468) are transferred to the FD 156 (the N++ type semiconductor region 462) via the TRM 153 and the TRG 155. The potential of the FD 156 is then output as signal level to the vertical signal line VSL via the AMP 159 and the SEL 160.
Additionally, the solid-state image sensing device 101f can produce the similar effects to the solid-state image sensing device 101a in
A seventh embodiment of the present technology will be described below with reference to
While there has been described the solid-state image sensing device 101a in which each device such as transistor configuring a pixel is in a planar structure, the seventh embodiment will be described assuming that each device is in a mesa structure.
The arrangement of each device in the solid-state image sensing device 101g in
In the planar structure in
In the exemplary configuration of
The exemplary configuration of
Additionally, in a case where the TRM 153 and the TRG 155 have the configuration of
The exemplary configuration of
The exemplary configuration of
Additionally, the transistors in the mesa structure are employed so that the response speed of each transistor can be increased, the transistors can be completely insulated from each other, and a noise can be prevented from being mixed. Further, the AMP 159 is in the mesa structure thereby to reduce random noises. Further, the FD 156 is in the mesa structure thereby to improve the charge transfer speed.
An eighth embodiment of the present technology will be described below with reference to
The eighth embodiment is different from the first embodiment and others described above in the circuit configuration and cross section configuration of a pixel.
{Exemplary Configuration of Solid-State Image Sensing Device 101h}
The circuit configuration of
The insulative film 214, the planarizing film 212, and the micro lens 211 are stacked on the lower surface of an N− type semiconductor region 601 in the first semiconductor substrate 201. A P+ type semiconductor region 602 is formed on the N−type semiconductor region 601. The PD 151 is configured of the N− type semiconductor region 601 and the P+ type semiconductor region 602.
A light incident in a light receiving surface of the solid-state image sensing device 101h is photoelectrically converted by the PD 151, and the charges generated by the photoelectric conversion are accumulated in the N− type semiconductor region 601.
The light blocking film 213 is formed between the PDs 151 (the N− type semiconductor region 601 and the P+ type semiconductor region 602) in adjacent pixels on the lower surface of the insulative film 214.
Further, the upper surface of the PD 151 (the N− type semiconductor region 601 and the P+ type semiconductor region 602) is surrounded by a light blocking film 603. The light blocking film 603 is made of the same material as the light blocking film 453 in
The light blocking film 603 has a planar shape parallel to the light receiving surface of the solid-state image sensing device 101f. The light blocking film 603 covers the upper surface of the N− type semiconductor region 601 and the P+ type semiconductor region 602 configuring the PD 151 except an opening 603A and an opening 603B. Further, the light blocking film 603 is arranged over the entre pixel array part 111 except the opening 603A and the opening 603B in each pixel like the horizontal light blocking part 804A according to the tenth embodiment described below with reference to
The opening 603A is provided for inserting the vertical terminal (electrode) part 152AB of the gate terminal (electrode) 152A of the TRX 152 into the N− type semiconductor region 601 and transferring the charges accumulated in the N− type semiconductor region 601 to the N+ type semiconductor region 468.
The opening 603B is provided for inserting the vertical terminal (electrode) part 157AB of the gate terminal (electrode) 157A of the OFG 157A into the N− type semiconductor region 601 and transferring the charges accumulated in the N− type semiconductor region 601 to the N++ type semiconductor region 467.
A light which is not absorbed in the PD 151 and passes therethrough is reflected on the light blocking film 603 and is prevented from invading in an upper layer than the light blocking film 603. Thereby, the charges caused by the light passing through the PD 151 are prevented from invading in the N+ type semiconductor region 468 configuring the MEM 154 or the N++ type semiconductor region 462 configuring the FD 156, and a noise is prevented from occurring, for example.
Additionally, the opening 603A and the opening 603B are desirably as small as possible such that a light passing through the PD 151 does not pass.
The light blocking film 603 is covered with an insulative film 604. The insulative film 604 is made of a silicon oxide film (SiO), for example. The insulative film 604 is covered with a P++ type semiconductor region 605. An N++ type semiconductor region 606 is formed between the lower surface of the insulative film 604 and the P++ type semiconductor region 605. A gettering effect is caused by the N++ type semiconductor region 606. A stopper film 607 is formed between the insulative film 604 and the P++ type semiconductor region 605 above the light blocking film 603. The stopper film 607 is made of a SiN film or SiCN film, for example.
The gate terminal (electrode) 152A of the TRX 152, the gate terminal (electrode) 155A of the TRG 155, the gate terminal (electrode) 157A of the OFG 157, and the gate terminal (electrode) 158A of the RST 158 are formed on the device forming surface of the second semiconductor substrate 202 via an insulative film 611. The gate terminals (electrodes) 155A and 158A are arranged above the light blocking film 603, the gate terminal (electrode) 152A is arranged above the opening 603A of the light blocking film 603, and the gate terminal (electrode) 157A is arranged above the opening 603B of the light blocking film 603.
The gate terminal (electrode) 152A of the TRX 152 is configured of the horizontal terminal (electrode) part 152AA and the vertical terminal (electrode) part 152AB. The horizontal terminal (electrode) part 152AA is formed on the device forming surface of the second semiconductor substrate 202 via the insulative film 611 like the gate terminals (electrodes) of other transistors. The vertical terminal (electrode) part 152AB extends vertically downward from the horizontal terminal (electrode) part 152AA, penetrates through the second semiconductor substrate 202, and extends into the N− type semiconductor region 601 via the opening 603A of the light blocking film 603. Further, the vertical terminal (electrode) part 152AB is covered with the insulative film 611. Therefore, the gate terminal (electrode) 152A contacts the N− type semiconductor region 601 via the insulative film 611.
The OFG 157 is in the vertical gate structure, and the gate terminal (electrode) 152A is configured of the horizontal terminal (electrode) part 157AA and the vertical terminal (electrode) part 157AB. The horizontal terminal (electrode) part 152AA is formed on the device forming surface of the second semiconductor substrate 202 via the insulative film 611 like the gate terminals (electrodes) of other transistors. The vertical terminal (electrode) part 157AB extends vertically downward from the horizontal terminal (electrode) part 157AA, penetrates through the second semiconductor substrate 202, and extends into the N− type semiconductor region 601 via the opening 603B of the light blocking film 603. Further, the vertical terminal (electrode) part 157AB is covered with the insulative film 611. Therefore, the gate terminal (electrode) 157A contacts the N− type semiconductor region 601 via the insulative film 611.
Therefore, the TRX 152 and the OFG 157 are electrically connected via the N− type semiconductor region 601.
The N++ type semiconductor region 459, the N+ type semiconductor region 460, the N+ type semiconductor region 461, the N++ type semiconductor region 462, the N+ type semiconductor region 463, a P+ type semiconductor region 609, a P−− type semiconductor region 610, the N+ type semiconductor region 466, and the N++ type semiconductor region 467 are formed around the surface of the P type semiconductor region 608 in the second semiconductor substrate 202 above the light blocking film 603.
The P+ type semiconductor region 609 is arranged between the horizontal terminal (electrode) part 152AA of the TRX 152 and the horizontal terminal (electrode) part 157AA of the OFG 157.
The P−− type semiconductor region 610 is arranged immediately below the horizontal terminal (electrode) part 157AA of the OFG 157. Further, the P−− type semiconductor region 610 surrounds the vertical terminal (electrode) part 157AB of the OFG 157 except the tip thereof via the insulative film 611.
The exemplary configuration of a pixel in
{Example of How to Drive Solid-State Image Sensing Device 101h}
How to drive the solid-state image sensing device 101h will be described below with reference to the potential diagram of
At first, the OFG 157 is turned on, and the TRX 152, the TRG 155, and the RST 158 are turned off. The charges accumulated in the PD 151 (the N− type semiconductor region 601) are then transferred to the N++ type semiconductor region 467 as charge discharging unit via the OFG 157 to be discharged to the outside. Thereby, the PD 151 is reset.
Then, the OFG 157 is turned off, and the TRG 155 and the RST 158 are turned on. Then, the charges accumulated in the MEM 154 (the N+ type semiconductor region 468) and the FD 156 (the N++ type semiconductor region 462) are transferred to the N++ type semiconductor region 459 as charge discharging unit via the TRG 155 and the RST 158 to be discharged to the outside. Thereby, the MEM 154 and the FD 156 are reset.
The TRG 155 and the RST 158 are then turned off, and a light exposure period starts. During the light exposure period, the PD 151 (the N− type semiconductor region 601) generates and accumulates the charges depending on the amount of received light. Here, when the TRX 152 and the OFG 157 is off, the potential of the channel of the OFG 157 is set to be slightly lower than the potential of the channel of the TRX 152. Thereby, an overflow path is formed between the PD 151 (the N− type semiconductor region 601) and the N++ type semiconductor region 467 as charge discharging unit. Therefore, the charges overflowed from the PD 151 (the N− type semiconductor region 601) are discharged to the N++ type semiconductor region 467 via the overflow path without leaking into the MEM 154 (the N+ type semiconductor region 468).
The TRX 152 is then turned on and the light exposure period ends. Thereby, the charges accumulated in the PD 151 (the N− type semiconductor region 601) during the light exposure period are transferred to and held in the MEM 154 (the N+ type semiconductor region 468) via the TRX 152.
Then, the TRX 152 is turned off and the TRG 155 is turned on. Thereby, the charges held in the MEM 154 (the N+ type semiconductor region 468) are transferred to the FD 156 (the N++ type semiconductor region 462) via the TRG 155. The potential of the FD 156 is then output as signal level to the vertical signal line VSL via the AMP 159 and the SEL 160.
Additionally, the solid-state image sensing device 101h can produce the effects almost similar to the solid-state image sensing device 101a in
A ninth embodiment of the present technology will be described below with reference to
The solid-state image sensing device 101i in
The first layer 701A is configured to include the pixel array part 702, the vertical drive unit 112, the ramp wave module 113, the clock module 114, and the horizontal drive unit 116. The vertical drive unit 112, the ramp wave module 113, the clock module 114, and the horizontal drive unit 116 are formed on the device forming surface of the second semiconductor substrate 202 as monocrystal silicon substrate by use of the devices in the mesa structure, for example. Further, the pixel ADC (A/D converter) processing unit arranged in the pixel array part 702 is also formed on the device forming surface of the second semiconductor substrate 202 as monocrystal silicon substrate by use of the devices in the mesa structure, for example. Furthermore, the ADC for AD converting a pixel signal of each pixel in the pixel array part 702 is provided per pixel.
The second layer 701B is configured to include a latch circuit 703, the data storage unit 115, the system control unit 117, and the signal processing unit 118. The latch circuit 703 is arranged at a position corresponding to the ADC provided per pixel in the pixel array part 702.
Further, the first layer 701A is joined with the second layer 701B via Cu—Cu joining, for example.
The advantages of an ADC provided per pixel will be described herein with reference to
Here, as illustrated, wiring resistance and parasitic capacitance are caused in the wiring between each pixel and an ADC. Further, the wiring resistance and the parasitic capacitance are different between the pixels in the upper stage and the pixels in the lower stage in the Figure since the distances of the wirings between the pixels in the same column and the ADC are different. For example, the wiring resistance and the parasitic capacitance are different between the pixel P(1, 1) and the pixel P(m, 1), for example. Thus, a time constant of the wiring between a pixel and an ADC is different among the pixels in the same column.
Therefore, a noise such as transverse thread or vertical shading easily occurs on a shot image. Further, the amplification rate of the amplification transistors 712-1 to 712-n needs to be increased in order to reduce the effects of signal loss due to the wiring resistance and the parasitic capacitance of a pixel signal flowing on the bit line. Therefore, the consumed power in the amplification transistors 712-1 to 712-n increases, and thus the drive frequency is difficult to increase.
On the other hand,
In this case, the wiring resistance and the parasitic capacitance caused in the wiring between each pixel and an ADC are lower than in the example of
Thus, a noise such as transverse thread or vertical shading is reduced. Further, the time constant of the wiring decreases, which enables high-speed drive using a high-frequency clock. Furthermore, the amplification rate of the amplification transistors 712-1 to 712-n can be reduced due to the decrease in noise, thereby reducing the consumed power.
Additionally, an ADC can be provided not per pixel but per pixels in the solid-state image sensing device 101i as illustrated in
In the example, the four pixels P1 to P4 share the FD 156, the RST 158, the AMP 159, the SEL 160, and an ADC circuit 751. Further, the ADC circuit 751 is configured of transistors TR1 to TR8. A digital signal output from the ADC circuit 751 is supplied to the latch circuit 703.
Therefore, the charges held in the MEMs 154 in the pixels P1 to P4 are transferred to the FD 156 in turn, and a pixel signal corresponding to the charges held in the FD 156 is supplied to the ADC circuit 751 via the AMP 159 and the SEL 160.
Additionally, the example of
The pixel P1 to the pixel P4 are arranged to be adjacent to each other. The pixel P1 and the pixel P2 are adjacent in the lateral direction in the Figure, and the layouts in the pixels are symmetric to each other. The pixel P3 and the pixel P4 are adjacent in the lateral direction in the Figure, and the layouts in the pixels are symmetric to each other. The pixel P1 and the pixel P3 are adjacent in the longitudinal direction in the Figure, and the layouts in the pixels are vertically symmetric to each other. The pixel P2 and the pixel P4 are adjacent in the longitudinal direction in the Figure, and the layouts in the pixels are vertically symmetric to each other.
The AMP 159 is arranged adjacently on the right of the pixel P2 in the Figure. The SEL 160 is arranged above the AMP 159A in the Figure.
The ADC circuit 751 is arranged upward adjacent to the pixel P1 and the pixel P2 in the Figure. Further, each transistor configuring the ADC circuit 751 is assumed to be in the mesa structure as described above, for example.
In this way, the ADC circuit 751 is shared among a plurality of pixels so that the effects almost similar to those in a case where the ADC is provided per pixel can be obtained and the device can be downsized.
A tenth embodiment of the present technology will be described below with reference to
{Exemplary Configuration of Solid-State Image Sensing Device 101j}
An N− type semiconductor region 802 and an N type semiconductor region 803 configuring the PD 151 are embedded in a semiconductor substrate 801 in the solid-state image sensing device 101j. A light incident in the light receiving surface of the solid-state image sensing device 101j is photoelectrically converted in the N− type semiconductor region 802, and the generated charges are accumulated in the N type semiconductor region 803.
Additionally, a definite border line as illustrated in the Figure is not necessarily provided between the N− type semiconductor region 802 and the N type semiconductor region 803, and an N type impurity concentration gradually increases from the N− type semiconductor region 802 toward the N type semiconductor region 803, for example.
The upper surface and the side surface of the PD 151 (the N− type semiconductor region 802 and the N type semiconductor region 803) are surrounded by a light blocking film 804. More specifically, the light blocking film 804 is configured of the horizontal light blocking part 804A, the vertical light blocking part 804B, a vertical light blocking part 804C, and a horizontal light blocking part 804D (
The horizontal light blocking part 804A has a planar shape parallel to the light receiving surface of the solid-state image sensing device 101j. The horizontal light blocking part 804A covers the upper surfaces of the N− type semiconductor region 802 and the N type semiconductor region 803 configuring the PD 151 except an opening 804E.
The vertical light blocking part 804B has a wall shape vertical to the light receiving surface of the solid-state image sensing device 101j. The vertical light blocking part 804B is formed to surround the side surfaces of the N− type semiconductor region 802 and the N type semiconductor region 803 configuring the PD 151.
The vertical light blocking part 804C is arranged around the border between the horizontal light blocking part 804A and the opening 804E, and has a wall shape vertical to the light receiving surface. The vertical light blocking part 804C is formed opposite to the vertical light blocking part 804B (closer to an N type semiconductor region 808) with reference to the horizontal light blocking part 804A in a direction vertical to the horizontal light blocking part 804A. Further, the vertical light blocking part 804C is formed at a different position from the vertical light blocking part 804B in a direction parallel to the horizontal light blocking part 804A. Furthermore, the vertical light blocking part 804C is formed to block a light at least between the vertical terminal (electrode) part 152AB of the TRX 152 and the N type semiconductor region 808 configuring the MEM 154.
The horizontal light blocking part 804D will be described below.
The opening 804E is provided for inserting the vertical terminal (electrode) part 152AB of the TRX 152 into the N− type semiconductor region 802 and transferring the charges accumulated in the N type semiconductor region 803 to the N type semiconductor region 808.
Additionally, the opening 804E is desirably as small as possible such that a light passing through the PD 151 does not pass. Further, the opening 804E is desirably arranged at an end of the pixel (near the vertical light blocking part 804B) in order to prevent an oblique light with a large incident angle from passing.
Additionally, at least one of the vertical light blocking part 804C and the horizontal light blocking part 804D may not be formed.
The light blocking film 804 is covered with an insulative film 805. The insulative film 805 employs a high dielectric film made of HfO2, TaO2, Al2O3, or the like with high dielectric constant, for example.
The surrounding of the light blocking film 804 and the lower surface of the N− type semiconductor region 802 are covered with a P type semiconductor region 806 as conductive layer reverse to signal charge. The thickness of the P type semiconductor region 806 is almost uniform, and is assumed to be within 20 nm, for example. The P type semiconductor region 806 has as high an impurity concentration as possible to restrict charges from occurring at a defect level present at an interface between the light blocking film 804 and the semiconductor substrate 801, and works as a pinning layer.
Additionally, the insulative film 805 is made of a high dielectric film, and has a predetermined potential, thereby enhancing the pinning effect of the P type semiconductor region 806. Further, a potential is directly given to the light blocking film 804 from the outside, thereby obtaining a similar effect.
The gate terminal (electrode) 152A of the TRX 152 and the gate terminal (electrode) 155A of the TRG 155 are formed on the upper surface (the device forming surface) of the semiconductor substrate 801. The gate terminal (electrode) 155A is arranged above the horizontal light blocking part 804A, and the gate terminal (electrode) 152A is arranged above the opening 804E of the light blocking film 804.
The gate terminal (electrode) 152A of the TRX 152 is configured of the horizontal terminal (electrode) part 152AA and the vertical terminal (electrode) part 152AB. The horizontal terminal (electrode) part 152AA is formed on the upper surface (the device forming surface) of the semiconductor substrate 801 like the gate terminal (electrode) 155A. The vertical terminal (electrode) part 152AB extends vertically downward from the horizontal terminal (electrode) part 152AA, and extends into the N− type semiconductor region 802 via the opening 804E of the light blocking film 804.
A P type semiconductor region 807, an N− type semiconductor region 809, and a P+ type semiconductor region 810 are formed around the surface of the semiconductor substrate 801 above the horizontal light blocking part 219A.
The P type semiconductor region 807 is arranged on the right of the vertical terminal (electrode) part 152AB of the TRX 152 and immediately below the horizontal terminal (electrode) part 152AA.
The N− type semiconductor region 809 is arranged on the right of the gate terminal (electrode) 155A of the TRG 155 thereby to configure the FD 156.
The P+ type semiconductor region 810 is arranged between the vertical terminal (electrode) part 152AB of the TRX 152 and the N− type semiconductor region 809.
The N type semiconductor region 808 is arranged immediately below the P type semiconductor region 807 thereby to configure the MEM 152. The vertical light blocking part 804C is arranged between the vertical terminal (electrode) part 152AB of the gate terminal (electrode) 152A and the N type semiconductor region 808.
When the drive signal TRX applied to the gate terminal (electrode) 152A of the TRX 152 is turned on and the TRX 152 is turned on, a channel is formed between the N− type semiconductor region 802 (the PD 151) and the N type semiconductor region 808 (the MEM 154). The charges accumulated in the N type semiconductor region 803 are then transferred to the N type semiconductor region 808 via the channel, and held in the N type semiconductor region 808.
Further, when the drive signal TRG applied to the gate terminal (electrode) 155A of the TRG 155 is turned on and the TRG 155 is turned on, a channel is formed between the N type semiconductor region 808 (the MEM 154) and the N− type semiconductor region 809 (the FD 156). The charges held in the N type semiconductor region 808 are then transferred to the N− type semiconductor region 809 via the channel. The potential of the N− type semiconductor region 809 is then output as signal level to the vertical signal line VSL via the AMP 159 and the SEL 160 (not illustrated).
Further, as illustrated in
Furthermore, as illustrated in
Therefore, a light which is not absorbed in the PD 151 and passes therethrough is reflected on the horizontal light blocking part 804A and is prevented from invading in an upper layer than the horizontal light blocking part 804A. Even if a light which is not absorbed in the PD 151 and passes therethrough passes through the opening 804E of the light blocking film 804, the vertical light blocking part 804C prevents the light from invading toward the N type semiconductor region 808 configuring the MEM 154. Thereby, for example, the charges generated by the light passing through the PD 151 are prevented from invading in the N type semiconductor region 808 configuring the MEM 154 or the N− type semiconductor region 809 configuring the FD 156, and a noise is prevented from occurring. Further, the vertical light blocking part 804B prevents a light incident from an adjacent pixel from leaking into the PD 151, and a noise such as mixed color from occurring.
Further, the channel formed on the surface of the semiconductor substrate 801 immediately below the horizontal terminal (electrode) part 152AA of the gate terminal (electrode) 152A can be formed to be shallower than the N type semiconductor region 808, the P+ type semiconductor region 810, and the like. Thus, the thickness of the horizontal light blocking part 804A can be adjusted or the vertical light blocking part 804C can be provided below the horizontal terminal (electrode) part 152AA. Thereby, the charges can be further prevented from leaking into the N type semiconductor region 808 or the N− type semiconductor region 809.
Furthermore, a region in which the gate terminal (electrode) 152A contacts the insulative film is in a metal gate structure, thereby further enhancing the light blocking capability.
{Method for Manufacturing Solid-State Image Sensing Device 101j}
A method for manufacturing the solid-state image sensing device 101j will be described below with reference to
At first, as illustrated in
Then, the N− type semiconductor region 802 and the N type semiconductor region 803, which are the same conductive layers as signal charge, are formed on part of the pinning layer by ion implantation in order to form a depletion layer for performing photoelectric conversion.
Then, as illustrated in
Then, as illustrated in
Additionally,
Then, as illustrated in
Then, as illustrated in
Then, as illustrated in
Then, as illustrated in
Then, a metal film is embedded in the trench 853 by a method such as CVD, and the horizontal light blocking part 804A, the vertical light blocking part 804B, and the vertical light blocking part 804C of the light blocking film 804 are formed. Further, the horizontal light blocking part 804D is formed on the backside of the semiconductor substrate 801 to clog the inlet port of the trench 853. The horizontal light blocking part 804D is arranged to extend over a plurality of pixels in the column direction between columns of pixels adjacent in the row direction in the pixel array part 111, for example. Further, the horizontal light blocking part 804D is arranged to extend over a plurality of pixels in the row direction between rows of pixels adjacent in the column direction in the pixel array part 111, for example.
Additionally, at this time, a metal film for blocking a light in a pixel region for determining the black level of a pixel signal and part of a phase difference detection pixel may be formed.
Further, the insulative film 805 is formed on the backside of the semiconductor substrate 801.
An on-chip color filter 854, an on-chip micro lens 855, and the like are then formed on the backside of the semiconductor substrate 801, and the solid-state image sensing device 101j is completed as illustrated in
The solid-state image sensing device 101j can produce the effects almost similar to the solid-state image sensing device 101a described above.
Further, a joining interface between applied substrates is not present in the solid-state image sensing device 101j unlike the solid-state image sensing device 101a, and thus a defect level is not present in the channel of the TRX 152. Further, the PD 151, the TRX 152, the MEM 154, and the like are all made of monocrystal silicon. Therefore, bad charge transfer between the PD 151 and the MEM 154 can be prevented.
Further, the solid-state image sensing device 101j is provided with the vertical light blocking part 804C for blocking a light between the vertical terminal (electrode) part 152AB of the TRX 152 and the N type semiconductor region 808 configuring the MEM 154, thereby further enhancing the light blocking performance.
Furthermore, the P type semiconductor region 806 can be formed to be uniformly thin and the volume of the N− type semiconductor region 802 configuring the PD 151 can be increased in the solid-state image sensing device 101j. Consequently, the amount of saturation charges increases and the sensitivity is enhanced. Moreover, the obliquely-incident light property is enhanced.
Additionally, for example, in the step in
An eleventh embodiment of the present technology will be described below with reference to
{Exemplary Configuration of Solid-State Image Sensing Device 101k}
The solid-state image sensing device 101k is different from the solid-state image sensing device 101j according to the tenth embodiment of the present technology described above mainly in the cross section configuration and the manufacture method of a pixel.
The PD 151 is embedded around the backside of a semiconductor substrate 1001 in the solid-state image sensing device 101k. Further, the upper surface and the side surface of the PD 151 are covered with a light blocking film 1002. Specifically, the light blocking film 1002 is configured of a horizontal light blocking part 1002A and a vertical light blocking part 10028. Further, the light blocking film 1002 is made of the same material as the light blocking film 219 in
The horizontal light blocking part 1002A has a planar shape parallel to the light receiving surface of the solid-state image sensing device 101k. The horizontal light blocking part 1002A covers the upper surface of the PD 151 except an opening 1002C. Further, the horizontal light blocking part 1002A is arranged in the entire region of the pixel array part 111 except the opening 1002C in each pixel similarly to the horizontal light blocking part 804A according to the tenth embodiment described above with reference to
The vertical light blocking part 1002B has a wall shape vertical to the light receiving surface of the solid-state image sensing device 101k. The vertical light blocking part 1002B is formed to surround the side surface of the PD 151. Further, the vertical light blocking part 1002B is arranged to extend over a plurality of pixels in the column direction between columns of pixels adjacent in the row direction in the pixel array part 111 like the vertical light blocking part 804B according to the tenth embodiment described above with reference to
The opening 1002C is provided for inserting the vertical terminal (electrode) part 152AB of the gate terminal (electrode) 152A of the TRX 152 in the PD 151 and transferring the charges accumulated in the PD 151 to the MEM 154.
A light which is not absorbed in the PD 151 and passes therethrough is reflected on the horizontal light blocking part 1002A and is prevented from invading in an upper layer than the horizontal light blocking part 1002A. Thereby, for example, the charges generated by the light passing through the PD 151 are prevented from invading in the MEM 154 or the FD 156, and a noise is prevented from occurring. Further, the vertical light blocking part 1002B prevents a light incident from an adjacent pixel from leaking into the PD 151, and a noise such as mixed color from occurring.
Additionally, the opening 1002C is desirably as small as possible such that a light passing through the PD 151 does not pass. Further, the opening 1002C is desirably arranged at an end of the pixel (near the vertical light blocking part 1002B) in order to prevent an oblique light with a large incident angle from passing.
The gate terminal (electrode) of the TRX 152, the gate terminal (electrode) 155A of the TRG 155, and a gate terminal (electrode) 1005A of a pixel transistor are formed on the upper surface (a device forming surface) of the semiconductor substrate 1001. The gate terminal (electrode) 155A and the gate terminal (electrode) 1005A are arranged above the horizontal light blocking part 1002A, and the gate terminal (electrode) 152A is arranged above the opening 1002C of the light blocking film 1002.
The gate terminal (electrode) 152A of the TRX 152 is configured of the horizontal terminal (electrode) part 152AA and the vertical terminal (electrode) part 152AB. The horizontal terminal (electrode) part 152AA is formed on the device forming surface of the semiconductor substrate 1001 like the gate terminals (electrodes) of other transistors. The vertical terminal (electrode) part 152AB extends vertically downward from the horizontal terminal (electrode) part 152AA, and extends into the PD 151 via the opening 1002C of the light blocking film 1002.
The FD 156 and source drain regions (SD) 1003, 1004 are formed around the upper surface of the semiconductor substrate 1001 above the horizontal light blocking part 1002A. The FD 156 is arranged on the right of the gate terminal (electrode) 155A. The SD 1003 and the SD 1004 are arranged on both sides of the gate terminal (electrode) 1005A.
Further, the MEM 154 is formed slightly deeper than the upper surface of the semiconductor substrate 1001 immediately below the horizontal terminal (electrode) part 152AA of the gate terminal (electrode) 152A and above the horizontal light blocking part 1002A.
When the drive signal TRX applied to the gate terminal (electrode) 152A of the TRX 152 is turned on and the TRX 152 is turned on, a channel is formed between the PD 151 and the MEM 154. The charges accumulated in the PD 151 are then transferred to the MEM 154 via the channel and held in the MEM 154.
Further, when the drive signal TRG applied to the gate terminal (electrode) 155A of the TRG 155 is turned on and the TRG 155 is turned on, a channel is formed between the MEM 154 and the FD 156. The charges held in the MEM 154 are then transferred to the FD 156 via the channel. The potential of the FD 156 is then output as signal level to the vertical signal line VSL via the AMP 159 and the SEL 160 (not illustrated).
{Method for Manufacturing Solid-State Image Sensing Device 101k}
A method for manufacturing the solid-state image sensing device 101k will be described below with reference to
(First Manufacture Method)
A first method for manufacturing the solid-state image sensing device 101k will be first described with reference to
At first, as illustrated in
Then, as illustrated in
Further, the thickness of the sacrifice film 1103 is set to be 200 nm or more, for example, in consideration of the light blocking property and the visual property. Here, the visual property indicates a visual property of an alignment mark since part of the sacrifice film 1103 is not removed and remains and is used as alignment mark as described below.
Additionally, as illustrated in
The hard mask 1102 is then removed by wet etching as illustrated in
A silicon film 1104 is then formed on the upper surfaces of the semiconductor substrate 1101 and the sacrifice film 1103 by epitaxial growth as illustrated in
The silicon film 1104 is then polished to a predetermined thickness by CMP as illustrated in
A pixel circuit is then formed as illustrated in
A support substrate (not illustrated) is then applied on the wiring layer (not illustrated). Further, the backside of the semiconductor substrate 1001 is thinned up to around the surface of the PD 151 as illustrated in
Additionally,
A trench 1105 is then formed on the backside of the semiconductor substrate 1001 as illustrated in
Additionally, the trench 1105 is formed in a method similar to the method described above with reference to
Further, the trench 1105 is not formed in a region (such as scribe region) other than the pixel region.
The sacrifice film 1103 is then removed by wet etching using a predetermined solution as illustrated in
Additionally, a mixed solution of HF, H2O2, and CH3COOH is used for wet etching, for example.
Further, as described above, the trench 1105 is not formed in the region other than the pixel region. Thus, the sacrifice film 1103 is not removed by wet etching in the step in
The light blocking film 1002 is then generated as illustrated in
An insulative film (not illustrated) is then formed on the surface of the fixed charge film. The insulative film is made of a SiO2 film, for example.
The light blocking film 1002 is then embedded in the trench 1105 and the cavity 1106.
Then, as illustrated in
In the first manufacture method, an alignment mark of the solid-state image sensing device 101k can be formed as described above with reference to
In the solid-state image sensing device 101k, as described above, the silicon film 1104 is epitaxially grown on the upper surface of the SiGe-made sacrifice film 1103 in the step in
On the other hand, the steps up to the step of epitaxially growing the silicon film on the upper surface of the sacrifice film (the P+ type semiconductor region 851 in
Here, the boron-implanted silicon is poor in visual property, and is difficult to use for alignment mark. Further, when the concentration of boron is increased for higher visual property, many defects occur, and many defects occur in the silicon film to be epitaxially grown, and the quality is deteriorated.
Thus, after being pre-processed, the surface of the silicon film is masked by photoresist. Then, the alignment mark is machined, and then post-processed. Thereby, the alignment mark is formed in the square in a dotted line in the Figure.
In this way, the steps of manufacturing an alignment mark can be further reduced in the solid-state image sensing device 101k than in the solid-state image sensing device 101j.
Additionally, there will be herein discussed whether an alignment mark can be formed by removing the sacrifice film 1103 in a region where the alignment mark is to be formed similarly as in the pixel region with reference to
For example, the trench 1105 is formed around the opening 1103A of the sacrifice film 1103 in a circle in a dotted line in
Then, as illustrated in
Then, as illustrated in
Here, the remains 11038 and 1103C are not removed and remain in the region surrounded in the dotted line 1121. Thus, in a case where the region is used for an alignment mark, the shape of the mark varies and is not symmetric. Therefore, a deterioration in alignment mark recognition accuracy is assumed, and the region surrounded in the dotted line 1121 is considered not suitable for an alignment mark.
(Second Manufacture Method)
A second method for manufacturing the solid-state image sensing device 101k will be described below with reference to
At first, as illustrated in
Then, as illustrated in
The sacrifice film 1201 employs SiGe like the sacrifice film 1103 in the first manufacture method. Incidentally, the sacrifice film 1201 is adjusted such that the concentration of Ge is higher toward the center and lower toward the upper end and the lower end unlike the sacrifice film 1103. Thereby, the wet etching rate (WER) of the sacrifice film 1201 is higher toward the center and lower toward the upper end and the lower end.
Additionally, as illustrated in
Then, as illustrated in
Then, as illustrated in
Then, as illustrated in
Then, as illustrated in
Then, as illustrated in
Then, as illustrated in
Then, as illustrated in
Here, as described above, the sacrifice film 1201 is higher in WER toward the center, and lower in WER toward the upper end and the lower end. Thus, the cavity 1203 is thicker closer to the trench 1202, and thinner farther away from the trench 1202 after the sacrifice film 1201 is removed. That is, a cross section of the cavity 1203 is the thickest at the connection part with the trench 1202, and is tapered toward the ends.
The light blocking film 1002 is then generated as illustrated in
Here, a difference in the shape of the light blocking film 1002 between the first manufacture method and the second manufacture method will be described herein with reference to
In the first manufacture method, the thickness of the cross section of the cavity 1106 in which the horizontal light blocking part 1002A is formed is almost uniform as described above with reference to
Here, in a case where the light blocking film 1002 is embedded in the trench 1105 and the cavity 1106 in a method such as CVD, material gas or carrier gas is introduced from the inlet port of the trench 1105 into the trench 1105. At this time, the material gas or carrier gas may accumulate and may not sufficiently reach the inside of the cavity 1106. In particular, the material gas or carrier gas is less likely to reach closer to the ends of the cavity 1106 and farther away from the inlet port of the trench 1105. Consequently, for example, voids 1251 and 1252 are caused in the horizontal light blocking part 1002A as illustrated in the upper part of
On the other hand, in the second manufacture method, the cross section of the cavity 1203 in which the horizontal light blocking part 1002A is formed is tapered as described above with reference to
Here, in a case where the light blocking film 1002 is embedded in the trench 1202 and the cavity 1203 from the inlet port of the trench 1202 in a method such as CVD, material gas or carrier gas may accumulate and may not sufficiently reach the inside of the cavity 1203 as described above. In particular, the material gas or carrier gas is less likely to reach closer to the ends of the cavity 1203. However, since the cavity 1203 is tapered and the connection part with the trench 1202 is wider, the material gas or carrier gas is less accumulated. Further, the ends of the cavity 1203 are tapered, and thus even if the amount of gas to reach the ends of the cavity 1203 is reduced, the cavity 1203 can be embedded without any gap. Consequently, the horizontal light blocking part 1002A, which is tapered from the connection part with the vertical light blocking part 10028 toward the ends (the opening 1002C) and has no void, can be formed as illustrated in the lower part of
A relationship between the depth of the trench 1202 and the shape of the horizontal light blocking part 1002A will be described below with reference to
In a case where the trench 1202 is formed at a shallow position from the surface of the sacrifice film 1201, the shape of the cross section of the horizontal light blocking part 1002A is not tapered to be vertically symmetric, and is tapered toward the trench 1202 (the vertical light blocking part 1002B).
On the other hand, there is not a large difference in the shape of the horizontal light blocking part 1002A between in a case where the trench 1202 is formed up to the center of the sacrifice film 1201 and in a case where it is formed deeper than the sacrifice film 1201. That is, the shape of the cross section of the horizontal light blocking part 1002A is tapered to be almost vertically symmetric.
Returning to the description of the manufacture method, the planarizing film 1107, the on-chip color filter 1108, and the on-chip micro lens 1109, and the like are then formed on the backside of the semiconductor substrate 1101 similarly as in the step in
As described above, in the second manufacture method, the cross section of the horizontal light blocking part 1002A of the light blocking film 1002 is tapered, thereby forming the light blocking film 1002 without any void and with the excellent light blocking property.
The conditions for the thickness of the tapered horizontal light blocking part 1002A will be discussed herein.
The upper table in
For example, in a case where the horizontal light blocking part 1002A is made of W, the transmissivity is −50 dB or less for a thickness of 80 nm or more, and the transmissivity is −100 dB or less for a thickness of 180 nm or more. In a case where the horizontal light blocking part 1002A is made of Ti, the transmissivity is −50 dB or less for a thickness of 70 nm or more, and the transmissivity is −100 dB or less for a thickness of 140 nm or more. In a case where the horizontal light blocking part 1002A is made of Ta, the transmissivity is −50 dB or less for a thickness of 70 nm or more, and the transmissivity is −100 dB or less for a thickness of 150 nm or more. In a case where the horizontal light blocking part 1002A is made of Al, the transmissivity is −50 dB or less for a thickness of 40 nm or more, and the transmissivity is −100 dB or less for a thickness of 70 nm or more.
A minimum value Dmin of the horizontal light blocking part 1002A is then determined by the material of the horizontal light blocking part 1002A and the required light blocking performance. Additionally, the minimum value Dmin is assumed as a thickness not at the tip of the horizontal light blocking part 1002A but at a position slightly away from the tip.
For example, the minimum value Dmin is assumed as a thickness at a position away from the tip (the end of the opening 1002C) of the horizontal light blocking part 1002A by a predetermined distance.
Alternatively, for example, assuming a length from the connection part between the horizontal light blocking part 1002A and the vertical light blocking part 1002B to the tip of the horizontal light blocking part 1002A as L, the minimum value Dmin is assumed as a thickness at a position away from the tip of the horizontal light blocking part 1002A by a distance of LXx (%). x is set to be 10% or less, for example. More specifically, x is set at 0.5%, 1%, 3%, 5%, 7%, or 10%, for example.
For example, in a case where the horizontal light blocking part 1002A is made of W and the transmissivity is set at −50 dB or less, the minimum value Dmin of the horizontal light blocking part 1002A is set at 80 nm or more.
{Third Method for Manufacturing Solid-State Image Sensing Device 101k}
A third method for manufacturing the solid-state image sensing device 101k will be described below with reference to
A plurality of trenches, which are vertical to the surface of a silicon-made semiconductor substrate 1301, are first formed at predetermined intervals as illustrated in
An annealing processing using H2 gas is performed on the semiconductor substrate 1301 in
The surface of the semiconductor substrate 1301 is then drilled leading to the cavity 1301B as illustrated in
Additionally, the reinforcing film 1302 may be an oxide film such as SiO2, a High-k film, or a laminated film of High-k film and oxide film, for example.
For example, in a case where the semiconductor substrate 1301 in
A pixel circuit is then formed similarly as in the step in
Then, a support substrate (not illustrated) is applied similarly as in the step in
Additionally,
A trench 1301C is then formed on the backside of the semiconductor substrate 1301 similarly as in the step in
Further, the reinforcing film 1302 is removed by wet etching using a solution such as ammonium, and the cavity 1301B is formed again. At this time, the polysilicon 1303 formed after the formation of the reinforcing film 1302 is not removed and remains in the hole for forming the reinforcing film 1302 in the step in
The light blocking film 1002 is then generated as illustrated in
As described above with reference to
There will be described herein a difference in the structure between in a case where a cavity is formed on a semiconductor substrate by wet etching using a sacrifice film thereby to form the horizontal light blocking part 1002A as in the first manufacture method and in a case where a cavity is formed on a semiconductor substrate by use of the SON thereby to form the horizontal light blocking part 1002A as in the third manufacture method, for example, with reference to
In the former case, the shape of the cross section at the tip of the horizontal light blocking part 1002A (the end of the opening 1002C) is almost rectangular. On the other hand, in the latter case, the shape of the cross section at the tip of the horizontal light blocking part 1002A (the end of the opening 1002C) is not rectangular but rounded.
Further, in the latter case, the polysilicon 1303, which clogs the hole used for embedding the reinforcing film 1302, is formed on the surface of the semiconductor substrate 1301. On the other hand, in the former case, nothing corresponding to the polysilicon 1303 is formed on the surface of the semiconductor substrate 1101.
A twelfth embodiment of the present technology will be described below with reference to
{Exemplary Configuration of Solid-State Image Sensing Device 101l}
Additionally, the parts corresponding to those in
The solid-state image sensing device 101l in
The PD 151 in the solid-state image sensing device 101l is configured of a main body 151A and a protruded plug 151B.
The main body 151A has substantially the same shape as the PD 151 in the solid-state image sensing device 101k. The side surface of the main body 151A is surrounded by the vertical light blocking part 1002B of the light blocking film 1002. The upper surface of the main body 151A is covered with the horizontal light blocking part 1002A of the light blocking film 1002 except the opening 1002C.
The plug 151B extends vertically upward from the upper surface of the main body 151A, and extends from the horizontal light blocking part 1002A toward the MEM 154 via the opening 1002C of the light blocking film 1002. The tip of the plug 151B then reaches around the surface of the semiconductor substrate 1001.
On the other hand, the gate terminal (electrode) 152A of the TRX 152 is different from the gate terminal (electrode) 152A in the solid-state image sensing device 101k in that the vertical terminal (electrode) part 152AB is not provide and only the part corresponding to the horizontal terminal (electrode) part 152AA is provided.
Thus, even when an incident light is not absorbed in the main body 151A of the PD 151 and passes through the opening 1002C of the light blocking film 1002, it is absorbed in the plug 151B of the PD 151 in the solid-state image sensing device 101k. Thereby, the charges generated by the light passing through the opening 1002C of the light blocking film 1002 are prevented from invading in the MEM 154 or the FD 156, and a noise is prevented from occurring.
{Method for Manufacturing Solid-State Image Sensing Device 101l}
A method for manufacturing the solid-state image sensing device 101l will be described below with reference to
A high-concentration boron (B) layer 1401, which extends in the horizontal direction, is first formed in the semiconductor substrate 1001 as illustrated in
The active layer in the semiconductor substrate 1001 is then epitaxially grown as illustrated in
Impurity ions are then implanted in the semiconductor substrate 1001 and the main body 151A of the PD 151 is formed in the layer lower than the B layer 1401 as illustrated in
Impurity ions are then implanted in the semiconductor substrate 1001 and the plug 151B of the PD 151 is formed as illustrated in
A pixel circuit is then formed as illustrated in
Then, as illustrated in
Additionally,
Then, as illustrated in
Then, as illustrated in
The light blocking film 1002 is then generated as illustrated in
The on-chip color filter and the on-chip micro lens are then formed as described above with reference to
A thirteenth embodiment of the present technology will be described below with reference to
{Exemplary Configuration of Solid-State Image Sensing Device 101m}
The solid-state image sensing device 101m in
The lid 151C spreads from the tip of the plug 151B along the upper surface of the semiconductor substrate 1001 in parallel with the upper surface of the main body 151A and reverse to the MEM 154.
A light with a small incident angle in a dotted line among the lights which are not absorbed in the main body 151A of the PD 151 and pass through the opening 1002C of the light blocking film 1002 is incident in the plug 151B and is easily absorbed. On the other hand, an oblique light with a large incident angle in a solid line is likely to pass through the plug 151B. This is applicable to a diffraction light passing through the opening 1002C.
Thus, the lid 151C is provided at the tip of the plug 151B so that a light, which is not absorbed in the plug 151B and passes therethrough, can be absorbed in the lid 151C. Consequently, the charges generated by the light passing through the opening 1002C of the light blocking film 1002 can be prevented from invading in the MEM 154 or the FD 156, and a noise can be more effectively prevented from occurring.
A fourteenth embodiment of the present technology will be described below with reference to
{Exemplary Configuration of Solid-State Image Sensing Device 101n}
The solid-state image sensing device 101n in
In this way, the opening 1002C of the light blocking film 1002 is made closer to the vertical light blocking part 1002B, and thus an oblique light with a large incident angle hardly passes through the opening 1002C as indicated in a solid arrow in the Figure, for example. Therefore, most of the lights passing through the opening 1002C are lights with a small incident angle, and the lights passing through the opening 1002C are more easily absorbed in the plug 151B. Consequently, the charges generated by the lights passing through the opening 1002C of the light blocking film 1002 can be prevented from invading in the MEM 154 or the FD 156, and a noise can be more effectively prevented from occurring.
A fifteenth embodiment of the present technology will be described below with reference to
{Exemplary Configuration of Solid-State Image Sensing Device 101o}
The solid-state image sensing device 101o in
The gate terminal (electrode) 157A of the OFG 157 is formed on the left of the plug 151B of the PD 151 on the device forming surface of the semiconductor substrate 1001.
The OFD 1501 is formed on the left of the gate terminal (electrode) 157A of the OFG 157 and at an end of the pixel around the surface of the semiconductor substrate 1001.
When the drive signal OFG applied to the gate terminal (electrode) 157A of the OFG 157 is turned on and the OFG 157 is turned on, the charges accumulated in the PD 151 are transferred to the OFD 1501 via the OFG 157 to be discharged to the outside. Thereby, the PD 151 is reset.
Further, an oblique light passing through the opening 1002C of the light blocking film 1002 is incident in the OFD 1501 as indicated by a solid arrow in the Figure. The charges generated by the light incident in the OFD 1501 are then discharged from the OFD 1501 to the outside. Consequently, the charges generated by the light passing through the opening 1002C of the light blocking film 1002 can be prevented from invading in the MEM 154 or the FD 156, and a noise can be more effectively prevented from occurring.
Additionally, the OFD 1501 does not necessarily need to be arranged between adjacent pixels. For example, the OFD 1501 is arranged at a position where an oblique light with a predetermined incident angle is incident in a case where the light passes through the opening 1002C of the light blocking film 1002.
A sixteenth embodiment of the present technology will be described below with reference to
{Exemplary Configuration of Solid-State Image Sensing Device 101p}
The solid-state image sensing device 101p in
The gate terminal (electrode) 158A of the RST 158 is formed on the right of the FD 156 on the device forming surface of the semiconductor substrate 1001.
The OFD 1501 is arranged between the pixel P1 and the pixel P2 which are adjacent to each other. More specifically, the OFD 1501 is arranged between the gate terminal (electrode) 158A of the RST 158 in the pixel P1 and the gate terminal (electrode) 157A of the OFG 157 in the pixel P2 around the surface of the semiconductor substrate 1001.
For example, when the drive signal RST applied to the gate terminal (electrode) 158A of the RST 158 in the pixel P1 is turned on and the RST 158 is turned on, the charges accumulated in the FD 156 are transferred to the OFD 1501 via the RST 158 to be discharged to the outside. Thereby, the FD 156 is reset.
Further, when the drive signal OFG applied to the gate terminal (electrode) 157A of the OFG 157 in the pixel P2 is turned on and the OFG 157 is turned on, the charges accumulated in the PD 151 are transferred to the OFD 1501 via the OFG 157 to be discharged to the outside. Thereby, the PD 151 is reset.
Therefore, the OFD 1501 is shared between the pixel P1 and the pixel P2 which are adjacent to each other in the solid-state image sensing device 101p.
Further, an oblique light passing through the opening 1002C of the light blocking film 1002 is incident in the OFD 1501 in the solid-state image sensing device 101p as in the solid-state image sensing device 1010. The charges generated by the light incident in the OFD 1501 are then discharged from the OFD 1501 to the outside. Consequently, the charges generated by the light passing through the opening 1002C of the light blocking film 1002 can be prevented from invading in the MEM 154 or the FD 156, and a noise can be more effectively prevented from occurring.
A seventeenth embodiment of the present technology will be described below with reference to
{Exemplary Configuration of Solid-State Image Sensing Device 101q}
Further, the solid-state image sensing device 101q is different from the solid-state image sensing device 101p in
An eighteenth embodiment of the present technology will be described below with reference to
{Exemplary Configuration of Solid-State Image Sensing Device 101r}
The solid-state image sensing device 101r is different from the solid-state image sensing device 101q in
The dummy opening 1551L is formed at a position corresponding to the position in which the plug 151B of the PD 151 in the pixel P2 is formed (or the position in which the opening 1002C (not illustrated) of the light blocking film 1002 in the pixel P2 is formed) in the pixel P1. The dummy opening 1551L has substantially the same size as the opening 1002C of the light blocking film 1002.
The dummy opening 1551R is formed at a position corresponding to the position in which the plug 151B of the PD 151 in the pixel P1 is formed (or the position in which the opening 1002C (not illustrated) of the light blocking film 1002 in the pixel P1 is formed) in the pixel P2. The dummy opening 1551R has substantially the same size as the opening 1002C of the light blocking film 1002.
Therefore, the openings are provided almost at the same positions in the pixel P1 and the pixel P2, respectively, to be symmetric to each other. Thereby, an optical property for the oblique lights indicated by the arrows in the Figure can be adjusted in the pixel P1 and pixel P2, for example. Consequently, a variation in color or brightness between the pixels can be restricted.
The description has been made assuming that the cross section of the light blocking film is tapered in the second manufacture method according to the eleventh embodiment of the present technology, but the films other than the light blocking film can be tapered in the manufacture method.
Further, part of the side surface of the PD may not be surrounded by the light blocking film as needed, for example.
Further, the present technology can be applied to solid-state image sensing devices in systems other than the global shutter system, or solid-state image sensing devices of surface irradiation type, for example, within the applicable range.
Further, each of the above embodiments has been described assuming that electrons are basically charges, but the present technology can be applied in a case where holes are assumed as charges. Furthermore, in each circuit configuration described above, the polarities of the transistors (N type MOS transistor and P type MOS transistor) can be exchanged.
The above-described solid-state image sensing devices can be used for various cases for sensing lights such as visible light, infrared ray, ultraviolet ray, and X-ray as described below.
{Shooting Device}
As illustrated in
The group of lenses 1711 takes an incident light (image light) from a subject, and forms an image on the imaging surface of the imaging device 1712. The imaging device 1712 converts the amount of incident light formed as an image on the imaging surface by the group of lenses 1711 into an electric signal in units of pixel, and outputs the electric signal as a pixel signal.
The display device 1715 is configured of a panel type display device such as liquid crystal display device or organic electro luminescence (EL) display device, and displays animations or still images shot by the imaging device 1712. The recording device 1716 records the animations or still images shot by the imaging device 1712 in a recording medium such as memory card, video tape, or digital versatile disk (DVD).
The operation system 1717 issues operation commands for various functions of the shooting device 1701 in response to user's operations. The power supply system 1718 supplies the DSP circuit 1713, the frame memory 1714, the display device 1715, the recording device 1716, and the operation system 1717 with power as needed.
The shooting device 1701 is applicable to video cameras or digital still cameras, and additionally camera modules for mobile devices such as Smartphones or cell phones. Further, the solid-state image sensing device according to each of the above embodiments can be used as the imaging device 1712 in the shooting device 1701. Thereby, the image quality of the shooting device 1701 can be enhanced.
Additionally, embodiments of the present technology are not limited to the above-described embodiments, and can be variously changed without departing from the spirit of the present technology.
For example, each of the above-described embodiments can be combined within the possible range. For example, the fourth embodiment, the ninth embodiment, or the eighteenth embodiment can be combined with other embodiment.
Further, the present technology can employ the following configurations, for example.
(1)
A solid-state image sensing device including:
a photoelectric conversion unit;
a charge holding unit for holding charges transferred from the photoelectric conversion unit;
a first transfer transistor for transferring charges from the photoelectric conversion unit to the charge holding unit; and
a light blocking part including a first light blocking part and a second light blocking part,
in which the first light blocking part is arranged between a second surface opposite to a first surface as a light receiving surface of the photoelectric conversion unit and the charge holding unit, and covers the second surface, and is formed with a first opening, and
the second light blocking part surrounds the side surface of the photoelectric conversion unit.
(2)
The solid-state image sensing device according to (1),
in which a cross section of the first light blocking part is tapered from a connection part with the second light blocking part toward the first opening.
(3)
The solid-state image sensing device according to (1) or (2), further including:
a third light blocking part for covering at least a surface of the charge holding unit opposite to a surface opposing the first light blocking part at a position away from the first light blocking part from a device forming surface on which the first transfer transistor is formed.
(4)
The solid-state image sensing device according to any of (1) to (3),
in which a gate electrode of the first transfer transistor includes a first electrode part parallel to the first light blocking part, and a second electrode part vertical to the first light blocking part and extending from the first light blocking part closer to the charge holding unit toward the photoelectric conversion unit via the first opening.
(5)
The solid-state image sensing device according to (4), further including:
a fourth light blocking part which is connected to the first light blocking part and is at least partially arranged closer to the charge holding unit than to the first light blocking part and at a different position from the second light blocking part in parallel with the second surface.
(6)
The solid-state image sensing device according to (4),
in which the photoelectric conversion unit is formed on a first semiconductor substrate,
the charge holding unit is formed on a second semiconductor substrate,
the first transfer transistor is formed over the first semiconductor substrate and the second semiconductor substrate, and
a joining interface between the first semiconductor substrate and the second semiconductor substrate is formed in a channel of the first transfer transistor.
(7)
The solid-state image sensing device according to (6),
in which the joining interface is formed closer to a drain end of the transfer transistor than to a source end.
(8)
The solid-state image sensing device according to (6) or (7),
in which the second light blocking part is formed from the second surface of the photoelectric conversion unit,
the device further including:
a fifth light blocking part formed from the first surface of the photoelectric conversion unit and connected to the second light blocking part.
(9)
The solid-state image sensing device according to any of (1) to (5),
in which the photoelectric conversion unit, the charge holding unit, and the first transfer transistor are made of monocrystal silicon.
(10)
The solid-state image sensing device according to any of (1) to (3),
in which the photoelectric conversion unit includes a protruded part from the second surface extending from the first light blocking part toward the charge holding unit via the first opening.
(11)
The solid-state image sensing device according to (10),
in which the protruded part spreads in parallel with the second surface from the first light blocking part toward the charge holding unit.
(12)
The solid-state image sensing device according to (10), further including:
a charge discharging unit for discharging charges accumulated in the photoelectric conversion unit,
in which the charge discharging unit is arranged at a position in which a light with a predetermined incident angle is incident in a case where the light passes through the first opening.
(13)
The solid-state image sensing device according to (12),
in which the charge discharging unit is arranged between a first pixel and a second pixel which are adjacent to each other, and is shared by the first pixel and the second pixel.
(14)
The solid-state image sensing device according to (13),
in which the first openings are arranged near the charge discharging unit in the first pixel and the second pixel, respectively,
a second opening with substantially the same size as the first opening is formed in the first pixel at a position corresponding to the first opening in the second pixel, and
a third opening with substantially the same size as the first opening is formed in the second pixel at a position corresponding to the first opening in the first pixel.
(15)
The solid-state image sensing device according to (1),
in which a sacrifice film making the first light blocking part is made of SiGe, and the device further including:
an alignment mark made of the sacrifice film which is not removed and remains.
(16)
The solid-state image sensing device according to (1),
in which a cross section of the first light blocking part is rounded at the first opening.
(17)
The solid-state image sensing device according to any of (1) to (16), further including:
a charge voltage conversion unit; and
a second transfer transistor for transferring charges held in the charge holding unit to the charge voltage conversion unit,
in which the first light blocking part is arranged between the second surface of the photoelectric conversion unit, and the charge holding unit and the charge voltage conversion unit.
(18)
An electronic device including a solid-state image sensing device, the device including:
a photoelectric conversion unit;
a charge holding unit for holding charges transferred from the photoelectric conversion unit;
a first transfer transistor for transferring charges from the photoelectric conversion unit to the charge holding unit; and
a light blocking part including a first light blocking part and a second light blocking part,
in which the first light blocking part is arranged between a second surface opposite to a first surface as a light receiving surface of the photoelectric conversion unit and the charge holding unit, covers the second surface, and is formed with a first opening, and
the second light blocking part surrounds the side surface of the photoelectric conversion unit.
(19)
A solid-state image sensing device including:
a photoelectric conversion unit;
a charge holding unit for holding charges transferred from the photoelectric conversion unit;
a transfer transistor for transferring charges from the photoelectric conversion unit to the charge holding unit; and
a light blocking part including a first light blocking part formed with an opening, and a second light blocking part,
in which the first light blocking part is arranged in parallel with a light receiving surface of the photoelectric conversion unit and between the photoelectric conversion unit and the charge holding unit, and covers the photoelectric conversion unit except the opening, and
the second light blocking part surrounds the side surface of the photoelectric conversion unit.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2015-039223 | Feb 2015 | JP | national |
The present application is a continuation application of U.S. patent application Ser. No. 15/551,129, filed Aug. 15, 2017, which is a national stage entry of PCT/JP2016/054067, filed Feb. 12, 2016, which claims priority from prior Japanese Priority Patent Application JP 2015-039223 filed in the Japan Patent Office on Feb. 27, 2015, the entire contents of which are hereby incorporated by reference.
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| Number | Date | Country | |
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| Number | Date | Country | |
|---|---|---|---|
| Parent | 15551129 | US | |
| Child | 16683379 | US |
