Solid-state image sensing device and method of operating the same

Abstract

A charge coupled device is provided with; an output gate; a main CCD region operated in response to a set of clock signals; and an output region positioned between the output gate and the main CCD region and designed to transfer electric charges received from the main CCD region to the output gate. The main CCD region includes first and second transfer electrodes. The output region includes third and fourth transfer electrodes receiving clock signals which are phase-reversed from each other. The set of clock signals received by the main CCD region and the clock signals received by the output region are outputted from different driver circuits.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanied drawings, in which:

FIG. 1 is a plan view illustrating the structure of a conventional CCD;

FIG. 2 is a section view illustrating the structure of the conventional CCD shown in FIG. 1;

FIG. 3 is a timing chart illustrating the operation of the conventional CCD shown in FIG. 1;

FIG. 4 is a schematic diagram illustrating the potential profile across the convention CCD shown in FIG. 1;

FIG. 5 is a schematic diagram explaining the existence of untransferred signal charges;

FIG. 6 is a timing chart illustrating the waveform of the output voltage of the conventional CCD;

FIG. 7 is a plan view illustrating the structure of a solid-state image sensing device in a first embodiment of the present invention;

FIG. 8 is a section view illustrating the structure of the solid-state image sensing device in the first embodiment;

FIG. 9 is a timing chart illustrating the operation of the solid-state image sensing device in the first embodiment;

FIG. 10 is a schematic diagram illustrating the manner in which signal charges are transferred over the CCD;

FIG. 11 is a timing chart illustrating the waveform of the output voltage generated by the clock signals;

FIG. 12 is an enlarged waveform chart illustrating the coupling noise observed on the output voltage in the first embodiment;

FIG. 13 is a section view illustrating the parasitic capacitances formed within the solid-state image sensing device in the first embodiment;

FIG. 14 is a timing chart illustrating the waveforms of clock signals in high-speed operation;

FIG. 15 is a schematic diagram illustrating a potential profile across the CCD for the high speed charge transmission;

FIG. 16 is a plan view illustrating the structure of a solid-state image sensing device in a second embodiment of the present invention;

FIG. 17 is a section view illustrating the structure of the solid-state image sensing device in the second embodiment;

FIG. 18 is a timing chart illustrating the operation of the solid-state image sensing device in the second embodiment;

FIG. 19 is a schematic diagram illustrating the potential profile across the CCD in the second embodiment;

FIG. 20 is a timing chart illustrating the waveform of the output voltage in the second embodiment;

FIG. 21 is a schematic diagram illustrating a potential profile across the CCD for the high speed charge transmission;

FIG. 22 is a plan view illustrating the structure of a solid-state image sensing device in a third embodiment of the present invention;

FIG. 23 is a plan view illustrating the structure of a solid-state image sensing device in a fourth embodiment of the present invention; and

FIG. 24 is a plan view illustrating the structure of a solid-state image sensing device in a fifth embodiment of the present invention.

Claims

1. A charge coupled device comprising: an output gate;a main CCD region operated in response to a set of clock signals; andan output region positioned between said output gate and said main CCD region and designed to transfer electric charges received from said main CCD region to said output gate;wherein said main CCD region includes first and second transfer electrodes receiving said set of clock signals, and said output region includes third and fourth transfer electrodes receiving clock signals which are phase-reversed from each other,wherein said set of clock signals received by said first and second transfer electrodes and said clock signals received by said third and fourth transfer electrodes are outputted from different driver circuits.

2. The charge coupled device according to claim 1, wherein said set of clock signals received by said first and second transfer electrodes include: a first clock signal; anda second clock signal which is phase-reversed from said first clock signal,wherein said clock signals received by said third and fourth transfer electrodes include:a third clock signal having the same cycle period as said first clock signal; anda fourth clock signal having the same cycle period as said second clock signal.

3. The charge coupled device according to claim 2, further comprising; a first clock signal line feeding said first clock signal to said main CCD region;a second clock signal line feeding said second clock signal to said main CCD region;a third clock signal line provided separately from said first and second clock signal lines and feeding said third clock signal to said fourth transfer electrode; anda fourth clock signal line provided separately from said first and second clock signal lines and feeding said fourth clock signal to said third transfer electrode;wherein said third clock signal line is connected with said fourth transfer electrode without being connected with said main CCD region, andwherein said fourth clock signal line is connected with said third transfer electrode without being connected with said main CCD region.

4. The charge coupled device according to claim 1, wherein said third and fourth transfer electrodes are positioned adjacent to each other, and wherein one of said third and fourth transfer electrodes are positioned adjacent to said output gate.

5. The charge coupled device according to claim 4, further comprising: a fifth transfer electrode connected between said output gate and said one of said third and fourth transfer electrodes,wherein said fifth transfer electrode receives a fifth clock signal having a cycle period identical to an integral multiple of a cycle period of said third clock signal.

6. The charge coupled device according to claim 4, wherein frequencies of said first to fourth clock signals are changeable.

7. The charge coupled device according to claim 1, further comprising: a charge transfer diffusion layer through which said electric charges are transferred within said main CCD region and said output region,wherein said charge transfer diffusion layer is tapered down toward said output gate in said output region, andwherein lengths of said third and fourth transfer electrodes are increased as the decrease in a width of said charge transfer diffusion layer.

8. A solid-state image sensing device comprising; an output gate;a main CCD region including first and second transfer electrodes;an output region positioned between said output gate and said main CCD region and designed to transfer electric charges received from said main CCD region to said output gate, said output region including third and fourth transfer electrodes;a first contact pad;a second contact pad;second and fourth clock signal lines connected with said first contact pad; andfirst and third clock signal lines connected with said second contact pad,wherein said first clock signal line feeds a first clock signal to said first transfer electrodes;wherein said second clock signal line feeds a second clock signal to said second transfer electrodes;wherein said third clock signal line feeds a third clock signal to said third transfer electrode(s);wherein said fourth clock signal line feeds said fourth clock signal to said fourth transfer electrodes).

9. The solid-state image sensing device according to claim 8, wherein a number of said third transfer electrode(s) connected with said third clock signal line is less than that of said first transfer electrodes connected with said first clock signal line.

10. The solid-state image sensing device according to claim 9, wherein a number of said fourth transfer electrode(s) connected with said fourth clock signal line is less than that of said second transfer electrodes connected with said second clock signal line.

11. The solid-state image sensing device according to claim 8, wherein said second and fourth clock signal lines are separated from each other at portions other than said first contact pad.

12. The solid-state image sensing device according to claim 11, wherein said first and third clock signal lines are separated from each other at portions other than said second contact pad.

13. The solid-state image sensing device according to claim 8, wherein said second and fourth clock signal lines are branched from said first contact pad.

14. The solid-state image sensing device according to claim 13, wherein said first and third clock signal lines are branched from said second contact pad.

15. The solid-state image sensing device according to claim 8, further comprising: a first node connected to said first contact pad; anda second node connected to said second contact pad,wherein said second and fourth clock signal lines each have an end connected with said first node,wherein said first and third clock signal lines each have an end connected with said second node.