Claims
- 1. A manufacturing process of a solid-state image sensor comprising:
- a first step of forming an insulating film on one major surface of a semiconductor substrate of the first conduction type and subjecting said insulating film to selective etching so that on one major surface of said semiconductor substrate, at least portions corresponding to regions assigned for photoelectric transducers are exposed and the remaining insulating film serves as a buried insulating film,
- a second step of forming an epitaxial growth semiconductor layer of the second conduction type thicker than said buried insulating film by epitaxial growth on the exposed surface of said semiconductor substrate so that it extends over said buried insulating film,
- a third step of subjecting the surface of said epitaxial growth semiconductor layer to selective oxidation so that a field insulating film is formed to be in contact with said buried insulating film, and
- a fourth step of forming photoelectric transducers in said regions assigned for photoelectric transducers in said epitaxial growth semiconductor layer.
- 2. A manufacturing process of a solid-state image sensor in accordance with claim 1, wherein
- said epitaxial growth semiconductor layer is formed in a vapor-phase epitaxy furnace where pressure is reduced to less than 100 Torr.
- 3. A manufacturing process of a solid-state image sensor in accordance with claim 1, wherein
- said buried insulating film is formed so as to have a width less than 100 .mu.m.
- 4. A manufacturing process of a solid-state image sensor in accordance with claim 1, wherein
- a layer of high impurity concentration is formed in said epitaxial growth semiconductor layer over said buried insulating film before formation of said field insulating film.
Priority Claims (1)
Number |
Date |
Country |
Kind |
57-188552 |
Oct 1982 |
JPX |
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Parent Case Info
This is a division of application Ser. No. 526,402, filed on Aug. 25, 1983, now U.S. Pat. No. 4,611,223.
US Referenced Citations (4)
Foreign Referenced Citations (1)
Number |
Date |
Country |
0040984A1 |
Feb 1981 |
EPX |
Non-Patent Literature Citations (3)
Entry |
Japanese J. of Applied Physics, vol. 21, No. 9, Sep. 1982, pp. L564-L566, Kohetsutanno et al, "Selective Silicon Epitaxy Using Reduced Pressure Technique". |
IEEE Symp. on VLSI Technology, Tech Dig. Paper 1982, pp. 116-117, S. Hine et al, "A New Isolation Technology for Bipolar Devices by Low Pressure Selective Silicon Epitaxy". |
IEEE IEDM, Dec. 1982, pp. 241-244, N. Endo et al, "Novel Devices Isolation Technology with Selective Epitaxial Growth". |
Divisions (1)
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Number |
Date |
Country |
Parent |
526402 |
Aug 1983 |
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