Patent Grant
10171761
This application is a U.S. National Phase of International Patent Application No. PCT/JP2016/058649 filed on Mar. 18, 2016, which claims priority benefit of Japanese Patent Application No. JP 2015-076732 filed in the Japan Patent Office on Apr. 3, 2015. Each of the above-referenced applications is hereby incorporated herein by reference in its entirety.
The present technology relates to a solid-state imaging device and an electronic device, and particularly relates to a solid-state imaging device and an electronic device that enable a reduction in the voltage of an AD conversion circuit.
Recent years have seen the widespread use of cameras using CMOS image sensors (solid-state imaging devices).
In the case where such an image sensor is irradiated with high-intensity light, a phenomenon occurs in which a portion that originally is to be bright in an image becomes black. The black portion in the image is also called a sunspot etc., because it looks like a sunspot. The sunspot is caused by fluctuation of a reset level, which occurs when a large amount of charge generated in a photodiode (PD) constituting a pixel leaks to a floating diffusion (FD) or the FD is directly exposed to light.
To correct such a sunspot, limiting the voltage of a vertical signal line so that the reset level does not fluctuate beyond a certain level has been proposed.
For example, Patent Literature 1 describes that a clipping circuit limits the potential of a vertical signal line to different potentials between in reset level reading and in signal level reading.
Patent Literature 1: JP 2012-85343A
However, in the case where there is variation (mainly variation in threshold voltage) between amplification transistors of pixels, the reset level of a pixel fluctuates. Therefore, the gate voltage of the clipping circuit needs to be set to include some margin, in consideration of this variation. Accordingly, also a dynamic range of an AD conversion circuit needs to be set to include a margin similarly. That is, it is necessary to design the AD conversion circuit in consideration of at least a voltage corresponding to this margin, which hinders a reduction in the voltage of the AD conversion circuit.
The present technology has been made in view of such circumstances, and enables a reduction in the voltage of an AD conversion circuit.
A solid-state imaging device of an aspect of the present technology includes: a plurality of pixels; a vertical signal line configured to output a pixel signal of the pixel; and a clipping circuit configured to limit a voltage of the vertical signal line to a predetermined voltage. The clipping circuit includes a transistor configured to generate the predetermined voltage in accordance with a voltage of a gate, and a sample holding circuit configured to hold a reset level of the pixel that is output to the vertical signal line, and input the reset level to the gate of the transistor.
The clipping circuit can further include a capacitor having one electrode connected to the gate of the transistor, and a voltage generation circuit configured to generate a plurality of different voltages can be connected to the other electrode of the capacitor.
The voltage generation circuit can apply different voltages to the capacitor between in reading the reset level of the pixel and in reading a signal level of the pixel.
The clipping circuit can include a plurality of the capacitors, and the voltage generation circuit can apply a first voltage to one capacitor in reading the reset level of the pixel, and apply a second voltage to another capacitor in reading a signal level of the pixel.
The clipping circuit can further include a selector configured to turn on/off a limitation on the voltage of the vertical signal line using the predetermined voltage generated by the transistor.
An electronic device of an aspect of the present technology includes a solid-state imaging device including a plurality of pixels, a vertical signal line configured to output a pixel signal of the pixel, and a clipping circuit configured to limit a voltage of the vertical signal line to a predetermined voltage. The clipping circuit includes a transistor configured to generate the predetermined voltage in accordance with a voltage of a gate, and a sample holding circuit configured to hold a reset level of the pixel that is output to the vertical signal line, and input the reset level to the gate of the transistor.
In an aspect of the present technology, the predetermined voltage is generated in accordance with the voltage of the gate, and the reset level of the pixel that is output to the vertical signal line is held and input to the gate of the transistor.
According to an aspect of the present technology, the voltage of an AD conversion circuit can be reduced.
Embodiments of the present technology are described below with reference to the drawings.
<Configuration of Solid-State Imaging Device>
A solid-state imaging device 1 is configured as a complementary metal oxide semiconductor (CMOS) image sensor. The solid-state imaging device 1 includes a pixel area (pixel array) 3 in which a plurality of pixels 2 are regularly arranged in a two-dimensional array in a semiconductor substrate (e.g., a Si substrate), which is not illustrated, and a peripheral circuit unit.
The pixel 2 includes a photoelectric conversion unit (e.g., a photodiode) and a plurality of pixel transistors (MOS transistors). The plurality of pixel transistors may include, for example, three transistors of a transfer transistor, a reset transistor, and an amplification transistor. Alternatively, the plurality of pixel transistors may include four transistors including a selection transistor in addition to the three transistors.
The pixel 2 may be configured as one unit pixel, or may be in a pixel sharing structure. This pixel sharing structure is a structure in which a plurality of photodiodes share a floating diffusion and transistors other than a transfer transistor.
The peripheral circuit unit includes a vertical drive circuit 4, column signal processing circuits 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8.
The control circuit 8 receives an input clock and data commanding an operation mode or the like, and outputs data such as internal information of the solid-state imaging device 1. In addition, on the basis of a vertical synchronizing signal, a horizontal synchronizing signal, and a master clock, the control circuit 8 generates a clock signal and a control signal that serve as a reference for the operation of the vertical drive circuit 4, the column signal processing circuits 5, the horizontal drive circuit 6, and the like. Then, the control circuit 8 inputs these signals to the vertical drive circuit 4, the column signal processing circuits 5, the horizontal drive circuit 6, and the like.
The vertical drive circuit 4 is constituted by a shift register, for example. The vertical drive circuit 4 selects a pixel drive line, and supplies a pulse for driving pixels to the selected pixel drive line to drive pixels in units of rows. That is, the vertical drive circuit 4 selectively scans the pixels 2 of the pixel area 3 sequentially in the vertical direction in units of rows. Then, the vertical drive circuit 4 supplies pixel signals based on signal charge generated in accordance with the amount of received light in the photoelectric conversion units of the respective pixels 2 to the column signal processing circuits 5 through vertical signal lines 9.
The column signal processing circuit 5 is disposed for each column of the pixels 2, for example. The column signal processing circuits 5 perform signal processing such as noise cancellation on signals output from the pixels 2 of one row, in units of pixel columns. Specifically, the column signal processing circuits 5 perform signal processing such as correlated double sampling (CDS) for cancelling fixed pattern noise peculiar to the pixel 2, signal amplification, and analog-digital (AD) conversion. In the output stage of the column signal processing circuit 5, a horizontal selection switch (not illustrated) is provided to be connected to a horizontal signal line 10.
The horizontal drive circuit 6 is constituted by a shift register, for example. The horizontal drive circuit 6 sequentially outputs a horizontal scanning pulse to select the column signal processing circuits 5 in order, and causes the column signal processing circuits 5 to output pixel signals to the horizontal signal line 10.
The output circuit 7 performs signal processing on signals sequentially supplied from the column signal processing circuits 5 through the horizontal signal line 10, and outputs the resulting signals. For example, the output circuit 7 performs only buffering in some cases, and performs black level adjustment, column variation correction, various digital signal processing, and the like in some cases.
Input/output terminals 12 exchange signals with the outside.
<Structure of Solid-State Imaging Device>
Next, a structure of a solid-state imaging device to which the present technology is applied will be described.
As a first example, a solid-state imaging device 1a illustrated in the upper stage of
As a second example, a solid-state imaging device 1b illustrated in the middle stage of
As a third example, a solid-state imaging device 1c illustrated in the lower stage of
Note that a configuration that electrically connects the first semiconductor substrate 21 and the second semiconductor substrate 22 may be a through via, Cu—Cu metallic bonding, or other configurations.
In addition, the second semiconductor substrate 22 includes one layer in the above description, but may include two or more layers. That is, the present technology is also applicable to a solid-state imaging device made of a stack of three or more layers including the first semiconductor substrate 21 as the uppermost layer.
<Circuit Configuration and Operation of Solid-State Imaging Device>
As illustrated in
An anode of the PD 51 is grounded, and a cathode of the PD 51 is connected to a source of the transfer transistor 52. A drain of the transfer transistor 52 is connected to a gate of the amplification transistor 55, and this connection point constitutes a floating diffusion (FD).
The reset transistor 54 is connected between a predetermined power source and the FD. A drain of the amplification transistor 55 is connected to the predetermined power source, and a source of the amplification transistor 55 is connected to a drain of the selection transistor 56. A source of the selection transistor 56 is connected to a vertical signal line 57.
In addition, the vertical signal line 57 is connected to a load MOS transistor 58. Bias voltage generated by a Bias generation circuit 59 is supplied to the load MOS transistor 58. Thus, the amplification transistor 55 and the load MOS transistor 58 constitute a source follower circuit.
The voltage of the vertical signal line 57 (a pixel signal) is read from an output terminal 60. The output of the output terminal 60 is held by a sample holding circuit 61 or a sample holding circuit 62. The sample holding circuit 61 holds the voltage (reset level) of the vertical signal line 57 corresponding to the potential of the FD when the FD is reset. The sample holding circuit 62 holds the voltage (signal level) of the vertical signal line 57 corresponding to the potential of the FD when charge of the PD 51 is transferred to the FD.
Furthermore, a clipping circuit 71 is connected to the vertical signal line 57. The clipping circuit 71 limits (clips) the voltage of the vertical signal line 57 to a predetermined voltage.
The clipping circuit 71 includes a clipping transistor 81, a sample holding circuit 82, and a capacitor 83.
The clipping transistor 81 generates a voltage to limit the voltage of the vertical signal line 57, in accordance with a clipping voltage CLP applied to its gate.
The sample holding circuit 82 holds the voltage of the vertical signal line 57, and inputs the voltage to the gate of the clipping transistor 81.
One electrode of the capacitor 83 is connected to the gate of the clipping transistor 81. The other electrode of the capacitor 83 is connected to a CLP adjustment voltage generation circuit 91.
The CLP adjustment voltage generation circuit 91 generates an adjustment voltage VCLP for adjusting the clipping voltage CLP, and applies the adjustment voltage VCLP to the capacitor 83.
Next, the operation of the solid-state imaging device illustrated in
In
First, in a state where the drive signal SEL is high (H), when the drive signal RST rises to H, the FD of the pixel 2 is reset. At this point, the drive signal SH_CLP rises to H; thus, the voltage (reset level) of the vertical signal line 57 is held and input to the gate of the clipping transistor 81.
Then, when the drive signal SH_R rises to H, the sample holding circuit 61 holds the reset level. That is, the reset level of the pixel 2 is read.
After that, when the drive signal TRG rises to H, charge of the PD 51 is transferred to the FD of the pixel 2.
Then, when the drive signal SH_S rises to H, the sample holding circuit 62 holds the voltage (signal level) of the vertical signal line 57 corresponding to the potential of the FD when charge of the PD 51 is transferred to the FD. That is, the signal level of the pixel 2 is read.
Here, the CLP adjustment voltage generation circuit 91 applies different adjustment voltages VCLP to the capacitor 83 between in reading the reset level of the pixel 2 and in reading the signal level of the pixel 2.
Specifically, the CLP adjustment voltage generation circuit 91 applies an adjustment voltage VCLP_R to the capacitor 83 in reading the reset level of the pixel 2. Thus, the clipping voltage CLP applied to the gate of the clipping transistor 81 is adjusted, and the voltage of the vertical signal line 57 is limited to a first voltage.
In addition, the CLP adjustment voltage generation circuit 91 applies an adjustment voltage VCLP_S lower than the adjustment voltage VCLP_R to the capacitor 83 in reading the signal level of the pixel 2. Thus, the clipping voltage CLP applied to the gate of the clipping transistor 81 is adjusted, and the voltage of the vertical signal line 57 is limited to a second voltage.
Note that as indicated by the dotted line in the drawing, the adjustment voltage VCLP_R and the adjustment voltage VCLP_S can be variable in accordance with the amount of adjustment of the clipping voltage CLP. The high-low relationship between the adjustment voltage VCLP_R and the adjustment voltage VCLP_S is reversed depending on the polarity of transistors included in the pixel 2.
Such operation enables the reset level and the signal level to be clipped appropriately.
The configuration in
The selector 111 turns on/off the limitation on the voltage of the vertical signal line 57 using a voltage generated by the transistor 81.
Next, the operation of the solid-state imaging device illustrated in
In
As illustrated in
The operation in this case is similar to the operation described with reference to
Here, as indicated by the dotted line in the drawing, the drive signal SEL_CLP is in the H state only in reading the reset level of the pixel 2. During this period, the selector 111 turns on the limitation on the voltage of the vertical signal line 57 using a voltage generated by the transistor 81. In reading the signal level, the selector 111 turns off the limitation on the voltage of the vertical signal line 57 using a voltage generated by the transistor 81.
Such operation enables only the reset level to be clipped appropriately.
Note that in the operation in
<Circuit Configuration and Operation of Conventional Solid-State Imaging Device>
Here, a circuit configuration and operation of a conventional solid-state imaging device for correcting a sunspot will be described.
In
A Ramp generation circuit 122 generates a reference signal Ramp that exhibits a ramp waveform having a predetermined slope at a predetermined timing. The reference signal Ramp is input to one terminal of a comparator 123.
The comparator 123 compares the reference signal Ramp input to one terminal with a pixel signal input to the other terminal. The comparator 123 outputs a signal whose level is inverted in accordance with the magnitude relationship between the reference signal Ramp and the pixel signal to a counter 124.
The counter 124 executes up-count operation and down-count operation while switching between them. The counter 124 ends the up-count operation and the down-count operation in accordance with a timing at which the output of the comparator 123 is inverted. Count values obtained by the up-count operation and the down-count operation are output as digital data.
Note that the two terminals of the comparator 123 are each configured in a manner that offset is cancelled (auto zero) by an AZ switch.
Thus, the comparator 123 and the counter 124 constitute a single-slope AD conversion circuit.
Next, the operation of the solid-state imaging device illustrated in
In
Note that for VSL, the solid line indicates a pixel signal in a state (dark) where charge of the PD does not leak to the FD. The dotted line indicates a pixel signal in a state (light) where charge of the PD leaks to the FD and a sunspot occurs.
Although detailed description of signals will be omitted, the CLP adjustment voltage generation circuit 91 applies different adjustment voltages VCLP to the gate of the transistor 81 between in reading the reset level of the pixel 2 and in reading the signal level of the pixel 2. Such operation enables the reset level and the signal level to be clipped appropriately.
Here, attention is focused on a dark pixel signal and a light pixel signal (VSL).
In reset level reading, a voltage difference Va between the dark pixel signal and the light pixel signal exhibits a voltage difference equal to or more than a voltage difference that does not interfere with a normal pixel. Furthermore, a voltage difference Vb between in reset level reading and in signal level reading of the light pixel signal exhibits a voltage difference by which it can be determined that a sunspot has occurred.
In this case, a sum Vdr of the voltage difference Va and the voltage difference Vb is needed as a dynamic range of the AD conversion circuit.
However, in the case where there is variation (mainly variation in threshold voltage) between amplification transistors of pixels, the reset level of a pixel (dark) fluctuates as illustrated in
Hence, in a solid-state imaging device of the present technology, a reset level is held and input to the gate of the clipping transistor 81.
The solid-state imaging device illustrated in
With this configuration, as illustrated in
The solid-state imaging device illustrated in
With this configuration, as illustrated in
Note that in the operation in
The solid-state imaging device illustrated in
The gain amplifier 131 amplifies the voltage of the vertical signal line 57, that is, a pixel signal, and supplies the amplified voltage to the comparator 123.
Also in the configuration illustrated in
The solid-state imaging device illustrated in
One electrode of each of the capacitors 83-R and 83-S is connected to the gate of the clipping transistor 81. The other electrode of each capacitor 83 is connected to a CLP adjustment voltage generation circuit 141.
The CLP adjustment voltage generation circuit 141 generates an adjustment voltage VCLP_R and applies it to the capacitor 83-R in reading the reset level of the pixel 2. In addition, the CLP adjustment voltage generation circuit 141 generates an adjustment voltage VCLP_S lower than the adjustment voltage VCLP_R and applies it to the capacitor 83-S in reading the signal level of the pixel 2.
Such operation enables the reset level and the signal level to be clipped appropriately.
Also in the configuration illustrated in
<Modification Examples of Structure of Solid-State Imaging Device>
Incidentally, as described with reference to
In this case, as illustrated in
Conversely, as illustrated in
Furthermore, in the circuit configurations of the solid-state imaging devices described above, the clipping circuit may be provided at any position.
For example, as illustrated in
The present technology is not limited to application to solid-state imaging devices, and is also applicable to imaging devices. Here, imaging devices refer to a camera system (e.g., a digital still camera and a digital video camera) and an electronic device with an imaging function (e.g., a mobile phone). Note that a module form mounted on an electronic device, that is, a camera module, is taken as an imaging device in some cases.
<Configuration Example of Electronic Device>
Here, a configuration example of an electronic device to which the present technology is applied will be described, with reference to
An electronic device 200 illustrated in
The optical lens 201 causes image light (incident light) from an object to form an image on an imaging surface of the solid-state imaging device 203. Thus, signal charge is accumulated in the solid-state imaging device 203 for a certain period. The shutter device 202 controls a light irradiation period and a light blocking period for the solid-state imaging device 203.
The drive circuit 204 supplies drive signals to the shutter device 202 and the solid-state imaging device 203. The drive signal supplied to the shutter device 202 is a signal for controlling shutter operation of the shutter device 202. The drive signal supplied to the solid-state imaging device 203 is a signal for controlling signal transfer operation of the solid-state imaging device 203. The solid-state imaging device 203 performs signal transfer in accordance with the drive signal (timing signal) supplied from the drive circuit 204. The signal processing circuit 205 performs various signal processing on signals output from the solid-state imaging device 203. Video signals that have undergone signal processing are stored in a storage medium, such as a memory, or output to a monitor.
In the electronic device 200 of the present embodiment, the voltage of an AD conversion circuit can be reduced in the solid-state imaging device 203; thus, as a result, an electronic device with low power consumption can be provided.
<Usage Examples of Image Sensor>
Lastly, usage examples of the image sensor to which the present technology is applied will be described.
The above-described image sensor can be used for, for example, various cases in which light such as visible light, infrared light, ultraviolet light, or X-rays is detected as follows.
Devices that take images used for viewing, such as a digital camera and a portable appliance with a camera function.
Devices used for traffic, such as an in-vehicle sensor that takes images of the front and the back of a car, surroundings, the inside of the car, and the like, a monitoring camera that monitors travelling vehicles and roads, and a distance sensor that measures distances between vehicles and the like, which are used for safe driving (e.g., automatic stop), recognition of the condition of a driver, and the like.
Devices used for home electrical appliances, such as a TV, a refrigerator, and an air conditioner, to takes images of a gesture of a user and perform appliance operation in accordance with the gesture.
Devices used for medical care and health care, such as an endoscope and a device that performs angiography by reception of infrared light.
Devices used for security, such as a monitoring camera for crime prevention and a camera for personal authentication.
Devices used for beauty care, such as skin measurement equipment that takes images of the skin and a microscope that takes images of the scalp.
Devices used for sports, such as an action camera and a wearable camera for sports and the like.
Devices used for agriculture, such as a camera for monitoring the condition of the field and crops.
In addition, embodiments of the present disclosure are not limited to the above-described embodiments, and various alterations may occur insofar as they are within the scope of the present disclosure.
Additionally, the present technology may also be configured as below.
(1)
A solid-state imaging device including:
a plurality of pixels;
a vertical signal line configured to output a pixel signal of the pixel; and
a clipping circuit configured to limit a voltage of the vertical signal line to a predetermined voltage,
in which the clipping circuit includes
The solid-state imaging device according to (1),
in which the clipping circuit further includes a capacitor having one electrode connected to the gate of the transistor, and
a voltage generation circuit configured to generate a plurality of different voltages is connected to the other electrode of the capacitor.
(3)
The solid-state imaging device according to (2),
in which the voltage generation circuit applies different voltages to the capacitor between in reading the reset level of the pixel and in reading a signal level of the pixel.
(4)
The solid-state imaging device according to (2),
the voltage generation circuit applies a first voltage to one capacitor in reading the reset level of the pixel, and applies a second voltage to another capacitor in reading a signal level of the pixel.
(5)
The solid-state imaging device according to any one of (1) to (4),
in which the clipping circuit further includes a selector configured to turn on/off a limitation on the voltage of the vertical signal line using the predetermined voltage generated by the transistor.
(6)
An electronic device including
a solid-state imaging device including
a plurality of pixels,
a vertical signal line configured to output a pixel signal of the pixel, and
a clipping circuit configured to limit a voltage of the vertical signal line to a predetermined voltage,
in which the clipping circuit includes
| Number | Date | Country | Kind |
|---|---|---|---|
| 2015-076732 | Apr 2015 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2016/058649 | 3/18/2016 | WO | 00 |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2016/158484 | 10/6/2016 | WO | A |
| Number | Name | Date | Kind |
|---|---|---|---|
| 7741593 | Iwata | Jun 2010 | B2 |
| 20060278809 | Takayanagi | Dec 2006 | A1 |
| 20090200449 | Iwata et al. | Aug 2009 | A1 |
| Number | Date | Country |
|---|---|---|
| 101243681 | Aug 2008 | CN |
| 101510963 | Aug 2009 | CN |
| 2006-352341 | Dec 2006 | JP |
| 2008-042676 | Feb 2008 | JP |
| 2008-544656 | Dec 2008 | JP |
| 2009-194569 | Aug 2009 | JP |
| 2012-085343 | Apr 2012 | JP |
| 10-2008-0019292 | Mar 2008 | KR |
| 10-1069524 | Sep 2011 | KR |
| 2006138533 | Dec 2006 | WO |
| Entry |
|---|
| International Search Report and Written Opinion of PCT Application No. PCT/JP2016/058649, dated May 24, 2016, 12 pages of ISRWO. |
| Number | Date | Country | |
|---|---|---|---|
| 20180098005 A1 | Apr 2018 | US |
