SOLID-STATE IMAGING DEVICE AND METHOD OF MANUFACTURING THE SAME

Abstract

A solid-state imaging device that realizes a reduction in 1/f noise in an amplifying transistor in a pixel cell and an analog circuit as a peripheral circuit, and a method of manufacturing the same are provided. A solid-state imaging device according to the present invention includes: a plurality of pixel cells that are arranged in a matrix form on a semiconductor substrate 100; and peripheral circuits that allow a signal to be outputted from the pixel cells via a predetermined signal line. Gate insulating films of a plurality of transistors constituitng the solid-state imaging device include both a nitrided gate insulating film and a non-nitrided gate insulating film.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram showing two types of transistors having a nitrided gate insulating film and a non-nitrided gate insulating film, respectively.

FIG. 2 is a diagram explaining a method of manufacturing two types of transistors having a nitrided gate insulating film and a non-nitrided gate insulating film, respectively.

FIG. 3 is a circuit diagram showing a typical configuration of a MOS type solid-state imaging device.

FIG. 4 is a diagram showing a main portion of a circuit configuration for explaining part of operations of a pixel cell and a noise suppressing circuit in a MOS type solid-state imaging device.

FIG. 5 is a diagram showing nitrogen distributions in a gate insulating film.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, the solid-state imaging device according to the present invention will be described in detail with reference to the appended drawings.

FIG. 1 is a schematic diagram showing a case where a MOS transistor having a nitrided gate insulating film and a MOS transistor having a non-nitrided gate insulating film are formed on a common semiconductor substrate 100.

With respect to two transistors separated to the left and right by an element isolator 101, a nitrided gate insulating film 105 and a non-nitrided gate insulating film 103 are formed on a p-type well 102, respectively, and a gate electrode 106 is disposed on each of the gate insulating films 105 and 103. It is to be noted that this diagram shows a state in which in a solid-state imaging device, a MOS transistor having a gate insulating film formed substantially of an oxide film and a MOS transistor having a gate insulating film formed of a nitride oxide film are placed side-by-side, and is not a cross-sectional view of a particular portion of the solid-state imaging device.

By referring to FIG. 2, the following describes a manufacturing method for forming two MOS transistors having different types of gate insulating films on a common semiconductor substrate.

First, on the semiconductor substrate 100 in which the element isolators 101 and the p-type well 102 are formed as shown in FIG. 2(A), the gate insulating film 103 is formed by thermal oxidation as shown in FIG. 2(B). This gate insulating film 103 is a pure silicon oxide film that does not contain nitrogen as an impurity and could be formed by a conventionally known normal method. Specific forming conditions are, for example, as follows.

Gas:           diluted oxygen (mixture of O2 and N2, O2: 5%)
Temperature:   800° C. to 900° C.
Treating time: 10 to 20 minutes

Herein, as shown in FIG. 2(C), in order to obtain a mask layer for masking a n-channel transistor region as one of transistor regions, a resist is applied to form a resist film that then is subjected to conventional treatments of exposure and development, and thus a patterned resist 104 is obtained.

Plasma nitriding is performed in this state under, for example, the following conditions.

High-frequency power: 13.56 MHz, 500 W
Gas:                  N2
Pressure:             5 Pa
Treating time:        10 to 120 seconds
Stage temperature:    20° C.

At this time, a surface of the gate insulating film in a portion exposed to nitrogen plasma is nitrided while the surface in a portion covered with the resist is not nitrided, and thus the nitrided gate insulating film 105 and the non-nitrided gate insulating film 103 can be formed separately from each other as shown in FIG. 2(D).

Next, after removing the resist using a chemical solution such as a mixture solution of sulfuric acid and hydrogen peroxide, post-annealing is performed under, for example, the following conditions.

Temperature: 800 to 1100° C.
Gas:         oxygen or nitrogen atmosphere
Time:        10 to 120 seconds

This process stabilizes film quality. After that, a gate electrode material film such as of silicon is deposited, and patterning is performed so that the gate electrodes 106 are formed as shown in FIG. 2(E), and thus a basic transistor configuration is obtained.

In the method of manufacturing a solid-state imaging device, process steps to be followed after the formation of a gate electrode are the same as those well known, and thus duplicate descriptions thereof are omitted herein.

The description is directed next to a configuration of the solid-state imaging device according to the present invention.

According to the above-described method, a gate insulating film that is formed substantially of an oxide film and a gate insulating film that is formed of a nitride oxide film can be formed on one semiconductor substrate, allowing this to be applied to solid-state imaging devices in practical use. A solid-state imaging device according to this embodiment has both a gate insulating film that is formed substantially of an oxide film and a gate insulating film that is formed of a nitride oxide film on a semiconductor substrate thereof.

The solid-state imaging device according to this embodiment has the same basic circuit configuration as the typical circuit configuration of the solid-state imaging device shown in FIG. 3. Herein, a pixel cell includes, as well as the photodiode 301, three transistors that are the transfer transistor 302, the amplifying transistor 304, and the reset transistor 303. In the solid-state imaging device according to this embodiment, as a gate insulating film of the amplifying transistor 304 among these transistors, a non-nitrided gate insulating film is used, and the amplifying transistor 304 is formed of a n-channel transistor. This is because the amplifying transistor 304 is the only transistor that may cause 1/f noise when image capturing is performed, and with the use of a n-channel transistor as the amplifying transistor 304, boron seepage is no longer a matter of concern.

The following explains, in a little more detail, why the amplifying transistor 304 is the only transistor that may cause 1/f noise, while the other transistors are not particularly regarded as problematic.

First, regarding the transfer transistor 302, insofar as electric charges can be transferred completely from the photodiode 301, no electric charges remain in a channel, and thus an exchange of an electric charge between the channel and an interface level at an interface between a gate insulating film and a semiconductor substrate, which may cause 1/f noise, does not occur.

Furthermore, regarding the reset transistor 303, although it may cause offset noise (referred to as kTC noise) when resetting is performed, as can be understood also from the operation of the noise suppressing circuit described with reference to FIG. 4, an output potential V1 from a pixel cell in an initial reset state and an output potential V2 from the pixel cell in a state where electric charges are transferred are expressed respectively by:

V1=VDD−VGS   (a)

V2=VDD−VGS−Q/C   (c),

and a final output is expressed by:

Vout=C1/(C1+C2)×(VDD×V1+V2)=C1/(C1+C2)×(VDD−Q1/C)   (f).

Herein, even in the case where offset noise (kTC noise) “offset” is added to a reset potential of the pixel cell as expressed by:

V1=VDD+offset−VGS

V2=VDD+offset−VGS−Q/C,

in the final output, the offset noise is cancelled out by the operation “V2−V1” in the the equation, thereby presenting no substantial problem.

The description is directed next to transistors constituting peripheral circuits.

Among the vertical driver circuit 307, the noise suppressing circuit 308, and the horizontal driver circuit 309 that constitute peripheral circuits, first, regarding the noise suppressing circuit 308, a non-nitrided gate insulating film is used in a MOS transistor constituting the noise suppressing circuit 308. This is because, in the noise suppressing circuit, since an image signal generated in the photodiode 301 is handled as described above, there is a need to avoid the influence of 1/f noise.

Meanwhile, among the peripheral circuits, regarding the vertical driver circuit 307 and the horizontal driver circuit 309, a nitrided gate insulating film is used for each of them. This is because transistors constituting these circuits are required to be driven at a high speed and thus are desired to be configured of a miniaturized transistor. Therefore, it is desirable that a gate insulating film containing a nitrogen impurity be used, which allows a gate insulating film of a MOS transistor to have an increased effective film thickness.

Furthermore, the solid-state imaging device according to the present invention can employ the dual-gate structure, and in that case, the following configuration of the transistors could be adopted.

For example, in the case of a solid-state imaging device with two voltage systems composed of: low-voltage MOS transistors (for example, having a power supply voltage of 1.5 V and a gate insulating film thickness of 3 nm) such as the vertical driver circuit 307, the horizontal driver circuit 309, a shift register, and other components including a digital signal processing circuit; and high-voltage MOS transistors (for example, having a power supply voltage of 3.3 V and a gate insulating film thickness of 7 nm) that handle a signal from a photodiode, such as the pixel cell 312, the noise suppressing circuit 308, an amplifier, and an analog signal processing circuit, a nitrided gate insulating film is used in each of a n-channel low-voltage MOS transistor and a p-channel low-voltage MOS transistor. Further, in this case, a non-nitrided gate insulating film is used in each of a n-channel high-voltage MOS transistor and a p-channel high-voltage transistor. This is based on the following. That is, with respect to the n-channel low-voltage MOS transistor, there is a need to prevent gate leakage, and with respect to the p-channel low-voltage MOS transistor, this is intended to prevent boron seepage as well as gate leakage. On the other hand, with respect to the high-voltage MOS transistor, since it handles an image signal, it is desirable that a non-nitrided gate insulating film be used so that 1/f noise is avoided. Similarly, the high-voltage p-channel MOS transistor also handles an image signal, and thus in the case of the high-voltage p-channel transistor, the problems of gate leakage and boron seepage are avoided by the use of a gate insulating film having a thickness of not less than 5 nm rather than by nitriding of a gate insulating film.

As far as the circuit elements shown in FIG. 3 are concerned, the noise suppressing circuit 308 is configured generally of an analog circuit and thus, in many cases, is formed of a high-voltage MOS transistor so that a dynamic range of a signal is secured. On the other hand, the vertical driver circuit 307 and the horizontal driver circuit 309 are required to be operated at a high speed in a mode in which a frame rate is increased so that a large number of images are captured per second and thus, in many cases, are formed of a low-voltage MOS transistor. In such a case, it is useful to select the type of a gate insulating film to be used in the above-described manner.

Furthermore, with the aim of completely eliminating the problem of boron seepage, a design also has been proposed that uses a gate electrode formed of polysilicon doped with a n-type impurity for each of both gate electrode structures of n-channel MOS transistor (surface channel transistor) and a p-channel MOS transistor (buried channel transistor). In the case where this design is adopted, similarly to the above-described case, with respect to low-voltage MOS transistors, a nitrided gate insulating film is used in each of the n-channel MOS transistor and the p-channel MOS transistor, while with respect to high-voltage MOS transistors, a non-nitrided gate insulating film is used in each of the n-channel MOS transistor and the p-channel MOS transistor. This is because, since the problem of boron seepage already has been solved in this case, the selection of a gate insulating film can be made from the viewpoint of preventing gate leakage.

As described in the foregoing discussion, the present invention provides a solid-state imaging device that achieves a reduction in 1/f noise and uses a miniaturized MOS transistor, and a method of manufacturing the same, and thus is useful in realizing a solid-state imaging device that has an excellent S/N ratio and provides high image quality.

The invention may be embodied in other forms without departing from the spirit or essential characteristics thereof The embodiments disclosed in this application are to be considered in all respects as illustrative and not limiting. The scope of the invention is indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are intended to be embraced therein.

Claims

1. A solid-state imaging device, comprising: a plurality of pixel cells that are arranged in a matrix form on a semiconductor substrate; andperipheral circuits that allow a signal to be outputted from the pixel cells via a predetermined signal line, wherein gate insulating films of a plurality of transistors constituting the solid-state imaging device include both a nitrided gate insulating film and a non-nitrided gate insulating film.

2. The solid-state imaging device according to claim 1, wherein among the transistors, a transistor having the non-nitrided gate insulating film is an amplifying transistor in each of the pixel cells.

3. The solid-state imaging device according to claim 1, wherein among the transistors, a plurality of transistors constituting the peripheral circuits include both a n-channel transistor and a p-channel transistor, while at least part of transistors constituting the pixel cells is a n-channel transistor, and at least part of the n-channel transistors has the non-nitrided gate insulating film.

4. The solid-state imaging device according to claim 3, wherein the n-channel transistor includes a gate electrode doped with a n-type impurity, and the p-channel transistor includes a gate electrode doped with a p-type impurity.

5. The solid-state imaging device according to claim 3, wherein both of the n-channel transistor and the p-channel transistor include a gate electrode doped with a n-type impurity.

6. A method of manufacturing a solid-state imaging device, the solid-state imaging device comprising: a plurality of pixel cells that are arranged in a matrix form on a semiconductor substrate; andperipheral circuits that allow a signal to be outputted from the pixel cells via a predetermined signal line,the method comprising the process steps of: forming, on the semiconductor substrate, a gate insulating film of transistors constituting the solid-state imaging device;masking a portion on the gate insulating film with a mask layer;performing plasma nitriding with respect to a region of the gate insulating film that is not masked with the mask layer;peeling off the mask layer;annealing the semiconductor substrate; andforming a gate electrode on the semiconductor substrate.

7. The method according to claim 6, wherein a region in each of the pixel cells in which an amplifying transistor is formed is masked with the mask layer.

8. The method according to claim 6, wherein among the transistors, a plurality of transistors constituting the peripheral circuits include both a n-channel transistor and a p-channel transistor, while at least part of transistors constituting the pixel cells is a n-channel transistor, and a region in which at least part of the n-channel transistors is formed is masked with the mask layer.

9. The method according to claim 8, wherein the n-channel transistor includes a gate electrode doped with a n-type impurity, and the p-channel transistor includes a gate electrode doped with a p-type impurity.

10. The method according to claim 8, wherein both of the n-channel transistor and the p-channel transistor include a gate electrode doped with a n-type impurity.