1. Field of the Invention
The present invention relates to a solid state imaging device and an operation method of a solid state imaging device.
2. Description of the Related Art
A digital image photographic apparatus mounted with a solid state imaging device such as a digital still camera and a digital video camera has come into wide use. The solid state imaging device contains a CCD (Charge Coupled Device), an amplifier that amplifies an output of the CCD, an A/D converter that converts an output from the amplifier into a digital signal, and the like.
The CCD contains light receiving elements such as photo diodes, and a charge transfer section that transfers electric charges generated by the light receiving elements. The charge transferred by the charge transfer section is supplied to a charge detecting section. The charge detecting section converts the supplied charges into an electrical signal corresponding to the supplied charge, to output the electrical signal to the amplifier. The amplifier amplifies and outputs the electrical signal supplied from the charge detecting section.
As a method of detecting the charge by the use of the charge detecting section, a FDA (Floating Diffusion Amplifier) method is generally used. In the FDA method, the transferred charge is detected by detecting a potential change of a floating diffusion layer that is provided in a subsequent stage of a charge transfer section, as shown in Japanese Laid Open Patent Application (JP-A-Heisei 6-338525). An output signal is outputted from the floating diffusion layer. Then, the charge in the floating diffusion layer is necessary to be reset or discharge. Therefore, a reset transistor is provided for the charge transfer section using the FDA method.
When the charge transfer section is formed in a P-type semiconductor substrate, a reset transistor is formed from the floating diffusion layer, a reset drain, and a reset gate electrode. The reset transistor forms an N-channel region when a reset pulse is applied to the reset gate electrode and discharges the charge from the floating diffusion layer into the reset drain. The amplitude of the reset pulse applied to the reset gate is made larger than that of a charge transfer clock to perform a reset operation without fail.
By the way, in a semiconductor circuit, a lower voltage operation is requested. Such a request of the lower voltage operation is no exception even for the above-mentioned CCD. In order to cope with the request for the lower voltage operation and a single power supply in the CCD, in the above-mentioned Japanese Laid Open Patent Application (JP-A-Heisei 6-338525), a floating diffusion layer, a reset drain, and an absorption drain are provided in a surface region of a semiconductor substrate in a subsequent stage of charge transfer section that contains an n-type diffusion layer 12, transfer gate electrodes 14 and 15, and an output gate 16. A reset gate electrode is provided above a semiconductor substrate between the floating diffusion layer and the reset drain, while a barrier gate electrode is provided above the semiconductor substrate between the reset drain and the absorption drain. A resistance R is connected to the reset drain to discharge charge. A reset pulse with 5V as an H level and 0V as an L level is applied to the reset gate electrodes. A power supply voltage VB (5V) is applied to the barrier gate electrode, while an output voltage (12V) of a boosting circuit is applied to the absorption drain. Since the barrier transistor is in an on state at all times in this charge transfer section, a potential of the reset drain is kept to the potential of a channel region in the barrier transistor. The boosting circuit is formed by connecting rectifier circuits of diodes in multiple stages, and is applied with a transfer clock (not shown).
In such a solid state imaging device, when readout of charge from the light receiving element (photo diode) to the charge transfer section provided in the solid state imaging device is performed, the charge transfer section does not need to carry out its operation. Therefore, a transfer clock signal is stopped when the readout of charges from the light receiving element is carried out. Also, it is not necessary to operate the reset transistor, since the charge transfer is not carried out. Further, the boosting circuit also stops the charge transfer operation since the transfer clock is stopped.
In the solid state imaging device in the above-mentioned Japanese Laid Open Patent Application (JP-A-Heisei 6-338525), a signal voltage is supplied through a CCD output terminal from the floating diffusion layer to an amplifier circuit to obtain a signal output. The amplifier circuit is provided with a clamp circuit that applies an offset voltage to the signal voltage. In the same way as in the reset transistor and the boosting circuit, the clamp circuit does not need to operate when the readout of charge is carried out. Therefore, the clamp circuit stops its operation. An operation during such a period during which the readout of charge is carried out, namely, the operation when the transfer clock signal is stopped, is described next with reference to
Originally, a reset drain voltage VRD1 does not change since a constant voltage is applied to the gate electrode of the barrier transistor. However, if a gate length L of the barrier transistor is shortened in order to promptly discharge the charge stored in the floating diffusion layer to the reset drain, the reset drain voltage VRD1 decreases as the output voltage of the boosting circuit decreases.
Because the reset drain voltage VRD1 decreases lower than the original voltage, the offset voltage of the signal output Vout is also made lower than a predetermined voltage. If supply of the transfer clock signal is restarted in this state at a time t2, several bits in the beginning are not clamped to a desired voltage. Thus, it becomes difficult to obtain a desired output waveform from valid pixels.
In order to obtain the desired output waveform from the valid pixels as mentioned above, a technique is known to use invalid pixels provided for the solid state imaging device. In this technique, it is possible to stabilize the offset voltage until the signal voltage is generated based on the charges from the valid pixels. However, a circuit area of the solid state imaging device becomes larger if the invalid pixels are provided.
In an aspect of the present invention, a solid state imaging device includes a floating diffusion layer, a reset drain, and an absorption drain formed in a semiconductor substrate. The solid state imaging device further include a charge transfer section configured to transfer electric charge into the floating diffusion layer in response to a transfer clock signal; a reset transistor configured to transfer the electric charge from the floating diffusion layer into the reset drain in response to a reset pulse signal; a barrier transistor configured to transfer the electric charge from the reset drain into the absorption drain; a boosting circuit configured to bias the absorption drain to a predetermined voltage based on the transfer clock signal; a timing control circuit configured to stop supply of the transfer clock signal to the boosting circuit and the charge transfer section, and to restart supply of the reset pulse signal to the reset transistor at a first time prior to restart of the supply of the transfer clock signal at a second time.
Here, the solid state imaging device may further include an amplifying circuit connected with the floating diffusion layer to amplify a voltage signal based on the electric charge in the floating diffusion layer; a capacitor configured to cut a DC component from the amplified voltage signal; and a clamping circuit configured to apply a reference voltage to an output of the capacitor in response to a clamp pulse signal. The timing control circuit supplies the clamp pulse signal.
In this case, the timing control circuit may supply the clamp pulse signal when supplying the reset pulse signal and stops the supply of the clamp pulse signal when stopping the supply of the reset pulse signal.
Also, the first time is preferably predetermined such that an output signal of the solid state imaging device corresponding to the electric charge stored in the floating diffusion layer has a reference voltage.
Also, the transfer clock signal may include a first transfer clock signal and a second transfer clock signal.
Also, the reset transistor may be formed from the floating diffusion layer, the reset drain, and a reset gate electrode supplied with the reset pulse signal, and the barrier transistor may be formed from the reset drain, the absorption drain and a barrier gate electrode supplied with a constant voltage.
Also, the timing control circuit may stop the supply of the transfer clock signal to the boosting circuit and the charge transfer section when the electric charge is read out from a pixel to the charge transfer section.
In another aspect of the present invention, an operation method of a solid state imaging device is achieved by transferring electric charge into a floating diffusion layer of a charge transfer section in response to a transfer clock signal; by transferring the electric charge from the floating diffusion layer into a reset drain in response to a reset pulse signal; by transferring the electric charge from the reset drain into an absorption drain; by biasing the absorption drain to a predetermined voltage based on the transfer clock signal to absorb the electric charge; by stopping generation of the transfer clock signal; and by restarting the generation of the reset pulse signal at a first time prior to restart of the generation of the transfer clock signal at a second time.
Here, the operation method may be achieved by further amplifying a voltage signal based on the electric charge in the floating diffusion layer; cutting a DC component from the amplified voltage signal; applying a reference voltage to an output of the capacitor in response to a clamp pulse signal; and generating the clamp pulse signal.
Also, the generating may be achieved by generating the clamp pulse signal when the reset pulse signal is generated; and by stopping the generation of the clamp pulse signal when the supply of the reset pulse signal is stopped.
Here, the first time is preferably predetermined such that an output signal of the solid state imaging device corresponding to the electric charge stored in the floating diffusion layer has a reference voltage.
Also, the transfer clock signal may include a first transfer clock signal and a second transfer clock signal.
Also, a reset transistor may be formed from the floating diffusion layer, the reset drain, and a reset gate electrode supplied with the reset pulse signal, and a barrier transistor may be formed from the reset drain, the absorption drain and a barrier gate electrode supplied with a constant voltage.
Also, the stopping generation of the transfer clock signal may be achieved by stopping the generation of the transfer clock signal when the electric charge is read out from a pixel to the charge transfer section.
Hereinafter, a solid state imaging device such as a charge coupled device of the present invention will be described in detail with reference to the attached drawings.
Transfer gate electrodes 4a, 4b, 5a, and 5b are formed on the insulating film 3 from an upstream side to a downstream side in this order. A part of the transfer gate electrodes 4a and 5a is formed to cover the transfer gate electrode 4b, and a part of the transfer gate electrode 5a and a readout gate electrode 6 is formed to cover the transfer gate electrode 5b. A reset gate electrode 24 is formed on the insulating film 3 apart from the readout gate electrode 6, and a barrier gate electrode 25 is formed on the insulating film 3 apart from the reset gate electrode 24.
A barrier layer 7 is formed in a surface region of the n-type diffusion region 2 directly below each of the transfer gate electrodes 4a and 5a. Thus, the transfer gate electrodes 4a and 5a have shallow potential wells, while the transfer gate electrodes 4b and 5b have deep potential wells. A floating diffusion layer 21 is formed in a region of the n-type diffusion region 2 between the readout gate electrode 6 and the reset gate electrode 24. A reset drain 22 is formed in a region of the n-type diffusion region 2 between the reset gate electrode 24 and the barrier gate electrode 25. An absorption drain 23 is formed in a region of the n-type diffusion region 2 from the barrier gate electrode 25. Thus, a reset transistor 26 is formed from the floating diffusion layer 21, the reset gate electrode 24, and the reset drain 22, and a barrier transistor 27 is formed from the reset drain 22, the barrier gate electrode 5, and the absorption drain 23. In this configuration, the reset transistor 22 resets the charge stored the floating diffusion layer 21 and the absorption drain 23 stabilizes the voltage of the reset drain 22. The barrier transistor 27 is always operable since a constant voltage is applied to the barrier gate electrode 25.
The solid state imaging device of the present invention further includes a timing control circuit 28 and a boosting circuit 20. The timing control circuit 28 receives a main clock signal Φclk and generates first and second transfer clock signals Φ1 and Φ2, a readout gate signal VOG, a reset pulse signal ΦRS and a clamp pulse signal ΦCLP. The reset pulse signal ΦRS is a clock that is in phase with the first transfer clock signal Φ1, having a high level period shorter than that of the first transfer clock signal Φ1, and 5V as the high level and 0V as the low level. The boosting circuit 20 receives the first and second transfer clock signals Φ1 and Φ2, and generates a boosted voltage VDR0 of 12V. Thus, the boosting circuit 20 does not operate or stops its operation when the first and second transfer clock signals Φ1 and Φ2 are supplied. The first transfer clock signal Φ1 is supplied to the transfer gate electrodes 5a and 5b, and the second transfer clock signal Φ2 is supplied to the transfer gate electrodes 4a and 4b. Thus, a pair of the first transfer gate electrodes 5a and 5b operates in synchronization with the first transfer clock signal Φ1, and a pair of the second transfer gate electrodes 4a and 4b operates in synchronization with the second transfer clock signal Φ2. The readout gate signal VOG is supplied to the readout gate electrode 6, and the reset pulse signal ΦRS is supplied to the reset gate electrode 24. The reset drain 22 is connected with a resistance RL and the barrier gate electrode 25 is connected with a constant voltage source VB. The output VDRO of the boosting circuit 20 is connected with the absorption drain 23. The floating diffusion layer 21 is connected with a terminal CCDout.
Next, the configuration of an amplifier circuit in the solid state imaging device of the present invention will be described with reference to
An operation of the solid state imaging device in the embodiment of the present invention will be described below with reference to
The reset drain voltage VRD1 ought not change originally since the constant voltage VB is applied to the gate of the barrier transistor 27. However, when the gate length L of the reset transistor 26 is shortened in order to promptly discharge the charges stored in the floating diffusion layer 21 to the reset drain 22, the reset drain voltage VRD1 is easily influenced by the change of the output voltage VRD0 of the boosting circuit 20 and the reset drain voltage VRD1 also changes accordingly.
Here, at a time t3 prior to the time t2, the timing control circuit 28 supplies the reset pulse ΦRS to the reset gate electrode 24. Further, the timing control circuit 28 supplies the clamp pulse signal ΦCLP to the clamp transistor 8 of the clamp circuit in synchronization with the reset pulse signal ΦøRS.
In this way, as shown in
It should be noted that it is possible not to stop the supply of the reset pulse signal ΦRS and the clamp pulse signal ΦCLP, when the control of power consumption is unnecessary. In addition, in the embodiment of the present invention, the same clock signals are used for the charge transfer electrodes and the boosting circuit 20, but it could be understood to a person skilled in the art that the clock signals does not need to be the same.
According to the present invention, in a solid state imaging device provided with a boosting circuit, a stable output signal can be obtained without being affected through stop of the operation of the boosting circuit.
Also, according to the present invention, in the solid state imaging device provided with the boosting circuit, it is not necessary to provide the invalid pixels in order to obtain the stable output signal. Thus, it is possible to configure the solid state imaging device with a small circuit area.
Number | Date | Country | Kind |
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2004-268859 | Sep 2005 | JP | national |