Patent Application
20100224951
The present application claims priority from Japanese Patent Application No. JP 2009-055253 filed in the Japanese Patent Office on Mar. 9, 2009, the entire content of which is incorporated herein by reference.
1. Field of the Invention
The present invention relates to a solid-state imaging device, a method for producing the same, and an electronic apparatus. In particular, the invention relates to a solid-state imaging device having, in the image sensing area thereof, an image sensing element that captures an image of an object; a method for producing the same; and an electronic apparatus.
2. Description of the Related Art
An electronic apparatus such as a digital video camera or a digital still camera includes a solid-state imaging device. An example of such a solid-state imaging device included is a CMOS (Complementary Metal Oxide Semiconductor) image sensor.
As a solid-state imaging device, a CMOS image sensor provides the following advantages:
A CMOS logic LSI process can be applied.
Peripheral circuits can be formed on a chip.
Low-voltage driving is possible.
Power consumption is low.
In a CMOS image sensor, a plurality of image sensing elements that capture an image of an object are formed as pixels. The plurality of pixels each have a photoelectric converter so as to receive incident light and photoelectrically convert the received light, thereby generating signal charges. For example, a photodiode is formed as such a photoelectric converter. Further, an interconnect layer with a multilayer structure is provided to electrically connect the elements (see, e.g., JP-A-2005-278135 and JP-A-2005-323331).
The interconnect layer with a multilayer structure has a contact plug formed in the following manner: specifically, an insulation film is anisotropically etched to form a contact hole, and the contact hole is then filled with an electrically conductive material to provide the contact plug.
In such anisotropic etching, the etch selectivity is low between insulation films (SiO2-based films), element electrodes (polysilicon, tungsten), and the silicon substrate. Therefore, a SiN film is provided as an etching stopper layer on the electrodes (polysilicon, tungsten) and also on the silicon substrate. After etching to remove the insulation layer on the etching stopper layer, further etching is performed to remove the etching stopper layer. That is, the etching is completed in two steps (see, e.g., JP-A-2000-243832).
With respect to a CMOS image sensor, for the purpose of improving the image quality of a captured image, a method for suppressing dark current has been proposed.
In order to prevent dark current, hydrogenation is performed to terminate the silicon dangling bonds of the silicon semiconductor substrate, thereby reducing the interface state (see, e.g., JP-A-2004-165236 and JP-A-2003-229556).
In a CMOS image sensor, the peripheral circuits may cause noise, reducing the image quality of a captured image.
In particular, in an ADC (analog-to-digital-conversion circuit) that converts analog signals read out from image sensing elements row by row into digital signals, a comparator that compares such an analog signal with a reference signal has been found to be a random noise source.
In addition, a DAC (digital-to-analog converter circuit) that generates the reference signal has also been found to be a random noise source.
In preventing the generation of noise, it is effective to subject elements forming the peripheral circuits to the above-mentioned hydrogenation.
In the hydrogenation, however, above a peripheral circuit, an etching stopper layer for use in etching to form contact holes may interfere with the permeation of hydrogen, making it difficult to prevent the generation of noise. For example, an LP-SiN film formed by low-pressure CVD hardly allows the permeation of hydrogen, possibly causing the problem.
Further, above a peripheral circuit, metal interconnects are provided as a light-shielding film. Like the etching stopper layer, the metal interconnects may interfere with the permeation of hydrogen, making it difficult to prevent the generation of noise.
The image quality of a captured image is thus occasionally reduced due to peripheral circuits.
The invention thus provides a solid-state imaging device capable of improving the image quality of a captured image, a method for producing the same, and an electronic apparatus.
A method for forming a solid-state imaging device according to one embodiment of the invention includes: an element-forming process of forming a peripheral circuit element on a semiconductor substrate having an image sensing area where an image sensing element that captures an image of an object is provided and a peripheral area located on the periphery of the image sensing area, the peripheral circuit element being in the peripheral area; an insulation-film-forming process of forming a plurality of insulation films so as to cover at least the peripheral circuit element; a contact-hole-forming process of forming a contact hole through the plurality of insulation films and above the peripheral circuit element, the contact hole receiving a contact plug that is electrically connected to the peripheral circuit element; and a hydrogenation process of subjecting the semiconductor substrate having the plurality of insulation films to hydrogenation. The insulation-film-forming process includes: a first-insulation-film-forming step of forming as one of the insulation films a first insulation film; and a second-insulation-film-forming step of forming as one of the insulation films a second insulation film to cover the first insulation film. The contact-hole-forming process includes: a first etching step of etching the second insulation film so as to remove a portion thereof where the contact hole is to be formed; and a second etching step of, after the first etching step, etching the first insulation film so as to remove a portion thereof where the contact hole is to be formed. The first-insulation-film-forming step includes: forming the first insulation film to serve as an etching stopper layer during etching in the first etching step; and also forming the first insulation film to cover a portion where the contact hole is to be formed above the peripheral circuit element, with portions other than the portion where the contact hole is to be formed above the peripheral circuit element being exposed.
A solid-state imaging device according to an embodiment of the invention includes: a peripheral circuit element formed on a semiconductor substrate having an image sensing area where an image sensing element that captures an image of an object is provided and a peripheral area located on the periphery of the image sensing area, the peripheral circuit element being in the peripheral area; a plurality of insulation films formed to cover at least the peripheral circuit element; and a contact plug formed in a contact hole through the plurality of insulation films and above the peripheral circuit element in such a manner that the contact plug is electrically connected to the peripheral circuit element. The plurality of insulation films include a first insulation film and a second insulation film formed to cover the first insulation film. The contact hole is formed by etching the second insulation film so as to remove a portion thereof where the contact hole is to be formed, and then etching the first insulation film so as to remove a portion thereof where the contact hole is to be formed. The first insulation film is formed to serve as an etching stopper layer during etching of the second insulation film, and is also formed to cover a portion where the contact hole is to be formed above the peripheral circuit element, with portions other than the portion where the contact hole is to be formed above the peripheral circuit element being exposed.
An electronic apparatus according to an embodiment of the invention includes: a peripheral circuit element formed on a semiconductor substrate having an image sensing area where an image sensing element that captures an image of an object is provided and a peripheral area located on the periphery of the image sensing area, the peripheral circuit element being in the peripheral area; a plurality of insulation films formed to cover at least the peripheral circuit element; and a contact plug formed in a contact hole through the plurality of insulation films and above the peripheral circuit element in such a manner that the contact plug is electrically connected to the peripheral circuit element. The plurality of insulation films include a first insulation film and a second insulation film formed to cover the first insulation film. The contact hole is formed by etching the second insulation film so as to remove a portion thereof where the contact hole is to be formed, and then etching the first insulation film so as to remove a portion thereof where the contact hole is to be formed. The first insulation film is formed to serve as an etching stopper layer during etching of the second insulation film, and is also formed to cover a portion where the contact hole is to be formed above the peripheral circuit element, with portions other than the portion where the contact hole is to be formed above the peripheral circuit element being exposed.
According to an embodiment of the invention, the first insulation film is formed to serve as an etching stopper layer during etching to form contact holes in the second insulation film. Here, prior to the etching, the first insulation film is patterned to cover a portion where a contact hole is to be formed above a peripheral circuit element forming a peripheral circuit, with other portions being exposed. Accordingly, at the time of hydrogenation, the first insulation film (etching stopper layer) that interferes with the permeation of hydrogen is not formed at portions other than the portion where the contact hole is to be formed above the peripheral circuit element. As a result, the peripheral circuit element suitably receives the effect of hydrogenation.
According to some embodiments of the invention, a solid-state imaging device capable of improving the image quality of a captured image, a method for producing the same, and an electronic apparatus can be provided.
Embodiments of the invention are explained hereinafter with reference to the drawings.
The explanations will be given in following order.
1. Embodiments
2. Others
As shown in
The solid-state imaging device 1 receives, by an imaging surface PS thereof, light H (image of an object) entering through the optical system 42, and photoelectrically converts the light to generate signal charges. Here, the solid-state imaging device 1 is driven based on a drive signal that is output from the drive circuit 43. The signal charges are then read and output as raw data.
The optical system 42 is disposed to concentrate the incident light H of an image of an object to the imaging surface PS of the solid-state imaging device 1.
The drive circuit 43 outputs various drive signals to the solid-state imaging device 1 and the signal processing circuit 44, thereby driving the solid-state imaging device 1 and the signal processing circuit 44.
The signal processing circuit 44 is configured to process signals in the raw data output from the solid-state imaging device 1, thereby generating an digital image of the image of an object.
The following explains the overall configuration of the solid-state imaging device 1.
The solid-state imaging device 1 in this embodiment is a CMOS image sensor and includes a substrate 101 as shown in
The following explains the image sensing area PA.
As shown in
Specifically, as shown in
The image sensing area PA includes row control lines VL. The row control lines VL are each electrically connected to a plurality of pixels P aligned in the horizontal direction x in the image sensing area PA. The row control lines VL are placed side by side in the vertical direction y for a plurality pixels P aligned in the vertical direction y. That is, the row control lines VL are provided in such a manner that a first row control line VL1 to an n-th row control line VLn are connected to the rows of pixels P (first to n-th rows) in the image sensing area PA, respectively.
The image sensing area PA also includes column signal lines HL. The column signal lines HL are each electrically connected to a plurality of pixels P aligned in the vertical direction y in the image sensing area PA. The column signal lines HL are placed side by side in the horizontal direction x for the plurality pixels P aligned in the horizontal direction x. That is, the column signal lines HL are provided in such a manner that a first column signal line HL1 to an m-th column signal line HLm are connected to the columns of pixels P (first to m-th columns) in the image sensing area PA, respectively.
As shown in
In the pixel P, the photodiode 21 receives light of an image of an object, and photoelectrically converts the received light to generate and accumulate a signal charge. As shown in
In the pixel P, the transfer transistor 22 is interposed between the photodiode 21 and the floating diffusion FD, as shown in
In the pixel P, as shown in
In the pixel P, as shown in
In the pixel P, as shown in
When various pulse signals are supplied from peripheral circuits in the below-mentioned peripheral area SA via the row control lines VL to the pixels P, the pixels P are sequentially selected and driven horizontal line by horizontal line (pixel row by pixel row).
The following explains the peripheral area SA.
As shown in
The row scanning circuit 13 includes a shift register (not illustrated), and is configured to select and drive pixels P row by row. As shown in
Specifically, the row scanning circuit 13 outputs a reset pulse signal, a transfer pulse signal, and like various pulse signals via the row control lines VL to the pixels P row by row, thereby driving the pixels P.
The plurality of column signal lines HL are each electrically connected at one end thereof to the column circuit 14. The column circuit 14 is configured to process signals read out from the pixels P column by column.
As shown in
In the column circuit 14, a plurality of ADCs 400 are placed side by side in the horizontal direction x for the plurality pixel P columns placed side by side in the horizontal direction x in the image sensing area PA. That is, the ADCs 400 are provided in such a manner that a “first ADC 400-1” to an “m-th ADC 400-m” are provided for the columns of pixels P (first to m-th columns) in the image sensing area PA, respectively. In this manner, the plurality of ADCs 400 are mounted in parallel with the columns of pixels P. The plurality of ADCs 400 (400-1 to 400-m) are electrically connected to the plurality of column signal lines HL (HL1 to HLm) that are each provided for each column of pixels P, and performs A/D conversion of signals output from the pixels P column by column.
As shown in
In each of the ADCs 400 forming the column circuit 14, the comparator 411 is electrically connected to a column signal line HL as shown in
In each of the ADCs 400 forming the column circuit 14, the up/down counter 421 is electrically connected to the comparator 411 as shown in
When the up/down counter 421 receives the control signal CS2, the clock signal CK is given simultaneously with a DAC 501. In synchronization with the clock signal CK, the up/down counter 421 alternately performs counting down (DOWN) and counting up (UP). The up/down counter 421 thereby measures the period of the comparison by the comparator 411.
The comparator 411 and the up/down counter 421 forming an ADC 400 thus convert an analog signal output via a column signal line HL from a pixel P in the image sensing area PA into an N-bit digital signal.
In each of the ADCs 400 forming the column circuit 14, the transfer switch 431 is configured to switch the connection to the up/down counter 421 as shown in
Specifically, the transfer switch 431 turns on at the time when the up/down counter 421 completes counting about a pixel P in a certain row, and transfers the obtained count value to the memory 441.
In each of the ADCs 400 forming the column circuit 14, the memory 441 is electrically connected to the transfer switch 431 as shown in
The reference voltage supply 15 is electrically connected to the comparators 411 as shown in
Specifically, the reference voltage supply 15 includes a DAC 501. Under control of the control signal CS1 output from the timing control circuit 18, the DAC 501 generates the reference voltage Vref of a ramp waveform based on the clock signal CK.
The column scanning circuit 16 includes a shift register (not illustrated), and is configured to select the column of pixels P and output a digital signal from the column circuit 14 to a horizontal output line 17. The column scanning circuit 16 is electrically connected to the plurality of ADCs 400 forming the column circuit 14 as shown in
The horizontal output line 17 is electrically connected to the column circuit 14 as shown in
The timing control circuit 18 is configured to, based on a master clock CK0, generate a drive signal for each component and then output the signal to each component.
As shown in
Specifically, as shown in
The reference voltage Vref of a ramp waveform is applied to the comparator 411 of an ADC 400 via the DAC 501, as shown in
The clock signal CK is applied from the timing control circuit 18 to the up/down counter 421, as shown in
Next, as shown in
The output Vco is applied to the up/down counter 421, as shown in
At this time, in the up/down counter 421, as shown in
Subsequently, as shown in
As mentioned above, in the A/D conversion period, after the completion of the first readout, the second readout is performed as shown in
In the second readout, as shown in
Specifically, as shown in
Here, in response to the application of the reference voltage Vref of a ramp waveform, the comparator 411 compares the signal voltage Vx of the column signal line HL with the reference voltage Vref. The reference voltage Vref in the second readout is applied so that the slope of the ramp waveform is the same as in the first readout.
Further, in response to the application of the clock signal CK, the up/down counter 421 measures the comparison time of the comparator 411. Unlike the first readout, the measurement is performed by an up-count operation as shown in
Accordingly, the up/down counter 421 performs a subtraction of the “first comparison period” from the “second comparison period”.
Next, as shown in
At this time, as shown in
The count value obtained by subtracting the “first comparison period” from the “second comparison period” has the following relation. Specifically, by the above subtraction, not only the reset component ΔV but also the offset component of the ADC 400 is removed.
(Second comparison period)−(first comparison period)=(Vsig+ΔV+offset component of ADC 400)−(ΔV+offset component of ADC 400)=Vsig
Subsequently, as shown in
Thus, in this embodiment, CDS (Correlated Double Sampling) processing as above is performed to make conversion into a digital signal.
After the A/D conversion, the thus-generated n-bit digital signal is retained in the up/down counter 421.
Subsequently, as shown in
The following provides a detailed explanation of the solid-state imaging device 1 according to this embodiment.
The solid-state imaging device 1 includes pixels P in the image sensing area PA as shown in
In addition, although not illustrated in
The peripheral area SA includes peripheral circuits SK.
For example, the transistor 311 is a semiconductor element that forms the above-mentioned comparator 411 (see
In addition, although not illustrated in
The substrate 101 has formed thereon an interconnect layer 500.
The interconnect layer 500 includes insulation films 511 to 519, contact plugs CP, and metal interconnects HW, as shown in
As shown in
As shown in
Of the plurality of insulation films 511 to 519, the second insulation film 512 is laminated on the top surface of the first insulation film 511 as shown in
As described below in detail, in this embodiment, the second insulation film 512 is formed to serve as an etching stopper layer during anisotropic etching to form a contact hole CH in the third insulation film 513. As mentioned above, in anisotropic etching, the etch selectivity is low between insulation films (SiO2-based), element electrodes (polysilicon, tungsten), and the substrate 101 (silicon substrate). Therefore, the second insulation film 512 is formed as an etching stopper layer.
Although not illustrated in
Thus, the contact hole CH in the second insulation film 512 is formed by etching the second insulation film 512 after etching the third insulation film 513. That is, the third insulation film 513, an upper layer, is etched so as to remove a portion thereof where a contact hole is to be formed. Subsequently, the second insulation film 512 is etched so as to remove a portion thereof where a contact hole is to be formed. Contact holes CH are thus formed in the second insulation film 512.
Of the plurality of insulation films 511 to 519, the third insulation film 513 is laminated on the top surface of the second insulation film 512 as shown in
Of the plurality of insulation films 511 to 519, the fourth insulation film 514 is laminated on the top surface of the third insulation film 513 as shown in
Of the plurality of insulation films 511 to 519, the fifth insulation film 515 is laminated on the top surface of the fourth insulation film 514 as shown in
Of the plurality of insulation films 511 to 519, the sixth insulation film 516 is laminated on the top surface of the fifth insulation film 515 as shown in
Of the plurality of insulation films 511 to 519, the seventh insulation film 517 is laminated on the top surface of the sixth insulation film 516 as shown in
Of the plurality of insulation films 511 to 519, the eighth insulation film 518 is laminated on the top surface of the seventh insulation film 517 as shown in
Of the plurality of insulation films 511 to 519, the ninth insulation film 519 is laminated on the top surface of the eighth insulation film 518 as shown in
As shown in
Specifically, as shown in
Further, as shown in
Further, as shown in
Each contact plug CP has a barrier metal BM on the bottom and the side thereof as shown in
In the interconnect layer 500, as shown in
Specifically, as shown in
Further, as shown in
Further, as shown in
As shown in
In this embodiment, as shown in
The following explains important parts of a method for producing the above-described solid-state imaging device 1.
(1) Formation of Image sensing elements and Peripheral Circuit Elements
First, as shown in
In the image sensing area PA, as a part of the image sensing element forming a pixel P, the photodiode 21 and the transfer transistor 22 are provided on the substrate 101 as shown in
In the peripheral area SA, as some of the peripheral circuit elements forming a peripheral circuit SK, the transistor 311 and the capacitor 312 are provided. For example, the transistor 311 is provided as a semiconductor element that forms the above-mentioned comparator 411 (see
Next, as shown in
The first insulation film 511 is formed as a SiO2 film, for example.
Next, as shown in
Here, the second insulation film 512 is formed to serve as an etching stopper layer during etching of the below-mentioned third insulation film 513. That is, the second insulation film 512 is formed to provide a high etch selectivity with respect to the third insulation film 513.
Specifically, the second insulation film 512 is formed under the following conditions to have the following characteristics, so that the second insulation film 512 serves as an etching stopper layer.
Temperature: 700° C. to 800° C.
Pressure: 20 Pa to 40 Pa
Film formation rate: 1 nm/min to 5 nm/min
Gas: SiH2Cl2/NH3=160/1600 sccm
Film thickness: 10 nm to 50 nm
Density: in wet etching using DHF, the etch rate with respect to P-SiN=1/5 to 1/20
The thus-formed second insulation film 512 is an LP-SiN film having a thickness of a few tens of nanometers, for example. That is, a film of silicon nitride is formed by low-pressure CVD to give the second insulation film 512.
Next, as shown in
Here, the second insulation film 512 is processed to cover a portion where a contact hole (not illustrated) is to be formed above a peripheral circuit element forming a peripheral circuit SK, with portions other than the portion where the contact hole (not illustrated) is to be formed being exposed (see
Specifically, the second insulation film 512 is processed to cover a portion where a contact hole (not illustrated) is to be formed above the transistor 311 that is the semiconductor element forming the comparator 411 (see
At the same time, the second insulation film 512 is processed not to cover the top surface of the light-receiving surface JS of the photodiode 21.
Specifically, a photomask is formed by photolithography, and then the second insulation film 512 is etched using the photomask; the second insulation film 512 is thus processed as above.
Next, as shown in
Here, as the third insulation film 513, an SiO2 film such as an LP-TEOS film is formed to a thickness of a few hundreds of nanometers, for example. The surface thereof is then planarized to give the third insulation film 513. The surface planarization is performed by CMP (Chemical Mechanical Polishing), for example.
Next, as shown in
Here, the contact holes CH are formed in the third insulation film 513 so that the contact holes CH pass through portions corresponding to the portions where contact plugs CP (see
Specifically, a photoresist mask (not illustrated) is formed by photolithography, and then the third insulation film 513 is subjected to anisotropic dry etching using the photoresist mask, thereby forming the contact holes CH. The contact holes CH are thus formed in such a manner that the sides of the contact holes CH extend along the direction z that is perpendicular to the plane of the substrate 101.
In this embodiment, the above dry etching is performed so that the second insulation film 512 located under the third insulation film 513 serves as an etching stopper layer. Specifically, the dry etching is performed to secure sufficient etch selectivity between the SiN film, i.e., the second insulation film 512, and the SiO2 film, i.e., the third insulation film 513.
The dry etching is performed under the following conditions, for example.
Pressure: 30 mTorr
Gas: Ar/C4F6/CO/O2=900/21/40/21 sccm
Power: 2000/2400 W
Next, as shown in
Here, the contact holes CH are formed in the first and second insulation films 511 and 512 in such a manner that the contact holes CH formed in the third insulation film 513 further extend downwards.
Specifically, in the same manner as above, the first and second insulation films 511 and 512 are subjected to anisotropic dry etching to form the contact holes CH. As a result, the surface of an electrode or a diffusion layer of an element in the lower layer is exposed, whereby the contact holes CH are formed.
In this embodiment, the dry etching is performed to secure sufficient etch selectivity between electrodes (e.g., polysilicon) or diffusion layers (Si) of the elements in the lower layer and the first and second insulation films 511 and 512 (SiO2 film and SiN film).
The dry etching is performed under the following conditions, for example.
[Second insulation film 512 (SiN film)]
[First insulation film 511 (SiO2 film)]
The hydrogenation is performed under the following conditions, for example.
Temperature: 350° C. to 400° C.
Time: 60 min to 1200 min
Gas: H2/N2=4/96 to 100/0 or D2/N2, or T2/N2
TTL flow rate: 10000 sccm
Next, as shown in
Here, after applying a barrier metal BM to cover the bottom and the side of each contact hole CH, the contact hole CH is filled with a metal material, thereby giving a contact plug CP. The contact plugs CP are formed using tungsten, for example.
As a result, the contact plugs CP are formed making electrical connection to the image sensing element forming a pixel P or the peripheral circuit elements forming a peripheral circuit SK.
(9) Formation of Metal Interconnects HW and so forth
Next, as shown in
The metal interconnects HW are formed on the third insulation film 513. The metal interconnects HW are formed using aluminum, for example.
Then, the fourth insulation film 514 is formed to cover the metal interconnects HW provided on the top surface of the third insulation film 513.
Then, as shown in
Subsequently, other components are formed as shown in
The hydrogenation is performed under the following conditions, for example.
Temperature: 350° C. to 400° C.
Time: 60 min to 1200 min
Gas: H2/N2=4/96 to 100/0 or D2/N2, or T2/N2
TTL flow rate: 10000 sccm
A solid-state imaging device 1 is thus completed.
In summary, as described above, in this embodiment, the second insulation film 512 is formed to serve as an etching stopper layer during etching to form contact holes CH in the third insulation film 513. Here, prior to the etching, the second insulation film 512 is patterned to cover a portion where a contact hole is to be formed above a peripheral circuit element forming a peripheral circuit SK, with other portions being exposed. In particular, the second insulation film 512 is patterned to cover a portion where a contact hole is to be formed above a peripheral circuit element such as the transistor 311 forming the comparator 411 that compares an analog signal output from a pixel P with a reference signal, with other portions being exposed. Hydrogenation is subsequently performed.
In this embodiment, at the time of hydrogenation, the second insulation film (etching stopper layer) that interferes with the permeation of hydrogen is not formed at portions other than a portion where a contact hole is to be formed above a peripheral circuit element such as the transistor 311. That is, of the plurality of insulation films 511 to 519 forming the interconnect layer 500, the second insulation film 512, which has lower hydrogen permeability than other insulation films 511 and 513 to 519, is formed only at the above portion. As a result, a peripheral circuit element such as the transistor 311 suitably receives the effect of hydrogenation.
Accordingly, in this embodiment, the captured image quality can be prevented from being reduced due to peripheral circuits SK. Therefore, the captured image quality can be improved.
Further, in this embodiment, a metal interconnect HW is provided at a portion where a contact hole CH is formed above a peripheral circuit element such as the transistor 311, and no metal interconnect HW is provided at other portions. Hydrogenation is subsequently performed.
That is, at the time of hydrogenation, like the second insulation film 512, the metal interconnect HW that interferes with the permeation of hydrogen is formed only at a portion where a contact hole is to be formed above a peripheral circuit element such as the transistor 311. As a result, the peripheral circuit element such as the transistor 311 suitably receives the effect of hydrogenation.
The invention is not limited to the above embodiment, and various modifications can be made thereto.
The above embodiment describes the case where the second insulation film 512 is patterned to cover a portion where a contact hole is to be formed above the transistor 311 forming the comparator 411, with other portions being exposed. The above embodiment also describes the case where a metal interconnect HW is provided at a portion where a contact hole is formed above the transistor 311 forming the comparator 411, and is not provided at other portions.
However, the invention is not limited to the case of the transistor 311 forming the comparator 411.
For example, the second insulation film 512 may also be patterned to cover a portion where a contact hole is to be formed above a peripheral circuit element such as the transistor forming the DAC 501 that generates the reference signal (reference voltage Vref), with other portions being exposed. Likewise, the metal interconnect HW may also be provided at a portion where a contact hole is formed above the transistor forming the DAC 501, with no metal interconnect HW being provided at other portions.
As mentioned above, it has been found out that a DAC 501 can also cause random noise. Therefore, the same effects as in the above embodiment can be provided.
Further, although the above embodiment describes the case where hydrogenation is performed twice, the invention is not limited thereto. For example, the invention is also applicable to the case where hydrogenation is performed once. Further, the invention is also applicable to the case where hydrogenation is performed three times.
Further, although the above embodiment describes the case where the invention is applied to the camera 40, the invention is not limited thereto. The invention is also applicable to a scanner, a copier, or a like electronic apparatus equipped with a solid-state imaging device.
The solid-state imaging device 1 in the above embodiment is an example of the solid-state imaging device of the invention. The camera 40 in the above embodiment is an example of the electronic apparatus of the invention. The substrate 101 in the above embodiment is an example of the semiconductor substrate of the invention. The transistor 311 in the above embodiment is an example of the peripheral circuit element of the invention. The comparator 411 in the above embodiment is an example of the comparator of the invention. The DAC 501 in the above embodiment is an example of the digital-to-analog converter circuit of the invention. The second insulation film 512 in the above embodiment is an example of the first insulation film of the invention. The third insulation film 513 in the above embodiment is an example of the second insulation film of the invention. The contact hole CH in the above embodiment is an example of the contact hole of the invention. The contact plug CP in the above embodiment is an example of the contact plug of the invention. The metal interconnect HW in the above embodiment is an example of the metal interconnect of the invention. The pixel P in the above embodiment is an example of the image sensing element of the invention. The image sensing area PA in the above embodiment is an example of the image sensing area of the invention. The peripheral area SA in the above embodiment is an example of the peripheral area of the invention.
It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| P2009-055253 | Mar 2009 | JP | national |
