BRIEF DESCRIPTION OF THE DRAWINGS
The objects and features of the present invention will become more apparent from consideration of the following detailed description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a schematic block diagram showing a preferred embodiment of a two-line readout CCD implemented as a solid state imaging device according to the present invention;
FIG. 2 is a schematic block diagram showing a preferred embodiment of a digital camera employing the solid state imaging device of FIG. 1;
FIG. 3 is a schematic block diagram showing drivers shown in FIG. 2;
FIG. 4, part (A) is a partial plan view looked from above, and showing the schematic constitution of a horizontal transfer path in the solid state imaging device of FIG. 1, part (B) is a cross-sectional view of the transfer path, taken along a section line IV-IV, and parts. (C) and (D) show how the potential changes in various parts of the horizontal transfer path;
FIG. 5 is a timing chart showing the timing of drive signals supplied to respective electrodes of FIG. 4, parts (A) and (B);
FIG. 6, part (A) continuing from the lower part of FIG. 4 is a cross-sectional view of the transfer path, and parts (B), (C) and (D) show how the potential changes;
FIG. 7, part (A) is a partial plan view, looking from above, showing the schematic constitution of the horizontal transfer path in the device of FIG. 1, part (B) is a cross-sectional view of the transfer path, taken along a section line VII-VII, and parts (C) and (D) show how the potential changes in various parts of the horizontal transfer path;
FIG. 8, part (A) continuing from the lower part of FIG. 7 is a cross-sectional view of the transfer path, and parts (B), (C) and (D) show how the potential changes;
FIGS. 9A to 9E are schematic views for illustrating the transfer of signal charge with color attributes over horizontal transfer paths in the solid state imaging device of FIG. 1;
FIGS. 10A and 10B schematically show the difference in gate capacitances in the output amplifier of FIG. 1;
FIGS. 11A and 11B schematically show the difference in film thickness formed in the floating diffusion in the output amplifier of FIG. 1;
FIGS. 12A and 12B schematically show the difference in the surface area in the floating diffusion in the output amplifier of FIG. 1;
FIGS. 13A and 13B schematically show the presence and the absence of a film formed in the floating diffusion in the output amplifier of FIG. 1, respectively;
FIG. 14 is a partial plan view of an array of offset pixels and color filter segments in the solid state imaging device of FIG. 1;
FIGS. 15 and 16 are timing charts showing re-arraying of signal charges of the first and second fields during the horizontal blanking period in connection with horizontal transfer of the device of FIG. 14, respectively;
FIG. 17 is a timing chart showing the relationship of the drive signals supplied for the first field and the output signals in connection with horizontal transfer of the device;
FIG. 18 is a timing chart showing the relationship of low-speed readout drive signals ad output signal in the horizontal transfer of the device;
FIG. 19 is a schematic block diagram showing a three-line readout solid state imaging device applied to the imaging unit of FIG. 2;
FIG. 20 is a timing chart showing the relationship between the drive signals and the output signals as applied to the horizontal transfer for the device of FIG. 19;
FIG. 21 is a schematic block diagram showing a four-line readout solid state imaging device applied to the imaging unit of FIG. 2;
FIG. 22 is a timing chart showing the relationship between the drive signals and the output signals as applied to the horizontal transfer for the device of FIG. 21;
FIG. 23 is a schematic block diagram showing an alternative embodiment of a solid state imaging apparatus according to the present invention;
FIG. 24 is a timing chart useful for understanding an operational sequence of horizontal transfer consistent with horizontal timing signals of the initial driving condition at the time of high speed driving in the solid state imaging device of FIG. 1;
FIG. 25 is a timing chart useful for understanding an operational sequence of horizontal transfer consistent with horizontal timing signals of the inverted-branching driving condition at the time of high speed driving in the device of FIG. 1;
FIG. 26 is a timing chart also useful for understanding an operational sequence of horizontal transfer at the time of low-speed driving in the device of FIG. 1;
FIG. 27 schematically shows signal charges being transferred responsive to the horizontal timing signals of the initial driving condition at the time of transfer efficiency measurement on the horizontal transfer path in the device of FIG. 1:
FIG. 28 schematically shows signal charges being transferred responsive to the horizontal timing signals of the inverted-branching driving condition at the time of transfer efficiency measurement on the horizontal transfer path in the device of FIG. 1;
FIG. 29 is a graph showing the relationship between the quantity of residual transfer charges and the quantity of reference signals on two branching transfer paths in the device of FIG. 1:
FIG. 30 is a graph showing the relationship between the transfer efficiency and the quantity of the reference signals;
FIG. 31 is a timing chart useful for understanding the operational sequence of mixing of horizontal pixels on a horizontal transfer path before branching in the device of FIG. 1;
FIGS. 32A through 32I showing how the potential level changes which is formed in the respective transfer elements by horizontal pixel mixing on the horizontal transfer path before branching in the device of FIG. 1;
FIGS. 33 and 34 are block diagrams schematically showing changes in the output destination, consistent with the transfer efficiency on the branching horizontal transfer paths in the device of FIG. 1;
FIG. 35 schematically shows horizontal transfer paths in the device of FIG. 1, looked from above;
FIG. 36, parts (A) and (B) are a schematic plan view and a schematic cross-sectional view of one of the horizontal transfer paths shown in FIG. 35, respectively;
FIG. 37, parts (A) and (B) are a schematic plan view and a schematic cross-sectional view of the other of the horizontal transfer paths shown in FIG. 35, respectively;
FIG. 38 is a timing chart showing the timing of drive signals supplied to the respective electrodes shown in FIG. 35;
FIG. 39 is a schematic potential diagram showing the state of transfer of signal charges on the horizontal transfer path in FIG. 36;
FIG. 40 is a schematic potential diagram showing the state of transfer of signal charges on the horizontal transfer path in FIG. 37;
FIGS. 41A to 41E schematically show the state of transfer of signal charges on the horizontal transfer path in FIG. 35;
FIG. 42 is a schematic timing chart showing an example of the timing of drive signals supplied to the respective electrodes shown in FIG. 35;
FIG. 43 is a schematic timing chart showing another example of the timing of drive signals supplied to the respective electrodes shown in FIG. 35;
FIG. 44 is a flowchart useful for understanding illustrative processing for calculating the transfer efficiency;
FIGS. 45 and 46 schematically show illustrative processing for calculating the transfer efficiency on one and the other of the horizontal transfer paths, respectively;
FIG. 47 is a graph schematically showing the residual charge quantities detected from one reference signal to another;
FIG. 48 is a graph schematically showing the transfer efficiency calculated from the residual signal quantities shown in FIG. 47;
FIG. 49 is a flowchart showing illustrative processing of calculating the transfer efficiency by the processing sequence shown in FIG. 44 and for setting a variable value of the duty cycle using the transfer efficiency calculated;
FIG. 50 is a block diagram schematically showing a further alternative embodiment of a digital camera employing the device of FIG. 1;
FIG. 51 is a plan view looked from above, showing a horizontal transfer path in the device of FIG. 1;
FIG. 52 is a partial cross-sectional view showing essential part of a horizontal transfer path of FIG. 51;
FIG. 53 is a partial plan view of an array of offset pixels and color filter segments as applied to the device of FIG. 1;
FIGS. 54A through 54E and 55A through 55E schematically show transfer of signal charges R and B, and signal charges G on the horizontal transfer path of FIG. 1, respectively;
FIG. 56 is a timing chart showing the supply timing of drive signal to the electrode of FIG. 51;
FIGS. 57A through 61B schematically show the potential levels generated on the horizontal transfer path when the drive signal shown in FIG. 56 is applied;
FIG. 62 is a timing chart showing the timing of drive signals supplied to the electrodes of FIG. 55 on transferring the signal charge G;
FIGS. 63A through 64B schematically show the potential level generated on applying the drive signal shown in FIG. 62;
FIGS. 65 and 66 are timing charts showing drive signals for providing the same color of the signal charges output from the same output amplifier in the first and second lines; and
FIGS. 67A to 67E schematically illustrate the transfer of signal charges G in two horizontal transfer paths.