Patent Application
20130148000
The present invention relates to metal oxide semiconductor (MOS) and complementary metal oxide semiconductor (COMS) solid-state imaging devices (hereinafter referred to as a MOS solid-state imaging device) that are incorporated into, for example, a digital camera.
In recent years, a technique as recited in Patent Literature 1 has been suggested to achieve a high-speed shutter operation using a CMOS image sensor (MOS solid-state imaging device). There has been a trend in recent years towards an increase in the number of pixels used in a MOS solid-state imaging device. An increase has been also seen in the amount of signals that are processed by a signal processing circuit in a MOS solid-state imaging device and a signal processing circuit in a digital camera and others having a MOS solid-state imaging device. Here, when high-speed signal processing is required, for example, for capturing video, pixel signals are combined to reduce the amount of signals to be processed. The following describes the example of a pixel signal combining method of a conventional MOS solid-state imaging device, with reference to
In this circuit, after a signal from a first pixel and a signal from a second pixel are stored in a capacitor 207 and a capacitor 208, respectively, a switch 209 including a MOS transistor becomes conductive so that the signals from the first and second pixels are combined and outputted to an output line 210.
Such a technique can reduce the amount of signals to be processed, as compared to when pixel signals are not combined.
However, the operation mode of the MOS solid-state imaging device recited in Patent Literature 1 has a problem that video distortion is caused by different timing of reading pixel signals for each pixel group due to the function of a focal-plane shutter.
Here, the present invention has been made in view of the above problem, and an object of the present invention is to provide a MOS solid-state imaging device that achieves less video distortion compared to that of a conventional one.
To achieve the above object, a solid-state imaging device according to an embodiment of the present invention includes: pixels arrayed two-dimensionally, each of which outputs an electrical signal in a reset state and an electrical signal in a light-received state; column signal lines each of which corresponds to one of columns of the pixels and transmits an electrical signal in the reset state and an electrical signal in the light-received state, from the corresponding column of the pixels; first holding circuit units each of which corresponds to one of the column signal lines, and holds electrical signals in the reset state and electrical signals in the light-received state that are transmitted from the pixels through the corresponding one of the column signal lines; and first difference circuit units that each output a difference between one of the electrical signals in the reset state and one of the electrical signals in the light-received state that are held by one of the first holding circuit units, in which the first holding circuit units each include pixel-wise holding circuits, the number of which is identical to the number of the pixels provided for the corresponding one of the column signal lines, the pixel-wise holding circuits being able to hold electrical signals in the reset state of the pixels and electrical signals in the light-received state of the pixels.
According to such a configuration, a pixel-wise holding circuit is provided for one pixel. This allows the first holding circuit units to hold signals from all of the pixels at high speed and separately. Therefore, it is possible to read the signals from the pixels and output to the first holding circuits at high speed. As a result, differences in light exposure time between pixels are reduced, as compared to when the function of a conventional focal-plane shutter is used. Therefore, video distortion can be reduced than before.
Moreover, the solid-state imaging device may further include a row selection circuit that (i) selects the pixels on a row basis, causes the selected pixels in a row to output, to the column signal lines, electrical signals in the reset state of the selected pixels and electrical signals in the light-received state of the selected pixels, (ii) simultaneously selects at least two rows of the pixel-wise holding circuits included in the first holding circuit units, and (iii) causes the first difference circuit units to simultaneously output the electrical signals in the reset state and the electrical signals in the light-received state that are held by the selected pixel-wise holding circuits.
According to such a configuration, after signals from pixels are stored in pixel-wise holding circuits, several pixel-wise holding circuits are simultaneously selected and the signals are outputted to the first difference circuit units. Therefore, noise can be averaged and reduced.
Moreover, the solid-state imaging device may further include: second holding circuit units that each hold output from one of the first difference circuit units; and second difference circuit units that each output a difference between a reference signal and output from one of the second holding circuit units.
More specifically, the solid-state imaging device includes the second holding circuit units that each include pixel-wise holding circuits each of which is capable of holding a differential signal indicating a difference between an electrical signal in the reset state and an electrical signal in the light-received state of one of the pixels, and the solid-state imaging device further includes a row selection circuit successively selects at least two rows of the pixel-wise holding circuits included in the second holding circuit units, and to cause the second difference circuit units to output differential signals held by the selected pixel-wise holding circuits.
According to this configuration, differential signals are held by the second holding circuit units, and it is possible to process signals by combining the differential signals.
As mentioned above, a solid-state imaging device according to the present invention can provide a solid-state imaging device that achieves less video distortion.
These and other objects, advantages and features of the invention will become apparent from the following description thereof taken in conjunction with the accompanying drawings that illustrate a specific embodiment of the present invention.
The following describes a solid-state imaging device according to the embodiments of the present invention with reference to the drawings.
It should be noted that in the drawings, the same reference numerals are given to elements representing substantially the same configurations, operations, and effects. Moreover, although connection relationships between structural elements are exemplified to specifically describe the present invention, connection relationships that achieve the functions of the present invention are not limited to the exemplified connection relationships.
The first embodiment of the present invention will be described,
The solid-state imaging device shown in
The pixel circuit unit 1 includes pixels that are arrayed two-dimensionally (in a matrix) and each of which outputs an electrical signal in a reset state (i.e., a state in which light is not received at a pixel) and an electrical signals in a light-received state (i.e., a state in which light is received at a pixel). The pixel circuit unit 1 outputs, to the first column signal lines 7, electrical signals in the reset state of pixels and electrical signals in the light-received state of the pixels.
The first column signal lines 7 each correspond to one of the columns of pixels, and transmit electrical signals in the reset state and electrical signals in the light-received state, from the corresponding column of pixels.
The first holding circuit units 2 each correspond to one of the first column signal lines 7, and hold electrical signals in the reset state and in the light-received state transmitted from pixels through the corresponding first column signal line 7. The first holding circuit units 2 each include pixel-wise holding circuits, the number of which is identical to the number of pixels provided for the corresponding first column signal line 7. The pixel-wise holding circuits can hold electrical signals in the reset state and in the light-received state of pixels.
The first difference circuit unit 3 outputs a differential signal indicating a difference between an electrical signal in the reset state and an electrical signal in the light-received state which are held by the first holding circuit unit 2. This differential signal is synchronized with the output of the column selection circuit 5 and outputted to the output line 4.
The row selection circuit 6 (i) selects pixels in the pixel circuit unit 1 on a row basis, (ii) causes the selected pixels in a row to output, to the first column signal lines 7, electrical signals in the reset state and light received state of the selected pixels, (iii) selects pixel-wise holding units of several rows at the same time or on a row basis, and (iv) causes the first difference circuit units 3 to output electrical signals in the reset state and the light-received state held at the selected pixel-wise holding units.
It should be noted that the row selection circuit (vertical scanning circuit) 6 and the column selection circuit (horizontal scanning circuit) 5 include circuits capable of scanning such as a shift register and a decoder. For instance, the row selection circuit 6 may include a Y decoder circuit that decodes row addresses each indicating the row of the first holding circuit units 2 to output row selection signals to the first holding circuit units 2. In addition, the column selection circuits 5 may each include a X decoder circuit that decodes a column address indicating the column of one of the first holding circuit units 2 to output a column selection signal to one of the first holding circuit units 2 or one of the first difference circuit units 3. This facilitates random access to the first holding circuit units 2. For instance, it is possible to easily achieve readout of any pixel or area or readout of any rectangular area from an image represented by electrical signals held by the first holding circuit units 2. Moreover, it is possible to easily achieve every K-row readout (K is an integer greater than or equal to 2), every L-column readout (L is an integer greater than or equal to 2), or thinning-out readout (reduction readout) that combined these readouts.
The pixel 1-1 includes a photodiode 10, a transfer MOS transistor 11, a reset MOS transistor 12, and an output MOS transistor 13. As same as the pixel 1-1, the pixel 1-2 includes a photodiode 15, a transfer MOS transistor 16, a reset MOS transistor 17, and an output MOS transistor 18.
In the pixel 1-1, the anode of the photodiode 10 is earthed and, the cathode of the photodiode 10 is connected to the drain of the transfer MOS transistor 11. The source of the transfer MOS transistor 11 is connected to the source of the reset MOS transistor 12 and the gate of the output MOS transistor 13. The gate of the transfer MOS transistor 11 is connected to a terminal 23. The connection area of the gate of the output MOS transistor 13, the source of the reset MOS transistor 12, and the source of the transfer MOS transistor 11 forms diffusion capacitance called floating diffusion (hereinafter referred to as FD). The drain of the reset MOS transistor 12 is connected to a power supply, and the gate of the reset MOS transistor 12 is connected to a terminal 22. The drain of the output MOS transistor 13 is connected to the power supply, and the source of the output MOS transistor 13 is connected to the drain of a row selection MOS transistor 14. A current source 20 is connected to the first column signal line 7. When the gate of the row selection MOS transistor 14 is connected to a terminal 24, and the row selection. MOS transistor 14 is conducting, the row selection MOS transistor 14 forms a source follower circuit together with the output MOS transistor 13 and the current source 20.
Also in the pixel 1-2, the anode of the photodiode 15 is earthed and, the cathode of the photodiode 15 is connected to the drain of the transfer MOS transistor 16. The source of the transfer MOS transistor 16 is connected to the source of the reset MOS transistor 17 and the gate of the output. MOS transistor 18. The gate of the transfer MOS transistor 16 is connected to a terminal 26. The connection area of the gate of the output MOS transistor 18, the source of the reset MOS transistor 17, and the source of the transfer MOS transistor 16 forms diffusion capacitance called FD. The drain of the reset MOS transistor 17 is connected to a power supply, and the gate of the reset MOS transistor 17 is connected to a terminal 25. The drain of the output MOS transistor 18 is connected to the power supply, and the source of the output MOS transistor 18 is connected to the drain of a row selection MOS transistor 19. When the gate of the row selection MOS transistor 19 is connected to a terminal 27, and the row selection MOS transistor 19 is conducting, the row selection MOS transistor 19 forms a source follower circuit together with the output MOS transistor 18 and the current source 20.
The output from the pixels 1-1 and 1-2 is connected to the first column signal line 7 via the row selection MOS transistors 14 and 19. The first column signal line 7 is connected to one of the first holding circuit units 2 in
The pixel-wise holding circuit 2-1 includes MOS transistors 31, 33, 34, and 36, and capacitors 32 and 35. The drain of the MOS transistor 31 is connected to the first column signal line 7. The source of the MOS transistor 31 is connected to one terminal of the capacitor 32 and the drain of the MOS transistor 33. The gate of the MOS transistor 31 is connected to a terminal 43. The other terminal of the capacitor 32 is earthed. The source of the MOS transistor 33 is connected to the gate of a MOS transistor 54, and the gate of the MOS transistor 33 is connected to a terminal 44. The drain of the MOS transistor 34 is connected to the first column signal line 7. The source of the MOS transistor 34 is connected to one terminal of the capacitor 35 and the drain of the MOS transistor 36. The gate of the MOS transistor 34 is connected to a terminal 46. The other terminal of the capacitor 35 is earthed. The source of the MOS transistor 36 is connected to the gate of a MOS transistor 54, and the gate of the MOS transistor 36 is connected to a terminal 45. The drain of the MOS transistor 54 is connected to a power supply, and the source of the MOS transistor 54 is connected to the drain of a row selection MOS transistor 53. The gate of the row selection MOS transistor 53 is connected to a terminal 57, and the source of the row selection MOS transistor 53 is connected to the second column signal line 8.
The pixel-wise holding circuit 2-2 includes MOS transistors 37, 39, 40, and 42, and capacitors 38 and 41. The drain of the MOS transistor 37 is connected to the first column signal line 7. The source of the MOS transistor 37 is connected to one terminal of the capacitor 38 and the drain of the MOS transistor 39. The gate of the MOS transistor 37 is connected to a terminal 47. The other terminal of the capacitor 38 is earthed. The source of the MOS transistor 39 is connected to the gate of a MOS transistor 56, and the gate of the MOS transistor 39 is connected to a terminal 48. The drain of the MOS transistor 40 is connected to the first column signal line 7. The source of the MOS transistor 40 is connected to one terminal of the capacitor 41 and the drain of the MOS transistor 42. The gate of the MOS transistor 40 is connected to a terminal 50. The other terminal of the capacitor 41 is earthed. The source of the MOS transistor 42 is connected to the gate of the MOS transistor 56, and the gate of the MOS transistor 42 is connected to a terminal 49. The drain of the MOS transistor 56 is connected to a power supply, and the source of the MOS transistor 56 is connected to the drain of a row selection MOS transistor 55. The gate of the row selection MOS transistor 55 is connected to a terminal 58, and the source of the row selection MOS transistor 55 is connected to the second column signal line 8.
A current source 52 and the MOS transistor 54 form a source follower when the corresponding row selection MOS transistor 53 is conducting. The current source 52 and the MOS transistor 56 form a source follower when the corresponding 55 is conducting.
The first difference circuit unit 3 is connected to the second column signal line 8 to which the output from the first holding circuit units 2 is transmitted, and includes capacitor 60 having a capacitance value C1, capacitor 61 having a capacitance value C2, and a MOS transistor 62. One terminal of the capacitor 60 is connected to the second column signal line 8. The other terminal of the capacitor 60 is connected to the source of the MOS transistor 62 and the connection node (the point M in
The following describes operations of a solid-state imaging device according to the present embodiment, with reference to
It should be noted that in
The signal S22 becomes “HIGH” at a time point t1 in
The signal S25 becomes “HIGH” at a time point t2. The gate of the reset MOS transistor 17 in the pixel 1-2 is caused to “HIGH”, so that the reset MOS transistor 17 is conducting. Thus, the ED in the pixel 1-2 is connected to the power supply and is brought to a reset state. At the time point t2, the reset MOS transistor 12 in the pixel 1-1 and the reset MOS transistor 17 in the pixel 1-2 are both conducting, and the FD in the pixel 1-1 and the ED in the pixel 1-2 are both in the reset state.
At a time point t3, the signal S22 becomes “LOW”, the signal S24 becomes “HIGH”, and the signal S43 becomes “HIGH”. Thus the row selection MOS transistor 14 becomes conductive. Therefore, the voltage of the FD in the pixel 1-1 is transmitted to the first column signal line 7. Moreover, the gate of the MOS transistor 31 in the first holding circuit unit 2 becomes “HIGH”, and thus the MOS transistor 31 becomes conductive. Therefore, the voltage of the FD is transmitted to and held in the capacitor 32.
At a time point t4, the signal S25 becomes “LOW”, the signal S27 becomes “HIGH”, and the signal S47 becomes “HIGH”. Thus, the row selection MOS transistor 19 becomes conductive. Therefore, the voltage of the FD in the pixel 1-2 is transmitted to the first column signal line 7. Moreover, the gate of the MOS transistor 37 in the first holding circuit unit 2 becomes “HIGH”, and thus the MOS transistor 37 becomes conductive. Therefore, the voltage of the FD is transmitted to and held in the capacitor 38.
At a time point t5, all signals become “LOW”. At the time point t5, electrical signals in the reset state of the FD in the pixel 1-1 are held in the capacitor 32 in the first holding circuit unit 2, and the electrical signals in the reset state of the FD in the pixel 1-2 are held in the capacitor 38 in the first holding circuit unit 2.
At a time point t6, the signal S23 becomes “HIGH” The gate of the transfer MOS transistor 11 in the pixel 1-1 is caused to “HIGH”, so that the transfer MOS transistor 11 is conducting. Thus, signals obtained after the photodiode 10 received light is transferred to the ED.
At a time point t7, the signal S26 becomes “HIGH”. The gate of the transfer MOS transistor 16 in the pixel 1-2 is caused to “HIGH”, so that the transfer MOS transistor 16 is conducting. Thus, signals after the photodiode received light is transferred to the FD. At this time point, the transfer MOS transistor 11 in the pixel 1-1 and the transfer MOS transistor 16 in the pixel 1-2 are both conducting, and the FD in the pixel 1-1 and the FD in the pixel 1-2 are both in the light-received state.
At a time point t8 the signal S23 becomes “LOW”, the signal S24 becomes “HIGH”, and the signal S46 becomes “HIGH”. Thus, the row selection MOS transistor 14 becomes conductive. Therefore, the voltage of the FD in the pixel 1-1 is transmitted to the first column signal line 7. Moreover, the gate of the MOS transistor 34 in the first holding circuit unit 2 becomes “HIGH”, and thus the MOS transistor 34 becomes conductive. Therefore, the voltage of the FD is transmitted to and held in the capacitor 35.
At a time point t9 the signal S26 becomes “LOW” the signal S27 becomes “HIGH”, and the signal S50 becomes “HIGH”. Thus, the row selection MOS transistor 19 becomes conductive. Therefore, the voltage of the FD in the pixel 1-2 is transmitted to the first column signal line 7. Moreover, the gate of the MOS transistor 40 in the first holding circuit unit 2 becomes “HIGH”, and thus the MOS transistor 40 becomes conductive. Therefore, the voltage of the FD is transmitted to and held in the capacitor 41.
At a time point t10, all signals become “LOW”. At the time point t10, electrical signals in the light-received state of the FD in the pixel 1-1 are held in the capacitor 35 in the first holding circuit unit 2, and the electrical signals in the light-received state of the FD in the pixel 1-2 are held in the capacitor 41 in the first holding circuit unit 2.
At a time point t11, the signals S57, S44, and S63 become “HIGH”. Thus, the row selection MOS transistor 53 and the MOS transistor 33 in the first holding circuit unit 2 become conductive. Therefore, the voltage of the capacitor 32 is transmitted to the second column signal line 8. This voltage will be referred to as “Vrs1”. Moreover, when the MOS transistor 62 in the first difference circuit unit 3 is conducting, the Point M in
At a time point t12, the signals S57 and 545 become “HIGH”. Thus, the row selection MOS transistor 53 and the MOS transistor 36 in the first holding circuit unit 2 become conductive. Therefore, the voltage of the capacitor 35 is transmitted to the second column signal line 8. This voltage will be referred to as “Vsg1”. Since the MOS transistor 62 of the first difference circuit unit 3 is not conducting, a voltage change at the M point is defined by a voltage change in the second column signal line 8 and the capacitance ratio of the capacitor 60 to the capacitor 61. The voltage change in the second column signal line 8 is “Vrs1−Vsg1”, and the coefficient of capacitance is “C1/(C1+C2)”. Therefore, a voltage change at the Point M is “C1/(C1+C2)×(Vrs1−Vsg1)”.
At a time point t14, the signals S58, 548, and 563 become “HIGH”. Thus, the row selection MOS transistor 55 and the MOS transistor 39 in the first holding circuit unit 2 become conductive. Therefore, the voltage of the capacitor 38 is transmitted to the second column signal line 8. This voltage will be referred to as “Vrs2”. Moreover, when the MOS transistor 62 in the first difference circuit unit 3 is conducting, the Point M in
At a time point t15, the signals S58 and S49 become “HIGH”. Thus, the row selection MOS transistor 55 and the MOS transistor 42 in the first holding circuit unit 2 become conductive. Therefore, the voltage of the capacitor 41 is transmitted to the second column signal line 8. This voltage will be referred to as “Vsg2”. Since the MOS transistor 62 of the first difference circuit unit 3 is not conducting, a voltage change at the M point is defined by a voltage change in the second column signal line 8 and the capacitance ratio of the capacitor 60 to the capacitor 61. The voltage change in the second column signal line 8 is “Vrs2−Vsg2”, and the coefficient of capacitance is “C1/(C1+C2)”. Therefore, a voltage change at the Point. M is “C1/(C1+C2)×(Vrs2−Vsg2)”.
As described as above, in normal operations, differential signals between the electrical signals in the reset state of pixels and the electrical signals in the light-received state of the pixels are outputted to the output line 4 on a row basis.
The following describes the pixel combining operations of a solid-state imaging device according to the present embodiment.
It should be noted that in
The operations in
At the time point t11, the signals S57, S44, S58, S48, and S63 become “HIGH”. Thus, the row selection MOS transistors 53 and 55 and the MOS transistors 33 and 39 in the first holding circuit unit 2 become conductive. Therefore, the combined voltage of the capacitors 32 and 38 is transmitted to the second column signal line 8. The combined voltage will be referred to as “Vrs1+2”. Moreover, when the MOS transistor 62 in the first difference circuit unit 3 is conducting, the Point M in
At the time point t12, the signals S57, S45, S58, and S49 become “HIGH”. Thus, the row selection MOS transistors 53 and 55 and the MOS transistors 36 and 42 in the first holding circuit unit 2 become conductive. Therefore, the combined voltage of the capacitors 35 and 41 is transmitted to the second column signal line 8. The combined voltage will be referred to as “Vsg1+2”. Since the MOS transistor 62 of the first difference circuit unit 3 is not conducting, a voltage change at the M point is defined by a voltage change in the second column signal line 8 and the capacitance ratio of the capacitor 60 to the capacitor 61. The voltage change in the second column signal line 8 is “Vrs1+2−Vsg1+2”, the coefficient of capacitance is “C1/(C1+C2)”. Therefore, the voltage change at the Point M is “C1/(C1+C2)×Vrs1+2−Vsg1+2”.
In
As mentioned above, according to the solid-state imaging device of the present embodiment, the first holding circuit units 2 each include pixel-wise holding circuits each correspond to one of the pixels. This allows the first holding circuit units 2 to simultaneously and independently hold signals from the pixels in the pixel circuit unit 1. Therefore, the pixel circuit unit 1 can, at a high speed, transmit electrical signals in the reset state and in the light-received state to the first holding circuit units 2. As a result, differences in light exposure time between pixels are reduced, as compared to when the function of a conventional focal-plane shutter is used. Therefore, video distortion can be reduced.
Moreover, according to a solid-state imaging device of the present embodiment, pixels are combined when electrical signals are transmitted from the first holding circuit unit 2 to the output line 4. Therefore, the amount of data outputted from the output line 4 decreases. This achieves high-speed signal processing.
Moreover, according to a solid-state imaging device of the present embodiment, electrical signals in the first holding circuit unit 2 are simultaneously outputted to the first difference circuit unit 3. Therefore, noise can be averaged and reduced.
As an output form, the first holding circuit unit 2 in
MOS transistors 69 and 70 form a current mirror circuit. The drain of the MOS transistor 69 is connected to a power source. The source of the MOS transistor 69 is connected to the sources of the row selection MOS transistors 53 and 55 and the gate of the MOS transistor 69 itself. The drain of the MOS transistor 70 is connected to the power supply. The gate of the MOS transistor 70 is connected to the gate of the MOS transistors 69. The source of the MOS transistor 70 is connected to the drain of a MOS transistor 71. The gate of the MOS transistor 71 is connected to the drain of the MOS transistor 71, and the source of the MOS transistor 71 is connected to the drain of the MOS transistor 72. The gate of the MOS transistor 71 is connected to the second column signal line 8. The sources of the MOS transistors 54 and 56 are interconnected, and are connected to the drain of the MOS transistor 72. The source of the MOS transistor 72 is earthed, and the gate of the MOS transistor 72 is connected to a terminal 73. A bias voltage is applied to a terminal 73.
The operations of the first holding circuit unit 2 in
As mentioned above, a solid-state imaging device of the present modification can achieve high-speed signal processing while reducing video distortion. Moreover, noise can be reduced.
The second embodiment of the present invention will be described.
Signals S25, S26, S27, S47, and S50 in
According to the operations in
In the readout from the time points t11 to t13, two rows of the pixel-wise holding circuits 2-1 and 2-2 are selected at the same time and combined, and signals held by the holding circuits 2-1 and 2-2 are readout. When two signals from different pixels but in the same state are combined and readout in such a way, random noise decreases to (1/√2).
As mentioned above, a solid-state imaging device of the present embodiment can achieve high-speed signal processing while reducing video distortion. Moreover, noise can be reduced.
The third embodiment of the present invention will be described.
The solid-state imaging device in
Electrical signals in a reset state and electrical signals a light-received state that are held in the first holding circuit units 2 are applied to the first difference circuit units 3, and differential signals outputted from the first difference circuit units 3 are held by the second holding circuit units 75. The differential signal is readout to the output line 4 by applying a reference signal and a holding signal of the second holding circuit unit 75 to the second difference circuit unit 76.
The second holding circuit unit 75 holds output from the first difference circuit unit 3. The second difference circuit unit 76 outputs a difference between the output from the second holding circuit unit 75 and a reference signal. The second holding circuit unit 75 includes several pixel-wise holding circuits that can hold a differential signal between an electrical signal in the reset state of a pixel and an electrical signal in the light-received state of the pixel. The row selection circuit 6 successively selects pixel-wise holding circuits in the second holding circuit unit 75, and causes the second holding circuit unit 76 to output the differential signals held by the selected pixel-wise holding circuits.
The pixel-wise holding circuit 3-1 includes MOS transistors 81, 83, and 101, and a capacitor 82.
The drain of the MOS transistor 81 is connected to the third column signal line 77. The source of the MOS transistor 81 is connected to one terminal of the capacitor 82 and the drain of the MOS transistor 83. The gate of the MOS transistor 81 is connected to a terminal 92. The other terminal of the capacitor 82 is earthed. The source of the MOS transistor 83 is connected to the gate of the MOS transistor 87, and the gate of the MOS transistor 83 is connected to a terminal 93. The drain of the MOS transistor 101 is connected to a reference voltage line 103. The gate of the MOS transistor 101 is connected to a terminal 99. The source of the MOS transistor 101 is connected to the gate of the MOS transistor 87. The drain of the MOS transistor 87 is connected to a power supply, and the source of the MOS transistor 87 is connected to the drain of a row selection MOS transistor 89. The gate of the row selection MOS transistor 89 is connected to a terminal 94, and the source of the row selection MOS transistor 89 is connected to the fourth column signal line 78.
The pixel-wise holding circuit 3-2 includes MOS transistors 84, 86, and 102, and a capacitor 85.
The drain of the MOS transistor 84 is connected to the third column signal line 77. The source of the MOS transistor 84 is connected to one terminal of the capacitor 85 and the drain of the MOS transistor 86. The gate of the MOS transistor 84 is connected to a terminal 95. The other terminal of the capacitor 85 is earthed. The source of the MOS transistor 86 is connected to the gate of the MOS transistor 88, and the gate of the MOS transistor 86 is connected to a terminal 96. The drain of the MOS transistor 102 is connected to the reference voltage line 103. The gate of the MOS transistor 102 is connected to a terminal 100. The source of the MOS transistor 102 is connected to the gate of the MOS transistor 88. The drain of the MOS transistor 88 is connected to a power supply, and the source of the MOS transistor 88 is connected to the drain of a row selection MOS transistor 90. The gate of the row selection MOS transistor 90 is connected to a terminal 97, and the source of the row selection. MOS transistor 90 is connected to the fourth column signal line 78.
A current source 91 and the MOS transistor 87 form a source follower when the corresponding row selection MOS transistor 89 is conducting. The current source 91 and the MOS transistor 88 form a source follower when the corresponding row selection MOS transistor 90 is conducting. The reference voltage line 103 is connected to a terminal 98.
The second difference circuit unit 76 is connected to the fourth column signal line 78 to which output from the second holding circuit unit 75 is transmitted, and includes a capacitor 110 having a capacitance value C11, a capacitor 111 having a capacitance value C12, and a MOS transistor 112. One terminal of the capacitor 110 is connected to the fourth column signal line 78, and the other terminal is connected to the source of the MOS transistor 112 and a connection node of one terminal of the capacitor 111 (a point N in
The following describes the operations of a solid-state imaging device according to the present embodiment, with reference to
It should be noted that in
In
At a time point t11, the signals S57, S44, and S63 become “HIGH”. Thus, the row selection MOS transistor 53 and the MOS transistor 33 in the first holding circuit unit 2 become conductive. Therefore, the voltage of the capacitor 32 is transmitted to the second column signal line 8. This voltage will be referred to as “Vrs1”. Moreover, when the MOS transistor 62 in the first difference circuit unit 3 is conducting, the Point M in
At a time point t12, the signals S57, 545, and 592 become “HIGH”. Thus, the row selection MOS transistor 53 and the MOS transistor 36 in the first holding circuit unit 2 and a MOS transistor 81 in the second holding circuit unit 75 become conductive. Therefore, the voltage of the capacitor 35 is transmitted to the second column signal line 8. This voltage will be referred to as “Vsg1”. Since the MOS transistor 62 in the first difference circuit unit 3 is not conducting, a voltage change at the M point is defined by a voltage change in the second column signal line 8 and the capacitance ratio of the capacitor 60 to the capacitor 61. The voltage change in the second column signal line 8 is “Vrs1−Vsg1”, and the coefficient of capacitance is “C1/(C1+C2)”. Therefore, a voltage change at the Point M is “C1/(C1+C2)×(Vrs1−Vsg1)”. This voltage is transmitted through the MOS transistor 81 and stored in the capacitor 82.
At a time point t14, the signals S58, S48, and S63 become “HIGH”. Thus, the row selection MOS transistor 55 and the MOS transistor 39 in the first holding circuit unit 2 become conductive. Therefore, the voltage of the capacitor 38 is transmitted to the second column signal line 8. This voltage will be referred to as “Vrs2”. Moreover, when the MOS transistor 62 in the first difference circuit unit 3 is conducting, the Point M in
At a time point t15, the signals S58, S49, and S95 become “HIGH”. Thus, the row selection MOS transistor 55 and the MOS transistor 42 in the first holding circuit unit 2 and a MOS transistor 84 in the second holding circuit unit 75 become conductive. Therefore, the voltage of the capacitor 41 is transmitted to the second column signal line 8. This voltage will be referred to as “Vsg1”. Since the MOS transistor 62 of the first difference circuit unit 3 is not conducting, a voltage change at the M point is defined by a voltage change in the second column signal line 8 and the capacitance ratio of the capacitor 60 to the capacitor 61. The voltage change in the second column signal line 8 is “Vrs2−Vsg2”, and the coefficient of capacitance is “C1/(C1+C2)”. Therefore, a voltage change at the Point M is “C1/(C1+C2)×(Vrs2−Vsg2)”. This voltage is transmitted through the MOS transistor 84 and stored in the capacitor 85.
Thus, by a time point t16, differential signals “C0×(Vrs1−Vsg1)” and “C0×(Vrs2−Vsg2)” are stored in the capacitor 82 and the capacitor 85 in the second holding circuit unit 75, respectively. It should be noted that C0=C1/(C1+C2).
At a time point t17, the signals S99, S94, S100, S97, and S113 become “HIGH”. Thus, the MOS transistor 101, the row selection MOS transistor 89, the MOS transistor 102, and the row selection MOS transistor 90 in the second holding circuit unit 75 and the MOS transistor 112 in the second difference circuit unit 76 become conductive. The voltage of the reference voltage line 103 (e.g., VrefS) is transmitted to the fourth column signal line 78 through the MOS transistor 101 and the row selection MOS transistor 89 and through the MOS transistor 102 and the row selection MOS transistor 90. When both the threshold voltage of the MOS transistor 87 and the threshold voltage of the MOS transistor 88 are “Vt”, this voltage is “VrefS−Vt”. In the second difference circuit unit 76, when the MOS transistor 112 becomes conductive, the point N in
At a time point t18, the signals S94 and S93 become “HIGH”. Thus, the row selection MOS transistor 89 and the MOS transistor 83 become conductive. Therefore, the voltage “C0×(Vrs1−Vsg1)” held in the capacitor 82 is transmitted to the fourth column signal line 78. The voltage value “C0×(Vrs1−Vsg1)−Vt” is generated in fourth column signal line 78. Since the MOS transistor 112 in the second difference circuit unit 76 is not conducting, a voltage change at the N point is defined by a voltage change in the fourth column signal line 78 and the capacitance ratio of the capacitor 110 to the capacitor 111. The voltage change in the fourth column signal line 78 is “VrefS−C0×(Vrs1−Vsg1)”, and the coefficient of capacitance is “C11/(C11+C12)”. Therefore, the voltage change at the point N is “Vrf1-C00×(VrefS−C0×(Vrs1−Vsg1))”. It should be noted that C00=C11/(C11+C12).
At a time point t19, the signals S97 and S96 become “HIGH”. Thus, the row selection MOS transistor 90 and the MOS transistor 86 become conductive. Therefore, the voltage “C0×(Vrs2−Vsg2)” (referred to as V22) held in the capacitor 85 is transmitted to the fourth column signal line 78. The voltage value “C0×(Vrs2−Vsg2)−Vt” is generated in fourth column signal line 78.
Since the MOS transistor 112 of the second difference circuit unit 76 is not conducting, a voltage change at the N point is defined by a voltage change in the fourth column signal line 78 and the capacitance ratio of the capacitor 110 to the capacitor 111. The voltage change in the fourth column signal line 78 is “Vrf1-C00×(VrefS−C0×(Vrs1−Vsg1)−C00×(C0×(Vrs2−Vsg2)−Vt)”, and the coefficient of capacitance is “C00”. Therefore, the voltage change at the point N is “C00×((Vrf1−C00×(VrefS−C0×(Vrs1−Vsg1)−C00×(C0×(Vrs2−Vsg2)−Vt))”. Thus, the second holding circuit unit 75 holds differential signals between electrical signals in the reset state and electrical signals in the light received state in the pixel circuit unit 1. Therefore, signals of two rows can be combined at the second difference circuit unit 76. Thus, it is possible to combine pixel signals more accurately.
The second difference circuit unit 76 is connected to the fourth column signal line 78 to which output from the second holding circuit unit 75 is transmitted, and includes the capacitor 110 having the capacitance value C11, the capacitor 111 having the capacitance value C12, and the MOS transistor 112. One terminal of the capacitor 110 is connected to the fourth column signal line 78, and the other terminal is connected to the source of a MOS transistor 121 and the connection node of one terminal of the capacitor 111 (the point N in
Moreover, the second difference circuit unit 76 includes the MOS transistors 121, 122, and 124 and a buffer 123. The drain of the MOS transistor 121 is connected to the sources of MOS transistors 112 and 124. The source of the MOS transistor 121 is connected to the point N. The gate of the MOS transistor 121 is connected to a terminal 125. The drain of the MOS transistor 122 is connected to the point N. The source of the MOS transistor 122 is connected to input of the buffer 123. The gate of the MOS transistor 122 is connected to a terminal 127. The drain of the MOS transistor 124 is connected to the output of the buffer 123. The gate of the MOS transistor 124 is connected to a terminal 126.
The following describes the operations of a solid-state imaging device according to the present embodiment, with reference to
It should be noted that in
In
At the time point t17, the signals S99, 594, 5113, and 5125 become “HIGH”. Thus, the MOS transistor 101 and the row selection MOS transistor 89 in the second holding circuit unit 75 and the MOS transistors 112 and 121 in the second difference circuit unit 76 become conductive. The voltage (VrefS) of the reference voltage line 103 is transmitted to the fourth column signal line 78 through the MOS transistor 101 and the row selection MOS transistor 89. When the threshold value of the MOS transistors 87 is “Vt87”, this voltage is “VrefS−Vt87”. In the second difference circuit unit 76, when the MOS transistors 112 and 121 become conductive, the point N in
At the time point t18, the signals S94, S93 and S127 become “HIGH”. Thus, the row selection MOS transistor 89 and the MOS transistor 83 become conductive. Therefore, the voltage “C0×(Vrs1−Vsg1)” held in the capacitor 82 is transmitted to the fourth column signal line 78. The voltage “C0×(Vrs1−Vsg1)−Vt87” is transmitted to the fourth column signal line 78. Since the MOS transistor 112 of the second difference circuit unit 76 is not conducting, a voltage change at the N point is defined by a voltage change in the fourth column signal line 78 and the capacitance ratio of the capacitor 110 to the capacitor 111. The voltage change in the fourth column signal line 78 is “VrefS−C0×(Vrs1−Vsg1)”, and the coefficient of capacitance is “C11/(C11+C12)” (referred to as C00). Therefore, the voltage change at the point N is “Vref1−C00×(VrefS−C0×(Vrs1−Vsg1))”. After transmitting through the MOS transistor 122, this voltage is stored in stray capacitance (the capacitance 200 shown in a parenthesis in
At the time point t19, the signals S100, S97, S125, and S126 become “HIGH”. Thus, the row selection MOS transistor 90 and the MOS transistor 102 become conductive. Therefore, the voltage (VrefS) of the reference voltage line 103 is transmitted to the forth column signal line 78 through the MOS transistor 102 and the row selection MOS transistor 90. When the threshold value of the MOS transistors 88 is “Vt88”, this voltage is “VrefS−Vt88”. In the second difference circuit unit 76, the MOS transistor 112 is not conducting while the MOS transistor 124 is conducting. Therefore, the voltage change at the point N is set to the output of the buffer 123 “Vref1−C00×(VrefS−C0×(Vrs1−Vsg1))”. At this point, the voltage on the side of the fourth column signal line 78 of the capacitor 110 is “VrefS−Vt88”.
At a time point t20, the signals S97 and 596 become “HIGH”. Thus, the row selection MOS transistor 90 and the MOS transistor 86 become conductive. Therefore, the voltage “C0×(Vrs2−Vsg2)” held in the capacitor 85 is transmitted to the fourth column signal line 78. When the threshold value of the MOS transistor 88 is Vt88, the voltage “C0×(Vrs2−Vsg2)−Vt88” is transmitted to the fourth column signal line 78. Since the MOS transistor 112 of the second difference circuit unit 76 is not conducting, a voltage change at the N point is defined by a voltage change in the fourth column signal line 78 and the capacitance ratio of the capacitor 110 to the capacitor 111. The voltage change in the fourth column signal line 78 is “VrefS−C0×(Vrs2−Vsg2)”, and the coefficient of capacitance is “C11/(C11+C12)” (referred to as COO). Therefore, the voltage change at the point N is “Vref1−C00×(VrefS−C0×(Vrs1−Vsg1))−C00×(VrefS−C0×(Vrs2−Vsg2))”. Thus, “Vref1−C00×(2VrefS−C0×(Vrs1+Vrs2−Vsg1−Vsg2))” is obtained.
Thus, the second holding circuit unit 75 holds differential signals between electrical signals in the reset state and electrical signals in the light received state in the pixel circuit unit 1. Therefore, signals of two rows can be combined at the second difference circuit unit 76. Thus, it is possible to combine pixel signals more accurately.
The buffer 123 includes MOS transistors 131, 132, 133, 134, and 135. The drain of the MOS transistor 131 is connected to a power supply. The gate of the MOS transistor 131 is connected to the source of the MOS transistor 131 and the drain of the MOS transistor 133. The drain of the MOS transistor 132 is connected to the power supply. The gate of the MOS transistor 132 is connected to the gate of the MOS transistor 131. The source of the MOS transistor 132 is connected to the drain of the MOS transistor 134. The sources of the MOS transistor 133 and the MOS transistor 134 are interconnected. A gate 137 of the MOS transistor 133 is connected to input. The gate of the MOS transistor 134 is connected to the drain of the MOS transistor 134 itself and servers as output. The drain of the MOS transistor 135 is connected to the sources of the MOS transistors 133 and 134. The source of the MOS transistor 135 is earthed. A bias voltage is applied to a gate 136.
The pixel-wise holding circuit 3-1 includes the MOS transistors 81, 87, and 101. The drain of the MOS transistor 81 is connected to the third column signal line 77. The source of the MOS transistor 81 is connected to the gate of the MOS transistor 87. The gate of the MOS transistor 81 is connected to the terminal 92. The drain of the MOS transistor 101 is connected to a reference voltage line 103. The gate of the MOS transistor 101 is connected to a terminal 99. The source of the MOS transistor 101 is connected to the gate of the MOS transistor 87. The drain of the MOS transistor 87 is connected to a power supply. The source of the MOS transistor 87 is connected to the drain of a row selection MOS transistor 89. The gate of the row selection MOS transistor 89 is connected to a terminal 94. The source of the row selection MOS transistor 89 is connected to the fourth column signal line 78.
The pixel-wise holding circuit 3-2 includes the MOS transistors 84, 88, and 102. The drain of the MOS transistor 84 is connected to the third column signal line 77. The source of the MOS transistor 84 is connected to the gate of the MOS transistor 88. The gate of the MOS transistor 84 is connected to the terminal 95. The drain of the MOS transistor 102 is connected to the reference voltage line 103. The gate of the MOS transistor 102 is connected to a terminal 100. The source of the MOS transistor 102 is connected to the gate of the MOS transistor 88. The drain of the MOS transistor 88 is connected to a power supply. The source of the MOS transistor 88 is connected to the drain of a row selection MOS transistor 90. The gate of the row selection MOS transistor 90 is connected to a terminal 97. The source of the row selection MOS transistor 90 is connected to the fourth column signal line 78. A current source 91 and the MOS transistor 87 form a source follower when the corresponding row selection MOS transistor 89 is conducting. The current source 91 and the MOS transistor 88 form a source follower when the corresponding row selection MOS transistor 90 is conducting. The reference voltage line 103 is connected to the terminal 98.
The following describes the operations of a solid-state imaging device according to the present embodiment, with reference to
It should be noted that in
In
At the time point t11, the signals S57, 544, and S63 become “HIGH”. Thus, the row selection MOS transistor 53 and the MOS transistor 33 in the first holding circuit unit 2 become conductive. Therefore, the voltage of the capacitor 32 is transmitted to the second column signal line 8. This voltage will be referred to as “Vrs1”. Moreover, when the MOS transistor 62 in the first difference circuit unit 3 is conducting, the Point M in
At the time point t12, the signals S57, S45, and S92 become “HIGH”. Thus, the row selection MOS transistor 53 and the MOS transistor 36 in the first holding circuit unit 2 and the MOS transistor 81 in the second holding circuit unit 75 become conductive. Therefore, the voltage of the capacitor 35 is transmitted to the second column signal line 8. This voltage will be referred to as “Vsg1”. Since the MOS transistor 62 in the first difference circuit unit 3 is not conducting, a voltage change at the M point is defined by a voltage change in the second column signal line 8 and the capacitance ratio of the capacitor 60 to the capacitor 61. The voltage change in the second column signal line 8 is “Vrs1−Vsg1”, and the coefficient of capacitance is “C1/(C1+C2)”. Therefore, the voltage change at the Point M is “C1/(C1+C2)×(Vrs1−Vsg1)”. This voltage is transmitted through the MOS transistor 81 and stored in the gate of the MOS transistor 87.
At the time point t14, the signals S58, 548, and S63 become “HIGH”. Thus, the row selection MOS transistor 55 and the MOS transistor 39 in the first holding circuit unit 2 become conductive. Therefore, the voltage of the capacitor 38 is transmitted to the second column signal line 8. This voltage will be referred to as “Vrs2”. Moreover, when the MOS transistor 62 in the first difference circuit unit 3 is conducting, the Point M in
At the time point t15, the signals S58, 549, and S95 become “HIGH”. Thus, the row selection MOS transistor 55 and the MOS transistor 42 in the first holding circuit unit 2 and the MOS transistor 84 in the second holding circuit unit 75 become conductive. Therefore, the voltage of the capacitor 41 is transmitted to the second column signal line 8. This voltage will be referred to as “Vsg2”. Since the MOS transistor 62 of the first difference circuit unit 3 is not conducting, a voltage change at the M point is defined by a voltage change in the second column signal line 8 and the capacitance ratio of the capacitor 60 to the capacitor 61. The voltage change in the second column signal line 8 is “Vrs2−Vsg2”, and the coefficient of capacitance is “C1/(C1+C2)”. Therefore, the voltage change at the point M is “C1/(C2+C2)×(Vrs2−Vsg2)”. This voltage is transmitted through the MOS transistor 84 and stored in the gate of the MOS transistor 88. In other words, by the time point t16, the differential signals “C0×(Vrs1−Vsg1)” and “C0×(Vrs2−Vsg2)” are stored in the gate of the MOS transistor 87 and the gate of the MOS transistor 88 in the second holding circuit unit 75, respectively. It should be noted that C0=C1/(C1+C2).
At the time point t17, the signals S94, S97, and S113 become “HIGH”. Thus, the row selection MOS transistors 89 and 90 in the second holding circuit unit 75 and the MOS transistor 112 in the second difference circuit unit 76 become conductive. The differential signal “C0×(Vrs1−Vsg1)−Vt (Vt is the threshold value of the MOS transistor 87)” held in the gate of the MOS transistor 87 is transmitted to the fourth column signal line 78 through the row selection MOS transistor 89. The differential signal “C0×(Vrs2−Vsg2−Vt (Vt is the threshold value of the MOS transistor 88)” held in the gate of the MOS transistor 88 is transmitted to the fourth column signal line 78 through the row selection MOS transistor 90. When two rows of pixel-wise holding circuits (two pixel-wise holding circuits) are selected at the same time, signals are combined as described in the first embodiment. The combined signal value generated in the fourth column signal line 78 is “VC”. In the second difference circuit unit 76, when the MOS transistor 112 becomes conductive, the point N in
At the time point t18, the signals S99, S94, S100, and S97 become “HIGH”. Thus, the MOS transistors 101 and 102 and the row selection MOS transistors 89 and 90 become conductive. Therefore, the voltage (Vref) of the reference voltage line 103 is transmitted to the fourth column signal line 78 through the MOS transistors 101 and 87 and the row selection MOS transistor 89 and through the MOS transistors 102 and 88 and the row selection MOS transistor 90. This voltage value is Vref−Vt. After that, as mentioned above, the difference between these two signals is derived at the second difference circuit unit 76 (an explanation for difference deriving operations is omitted here).
As mentioned above, when signals are held by the gate of a MOS transistor instead of employing a holding circuit using a capacitor, similar operations are possible.
As mentioned above, a solid-state imaging device of the present embodiment can achieve high-speed signal processing while reducing video distortion. Moreover, noise can be reduced.
The fourth embodiment of the present invention will be described.
The camera in
In this camera, light is incident from the outside through the lens 410, the incident light is converted into an output signal by the solid-state imaging device 400, and the output signal is outputted from an output line 4 and an output I/F428. The outputted output signal is processed by the DSP 420. As a video signal, the processed signal is outputted to and stored in the image memory 440, and is outputted to and displayed at the image display device 430.
The DSP 420 includes an image processing circuit 421 and a camera system control unit 422. The image processing circuit 421 performs processing such as noise reduction for output signals of the solid-state imaging device 400 to generate video signals. The camera system control unit 422 controls scan timing and gain for pixels in the solid-state imaging device 400. The DSP 420, for example, compensates a characteristic difference between pixels shared in pixels in the solid-state imaging device 400.
A communication/timing controller (timing generator) 450 (1) receives master clock CLK0 and data DATA that are inputted through an external terminal, (2) generates various internal clocks, and (3) controls the column selection circuits 5, the row selection circuit 6, the first difference circuit units 3, and the output I/F428.
It should be noted that in the present embodiment, an analog/digital signal processor (AD converter) may be provided between the first holding circuit units 2 and the output I/F428.
Although a solid-state imaging device and a camera according to the present invention are described above based on the embodiments, the present invention is not limited to these embodiments. The present invention includes various modifications which a person skilled in the art would conceive without materially departing from the novel teachings and advantages of the present invention. Moreover, structural elements in embodiments may be optionally combined within the scope of the present invention.
For example, in the above embodiments, electrical signals read from the pixels are held by capacitors in the first holding circuit units 2. However, as shown in
In this case, various operations can be performed. The following describes (1) a mechanical shutter mode combined with the above mentioned mode (hereinafter referred to as a combination mode using a mechanical shutter), (2) a memory through mode, and (3) a several-frame holding mode.
(1) The combination mode using a mechanical shutter will be described below.
In operations shown in
From time points t100 to t103, the signal S22 for resetting the pixel 1-1 is “HIGH”. During time points t102 and t103, the reset signal from the pixel 1-1 is transmitted through the row selection MOS transistor 14 and the MOS transistor 31 and held by the gate of the holding transistor 332. From time points t101 to t106, the signal S25 for resetting the pixel 1-2 is “HIGH”. During time points t104 and t106, the reset signal from the pixel 1-2 is transmitted through the row selection MOS transistor 19 and the MOS transistor 37 and held by the gate of the holding transistor 338. Moreover, from time points t105 to t110, the signal S23 for transferring electric charges in the pixel 1-1 to FD is “HIGH”. During time points t109 and t100, the signal of FD in the pixel 1-1 is transmitted through the row selection MOS transistor 14 and the MOS transistor 36 and held by the gate of the holding transistor 335. From time points t108 to t112, the signal S26 for transferring electric charges in the pixel 1-2 to FD is “HIGH”. During time points t111 and t112, the signal in FD in the pixel 1-2 is transmitted through the row selection MOS transistor 19 and the MOS transistor 40 and held by the gate of the holding transistor 341. When, between the pixels of different rows, signals for resetting each pixel have a partially overlapped duration and signals for transferring electric charges to the FD of each pixel have a partially overlapped duration, pixel signals can be transferred to the first holding circuit unit 2 at a high speed.
For example, when 4000 rows of pixels are selected, and one row of reset signals and signals of FD are transferred per microsecond, it takes four milliseconds to transfer pixel signals of all rows to the first holding circuit units 2.
In the case of a camera, pixel signals are transferred to the first holding circuit units 2 in four milliseconds from the moment a mechanical shutter closes. If a mode is changed to “a memory through mode” while the first holding circuit units 2 are holding pixel signals of one frame (e.g., all pixels), a monitor image (e.g., reduced image obtained by thinned-out or combination) can be obtained four milliseconds after the mechanical shutter closes. For example, when the mechanical shutter is a rear curtain shutter; this can be achieved by controls such as synchronization of the start of exposure to light by an electronic shutter and the end of exposure to light by the rear curtain shutter.
In other words, generally, a monitor image can be obtained only after one frame is processed, after shutter operation is finished by the rear curtain, i.e., after the rear curtain closes. On the other hand, in the combination mode using a mechanical shutter; a monitor image can be obtained at a high speed. Therefore, real time of the monitor image can be improved.
The following describes (2) the memory through mode. In the configuration of
For such a “memory through mode”, the configuration in
The following describes (3) the several-frame holding mode. In the above embodiments, the first holding circuit unit 2 has pixel-wise holding circuits of the number same as the pixels of one column of the pixel circuit unit 1. However, it is possible to provide pixel-wise holding circuits, the number of which is greater than the number of pixels of one column.
For instance, when the number of pixel-wise holding circuits is increased to twice the number of pixels of one column, pixel signal information of two frames can be held by the first holding circuit unit 2. Therefore, for example, one frame of pixel signal information in a dark condition and one frame of pixel signal information in a bright condition are caused to be held by the first holding circuit unit 2 in order to obtain the difference between the pixel signal information in the dark condition and the pixel signal information in the bright condition. Shading of the pixel circuit unit 1 can be corrected. Providing pixel-wise holding circuits, the number of which is greater than the number of pixels of one column can correct or process pixel signal information.
Moreover, even when pixel-wise holding circuits of the number same as the pixels in the pixel circuit unit 1 are provided, it is possible to cause the first holding circuit units 2 to hold several frames of fewer number of pixels by decimating pixels. For example, by horizontally and vertically decimating one pixel of two adjacent pixels, four frames of pixels, the number of which is ¼ the number of original pixels can be held in the first holding circuit units 2. For example, by horizontally and vertically decimating one of three adjacent pixels, nine frames of pixels, the number of which is 1/9 the number of original pixels can be held by the first holding circuit units 2. For example, if temporally consecutive frames having different exposure durations are held by the first holding circuit unit 2, and several frames are incorporated into one frame by an external device of the solid-stating imaging device, an image with improved dynamic range can be obtained.
It should be noted that a solid-state imaging device may perform operations by combining the operation modes (1) to (3). This facilitates high-speed operations because the solid-state imaging device can, using internal operation modes, perform operations which were conventionally performed only outside the device.
Although only some exemplary embodiments of the present invention have been described in detail above, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of the present invention. Accordingly, all such modifications are intended to be included within the scope of the present invention.
The present invention is useful for solid-state imaging devices, and is particularly useful for, for example, digital still cameras having a video capturing function.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2010-178960 | Aug 2010 | JP | national |
This is a continuation application of PCT International Application No. PCT/JP2011/000646 filed on Feb. 4, 2011, designating the United States of America, which is based on and claims priority of Japanese Patent Application No. 2010-178960 filed on Aug. 9, 2010. The entire disclosures of the above-identified applications, including the specifications, drawings and claims are incorporated herein by reference in their entirety.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2011/000646 | Feb 2011 | US |
| Child | 13759558 | US |
