Patent Application
20080116935
Embodiments of the invention relate to electronic circuitry commonly employed to transmit data and clock in the form of binary signals over lengths of interconnect to other electronic circuits, devices and systems. Such circuitry falls under the category of Data Communication Circuits.
Low Voltage Differential Signaling (LVDS) is ubiquitous in the art. The popularity of this signaling technique arose in part from the expectation of substantially reduced power consumption because of the low (˜350 mV) swing on the lines as well as the differential nature of the signals that enabled accurate recognition despite static or dynamic variations in ground or supply voltages between the transmitting and receiving systems. Low signal swing also permits faster signal transitions, enabling higher rates of data transmission. Additionally, the differential and low-swing nature of signals also minimizes electromagnetic interference (EMI) and emissions from the signaling interconnect. Hence LVDS became the signaling method of choice for point-to-point links such as high-speed links between peripheral components of a computing system (USB), networking interconnect infrastructure installed in buildings (Ethernet) etc.
Another low-swing signaling link promoted by an industry working group (Digital Display Working Group) is the Digital Video Interface specification [DVI, reference 1]. This specification details a method for data communication between a digital video content device and a digital video display device; the specification is supported by a number of companies in the industry with compliant components. DVI 1.0 specifies the use of Transition Minimized Differential Signaling (TMDS) intended to reduce electro-magnetic emissions from the data link by reducing the number of binary transitions. The voltage swing is also minimized to approximately 500 mV on each wire of the differential pair. A typical TMDS driver is shown in
TMDS uses low-swing signals, but is not necessarily low-power since the terminating voltage employed, as defined in DVI 1.0, is 3.3V. In order to produce a 500 mV swing across a 50 Ohm terminating resistor at the far end of the link, the minimum current required is 10 mA. TMDS is not truly differential in action, since current flow is only activated on one wire of the differential wire pair at any time. For example, with reference to
Prior art TMDS CMOS drivers as illustrated in
The invention improves upon prior art substantially through a novel source-coupled differential low-swing (SCDL) driver circuit. Output signals are connected to the source terminals of driving switches in the invention circuit, minimizing the detrimental impact of miller coupling capacitance between gate nodes and driven output nodes upon output slew-rate, enabling higher frequencies of operation. Output signal undershoots and overshoots are also mitigated by the invention driver circuit due in part to the in-phase relationship of the gate node to the driven output node of a driver switch. A cascoded current source additionally ensures very high output impedance and mitigates current modulation. Due in part to the controlled output slew, the SCDL driver lends itself to transmitter emphasis, extending the reach of DVI links.
A prior art embodiment of a TMDS differential signaling output driver and termination architecture is illustrated in
An issue with the prior art driver is that the switch devices in the driver circuit are relatively large, and possess significant parasitic capacitances that impact output signal integrity. With reference to
Such electrical phenomena lead to lower link performance in two distinct ways. One, the slower slew rate limits the maximum data transmission frequency of the link, and second, overshoots and undershoots impact signal integrity, and the integrity of the data ‘eye’, or distinctly differential data bit duration in the differential signal received, increasing bit error rates at high frequencies and over longer lengths of interconnect.
The miller coupling capacitances across switches P1 and P2 in the invention embodiment assist in output signal development, since PFET devices require a negative voltage swing at their input in order to turn ON, and the output signal desired from the driver is also a negative voltage swing down from the far-end reference voltage AVCC. Similarly, a PFET switch is turned ‘off’ by the input to its gate node going high, while the output wire connecting to the switch also transitions high towards the reference voltage AVCC. This ‘in-phase’ relationship between control and output signals ensures that the energy developed by pre-driver circuits driving signal inputs 5 and 6 is conveyed through the miller capacitances to assist in the output development, thereby improving the driver's overall energy efficiency per transition. Since there is no transient reverse swing of the output signal in a symbol transition, the rate of development of the output differential is improved significantly, improving the slew rate of the outputs. Alternately, instead of improved slew rates, the PFET switch devices may be reduced in their drive strength, with a corresponding benefit in reduced power consumption in the charge and discharge of capacitance associated with these devices. Additionally, since the miller coupling effect is in phase with output signal development, the output signal develops monotonically, eliminating overshoots or undershoots and thereby improving the differential data ‘eye’.
Another advantage of the invention circuit architecture is its self-limiting action with respect to the maximum voltage swing at the output. Since PFET switches are used, and the current source employs a cascode device NC that requires a minimum voltage value at its drain node to conduct current through, the output signal cannot swing below the sum of the minimum voltage values necessary across device NC, an active switch device and the current source device NS in its saturated state. This characteristic of the circuit further damps the voltage swings at the output near the maximum swing designed, preventing any overshoot, and makes the architecture suitable for higher voltage swings that may be necessitated by longer, high-frequency links.
Whereas faster slew rates are beneficial in binary signaling from a data communications maximum frequency and signal integrity standpoint, implications to EM radiation from the link need further inspection and are beyond the scope of this invention disclosure.
It will be evident to one skilled in the art that the advantages of the invention circuit architecture translate to substantial improvements in binary data transmission, and particularly with regard to data transmission through links with significant signal loss, dispersion or crosstalk such as low-cost video transmission cables. In such applications, conforming to DVI and high-definition multimedia interface (HDMI) specifications, link lengths exceed 15 meters and are often as much as 30 meters. Signal loss is directly proportional to the frequency of operation and to length; DVI/HDMI links are expected to see significant signal degradation as frequencies increase to accommodate high-definition video and lengths increase to facilitate sharing of high-definition video between multiple displays in a building. The invention circuit architecture therefore enables further development of such video communication interfaces.
An alternate embodiment of the invention including transmitter emphasis is shown in
It will be evident to one skilled in the art that this transmit emphasis technique may be implemented to a finer resolution by employing additional equalizing current source branches, and by designing their values and activation control so as to provide the desired equalization function. It will also be evident that the pre-emphasis equalization technique may be similarly implemented in alternate invention embodiments.
Although specific embodiments are illustrated and described herein, any circuit arrangement configured to achieve the same purposes and advantages may be substituted in place of the specific embodiments disclosed. This disclosure is intended to cover any and all adaptations or variations of the embodiments of the invention provided herein. All the descriptions provided in the specification have been made in an illustrative sense and should in no manner be interpreted in any restrictive sense. The scope, of various embodiments of the invention whether described or not, includes any other applications in which the structures, concepts and methods of the invention may be applied. The scope of the various embodiments of the invention should therefore be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled. Similarly, the abstract of this disclosure, provided in compliance with 37 CFR §1.72(b), is submitted with the understanding that it will not be interpreted to be limiting the scope or meaning of the claims made herein. While various concepts and methods of the invention are grouped together into a single ‘best-mode’ implementation in the detailed description, it should be appreciated that inventive subject matter lies in less than all features of any disclosed embodiment, and as the claims incorporated herein indicate, each claim is to viewed as standing on it's own as a preferred embodiment of the invention.
