This application claims the priority benefit of Taiwan Patent Application Serial Number 094102051, filed on Jan. 24, 2005, the full disclosure of which is incorporated herein by reference.
1. Field of the Invention
This invention generally relates to a source driver and a source driving method, and more particularly to a source driver and source driving method for LCDs.
2. Description of the Related Art
The pull-high differential amplifier 210 is operated just while the output voltage Vout is smaller than the voltage at the input Vin+, whereby increasing the output voltage Vout toward the voltage at the input Vin+. In addition, the pull-low differential amplifier 212 is operated just while the output voltage Vout is larger than the voltage at the input Vin+, whereby decreasing the output voltage Vout toward the voltage at the input Vin+.
The operation of the driver 204 is described below. The output voltage Vout is stable while the voltage at the input Vin+ equal to that at the input Vin−. When the voltage at the input Vin+ is changed and larger than that at the input Vin−, that is, when the level voltage Vin is larger than the output voltage Vout, only switches S1, S2, S3 are turned on such that the transistor 220 is turned on by an output voltage V01; then, the output voltage Vout begins increasing toward the voltage at the input Vin+; finally, only switch S0 is turned on such that the input 204a is short to the output 204b whereby more precisely pulling the voltage level of the output voltage Vout to that of the level voltage Vin. In addition, When the voltage at the input Vin+is changed and smaller than that at the input Vin−, that is, when the level voltage Vin is smaller than the output voltage Vout, only switches S4, S5, S6 are turned on such that the transistor 222 is turned on by an output voltage V02; then, the output voltage Vout begins decreasing toward the voltage at the input Vin+; finally, only switch S0 is turned on such that the input 204a is short to the output 204b whereby more precisely pulling the voltage level of the output voltage Vout to that of the level voltage Vin.
However, when the voltage level of the output voltage Vout is close to the voltage level of a high supply voltage VDD and smaller than that of the level voltage Vin, it is difficult for the pull-high differential amplifier 210 to pull up the output voltage Vout. In addition, when the voltage level of the output voltage Vout is close to the voltage level of a low supply voltage VSS and larger than that of the level voltage Vin, it is difficult for the pull-low differential amplifier 212 to pull down the output voltage Vout. Therefore, the output voltage Vout of the driver 204 is limited and cannot cover the whole voltage range between VSS and VDD.
Accordingly, the present invention provides a source driver for LCDs having a wide driving voltage range so as to solve the above-mentioned problem existing in the art.
It is an object of the present invention to provide a source driver for LCDs, which can increase the driving voltage range and decrease the power consumption.
It is another object of the present invention to provide a source driver for LCDs, which can reduce the circuit size and the manufacturing cost of a source driving circuit.
In order to achieve the above object, the source driver for LCD devices, used for driving at least one data line, comprises an input for receiving a predetermined voltage; an output electrically being connected to the data line and having an output voltage; a voltage clamping circuit for clamping the output voltage within a predetermined voltage range; a first differential amplifier for increasing the clamped output voltage toward the predetermined voltage; and a second differential amplifier for decreasing the clamped output voltage toward the predetermined voltage.
The source driver according to the present invention further comprises a first switching circuit and a second switching circuit respectively used for alternatively switching a plurality of predetermined voltages and alternatively switching a plurality of output voltage of a plurality of data lines to the first and second differential amplifiers during a scanning line period, such that the plurality of output voltages at the plurality of data lines can be respectively driven through the first and second differential amplifiers according to the plurality of predetermined voltages. More specifically, since the plurality of data lines can share the first and second differential amplifiers, the circuit size and the manufacturing cost of a source driving circuit can be reduced.
The present invention also provides a source driving method, applied to a source driver, for driving a plurality of data lines each having an output voltage, wherein the source driver includes a first differential amplifier for increasing the output voltage and a second differential amplifier for decreasing the output voltage. The source driving method comprises following steps: clamping the output voltage of each data line within a voltage range between a first voltage and a second voltage such that the output voltage is larger than the first voltage and smaller than the second voltage; and within a predetermined period, alternatively receiving the output voltages of the data lines and a plurality of predetermined voltages through the first and second differential amplifiers whereby respectively pulling the output voltage of each data line toward each predetermined voltage through the first and second differential amplifiers. The source driving method according to the present invention further comprises a step of receiving each predetermined voltage respectively through each data line such that the output voltage of each data line is substantially equal to each predetermined voltage.
According to the source driving method of the present invention, the two differential amplifiers can drive multiple data lines; therefore, the number of differential amplifiers used for driving data lines can be decreased whereby reducing the circuit size and the manufacturing cost of a source driving circuit.
Other objects, advantages, and novel features of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.
The source driver 300 is used for driving two data lines during a scanning line period, that is, for respectively pulling the voltage levels of the output voltages Vout1, Vout2 at the outputs 300c, 300d to those of the level voltages Vin1, Vin2 at the inputs 300a, 300b during a scanning line period. The term “a scanning line period” herein means the time period that one scanning line is selected or activated to turn on one row of transistors on an LCD panel.
In source driver 300, the pull-high differential amplifier 302 has a non-inverting input 302a, an inverting input 302b and an output 302c. The output 302c is connected to the inverting input 302b (negative feedback structure). The pull-low differential amplifier 304 has a non-inverting input 304a, an inverting input 304b and an output 304c. The output 304c is connected to the inverting input 304b (negative feedback structure).
The voltage clamping circuit 306 is used for clamping the output voltages Vout1, Vout2 of the outputs 300c, 300d within a voltage range between a first voltage VA and a second voltage VB.
The switches S1, S2, S3 and S4 of the first switching circuit 308 are used for alternatively and electrically connecting the level voltages Vin1, Vin2 of the inputs 300a, 300b with the non-inverting inputs 302a, 304a of the differential amplifiers 302, 304. The switches S5, S6, S7 and S8 of the second switching circuit 310 are used for alternatively and electrically connecting the outputs 302c, 304c of the differential amplifiers 302, 304 with the outputs 300c, 300d. The switches S9 and S10 of the third switching circuit 312 are used for respectively and electrically connecting the inputs 300a, 300b with the outputs 300c, 300d such that the output voltages Vout1, Vout2 can be respectively and substantially equal to the level voltages Vin1, Vin2.
In
The pull-high differential amplifier 302 includes a differential pair of NMOS (N-type metal oxide semiconductor) transistors NH3 and NH4, a current mirror composed of PMOS (P-type metal oxide semiconductor) transistors PH1 and PH2, and a constant current source CR1. The pull-high differential amplifier 302 has its output connected to the gate of a PMOS transistor PH3, which functions as an output stage. The differential pair of NMOS transistors NH3 and NH4 is electrically connected to the current mirror composed of the PMOS transistors PH1 and PH2. More specifically, the transistor PH1 has its drain electrically connected to the drain of the transistor NH3, its source electrically connected to a high supply voltage VDD, and its gate electrically connected to the gate of the transistor PH2; The transistor PH2 has its drain electrically connected to the drain of the transistor NH4, its source electrically connected to the high supply voltage VDD, and its gate electrically connected to its drain.
The gate of the transistor NH3 is connected to the inputs 300a and 300b respectively through the switches S1 and S4. The transistor NH4 has its gate connected to the drain of the transistor PH3. The sources of the transistors NH3, NH4 are commonly connected to one end of the constant current source CR1, and the other end of the constant current source CR1 is connected to a low supply voltage VSS.
The transistor PH3 functions as charging means and has its source electrically connected to the high supply voltage VDD, its gate electrically connected to the drain of the transistor PH1, and its drain electrically connected to the sources of PMOS transistors PH4 and PH5. The transistors PH4 and PH5 have their drains respectively connected to the outputs 300c and 300d and their gates respectively connected to controlling voltages VENA0 and VENB0. The transistors PH4 and PH5 can function as the switches S5 and S6 shown in
The pull-low differential amplifier 304 includes a differential pair of PMOS transistors PL3 and PL4, a current mirror composed of NMOS transistors NL1 and NL2, and a constant current source CR2. The pull-low differential amplifier 304 has its output connected to the gate of a NMOS transistor NL3, which functions as an output stage. The differential pair of PMOS transistors PL3 and PL4 is electrically connected to the current mirror composed of the NMOS transistors NL1 and NL2. More specifically, the transistor NL1 has its drain electrically connected to the drain of the transistor PL3, its source electrically connected to the low supply voltage VSS, and its gate electrically connected to the gate of the transistor NL2; The transistor NL2 has its drain electrically connected to the drain of the transistor PL4, its source electrically connected to the low supply voltage VSS, and its gate electrically connected to its drain.
The gate of the transistor PL3 is connected to the inputs 300a and 300b respectively through the switches S2 and S3. The transistor PL4 has its gate connected to the drain of the transistor NL3. The sources of the transistors PL3, PL4 are commonly connected to one end of the constant current source CR2, and the other end of the constant current source CR2 is connected to the high supply voltage VDD.
The transistor NL3 functions as discharging means and has its source electrically connected to the low supply voltage VSS, its gate electrically connected to the drain of the transistor NL1, and its drain electrically connected to the sources of NMOS transistors NL4 and NL5. The transistors NL4 and NL5 have their drains respectively connected to the outputs 300c and 300d and their gates respectively connected to controlling voltages VENB1 and VENA1. The transistors NL4 and NL5 can function as the switches S8 and S7 shown in
The voltage clamping circuit 306 has a first sub-clamping circuit composed of an NMOS transistor NC1 and a PMOS transistor PC1, and a second sub-clamping circuit composed of an NMOS transistor NC2 and a PMOS transistor PC2. The transistors NC1 and PC1 function as source followers and have their sources commonly connected to the output 300c, their gates respectively connected to controlling voltages VTL and VTH, and their drains respectively connected to the drains of a PMOS transistor PC3 (also referred to as switch S11) and an NMOS transistor NC3 (also referred to as switch S12). The first sub-clamping circuit composed of the NMOS transistor NC1 and the PMOS transistor PC1 is used for clamping the output voltage Vout1 of the output 300c within a voltage range between a first voltage VA and a second voltage VB such that VA≦Vout1≦VB, wherein both the voltages VA and VB are larger than the low supply voltage VSS and smaller than the high supply voltage VDD. The transistors NC2 and PC2 function as source followers and have their sources commonly connected to the output 300d, their gates respectively connected to the controlling voltages VTL and VTH, and their drains respectively connected to the drains of the PMOS transistor PC3 and the NMOS transistor NC3. The second sub-clamping circuit composed of the NMOS transistor NC2 and the PMOS transistor PC2 is used for clamping the output voltage Vout2 of the output 300d within the voltage range between the first voltage VA and the second voltage VB such that VA≦Vout2≦VB, wherein both the voltages VA and VB are larger than the low supply voltage VSS and smaller than the high supply voltage VDD. More preferably, the transistors NC1 and NC2 have the same threshold voltage and the transistors PC1 and PC2 have the same threshold voltage.
In order to clamp the output voltages Vout1, Vout2 of the outputs 300c, 300d between the first voltage VA and the second voltage VB, the controlling voltages VTL and VTH should conform to the following inequalities:
VB>VTL−Vthn2>=VA (1)
VA<VTH+Vthp2<=VB (2)
wherein Vthn2 is the threshold voltage of the transistors NC1 and NC2, and Vthp2 is the threshold voltage of the transistors PC1 and PC2.
In this embodiment, it is assumed that the threshold voltage Vthn2 of the transistors NC1 and NC2 is equal to the threshold voltage Vthn1 of the transistors NH3 and NH4, and the threshold voltage Vthp2 of the transistors PC 1 and PC2 is equal to the threshold voltage Vthp1 of the transistors PL3 and PL4; the controlling voltage VTL is equal to the sum of the first voltage VA and the threshold voltage Vthn2 (i.e. VTL=VA+Vthn2), and the controlling voltage VTH is equal to the difference of the second voltage VB and the threshold voltage Vthp2 (i.e. VTH=VB−Vthp2). Accordingly, when the output voltages Vout1, Vout2 of the outputs 300c, 300d are fallen into the voltage range between VDD and VB, the transistors PC1, PC2 are turned on due to the fact that the voltage difference Vsg between the source and the gate is larger than the threshold voltage Vthp2; the transistors PC1, PC2 are turned on such that the output voltages Vout1 and Vout2 are discharged to the voltage VB=VTH+Vthp2 respectively through the path of the transistors PC1, NC3 and the low supply voltage VSS and the path of the transistors PC2, NC3 and the low supply voltage VSS. In addition, when the output voltages Vout1, Vout2 of the outputs 300c, 300d are fallen into the voltage range between VSS and VA, the transistors NC1, NC2 are turned on due to the fact that the voltage difference Vgs between the gate and the source is larger than the threshold voltage Vthn2; the transistors NC1, NC2 are turned on such that the output voltages Vout1 and Vout2 are charged to the voltage VA=VTL−Vthn2 respectively through the path of the transistors NC1, PC3 and the high supply voltage VDD and the path of the transistors NC2, PC3 and the high supply voltage VDD. Further, when the output voltages Vout1, Vout2 of the outputs 300c, 300d are fallen into the voltage range between VA and VB, all the transistors PC1, PC2, NC1, NC2 are turned off such that the output voltages Vout1, Vout2 are maintained.
The transistors PC3 and NC3 have their sources respectively connected to the high supply voltage VDD and the low supply voltage VSS, and their gates respectively connected to controlling voltages VPREB and VPRE. The controlling voltages VPREB and VPRE are opposite (inverted) to each other.
The source driver 300 further comprises switches S9, S10 for connecting (shortening) the level voltages Vin1, Vin2 of the inputs 300a, 300b respectively to the outputs 300c, 300d whereby directly driving the output voltages Vout1, Vout2 of the outputs 300c, 300d to the level voltages Vin1, Vin2 respectively.
It should be understood that the pull-high differential amplifier 302 is used for increasing the output voltages Vout1, Vout2 between the voltage VA and the high supply voltage VDD; the pull-low differential amplifier 304 is used for decreasing the output voltages Vout1, Vout2 between the voltage VB and the low supply voltage VSS.
Firstly, during time t0 to t1, the controlling voltage VPRE presents a high voltage level and the controlling voltage VPREB presents a low voltage level such that the transistors PC3 and NC3 (switches S11 and S12) are respectively turned on and the switches S1 to S10 are turned off; meanwhile, the data clamping circuit 306 is enable so as to clamp the voltage values of the output voltages Vout1, Vout2 within the range between VA and VB. In this period, the data clamping circuit 306 pulls the voltage value of the output voltage Vout1 at output 300c from VSS to VA; in addition, the voltage value of the output voltage Vout2 is maintained at V2 since it has been fallen (or clamped) within the range between VA and VB.
Then, during time t1 to t2, switches S1, S3 are turned on while the controlling signals VENA1, VENB0 present a high voltage level and the controlling signals VENA0, VENB1 present a low voltage level, such that the transistors PH4 (switch S5) and NL5 (switch S7) are turned on and the others are turned off. In this period, the data clamping circuit 306 is disable from clamping the voltage voltages Vout1, Vout2, i.e. unclamps the voltage voltages Vout1, Vout2; the transistor NH3 of the pull-high differential amplifier 302 has its gate (non-inverting input) receive the level voltage Vin1 having the value V1 from the input 300a, and the transistor NH4 has its gate (inverting input) receive the output voltage Vout having the value VA from the output 300c. For the pull-high differential amplifier 302, since the voltage value V1 at the non-inverting input is larger than the voltage value VA at the inverting input, the pull-high differential amplifier 302 can increase the output voltage Vout1 of the output 300c from the value VA toward V1 through the transistors PH3, PH4. Meanwhile, the transistor PL3 of the pull-low differential amplifier 304 has its gate (non-inverting input) receive the level voltage Vin2 having the value VDD from the input 300b, and the transistor PL4 has its gate (inverting input) receive the output voltage Vout2 having the value V2 from the output 300d. For the pull-low differential amplifier 304, since the voltage value VDD at the non-inverting input is larger than the voltage value V2 at the inverting input, the pull-low differential amplifier 304 is not operated such that the voltage value of the output voltage Vout2 at the output 300d is maintained at V2.
Then, during time t2 to t3, the switches S2, S4 are turned on while the controlling signals VENA1, VENB0 present a low voltage level and the controlling signals VENA0, VENB1 present a high voltage level, such that the transistors PH5 (switch S6) and NL4 (switch S8) are turned on and the others are turned off. In this period, the transistor NH3 of the pull-high differential amplifier 302 has its gate (non-inverting input) receive the level voltage Vin2 having the value VDD from the input 300b and the transistor NH4 has its gate (inverting input) receive the output voltage Vout2 having the value V2 from the output 300d. For the pull-high differential amplifier 302, since the voltage value VDD at the non-inverting input is larger than the voltage value V2 at the inverting input, the pull-high differential amplifier 302 can increase the output voltage Vout2 of the output 300d from the value V2 toward VDD through the transistors PH3, PH5. Meanwhile, the transistor PL3 of the pull-low differential amplifier 304 has its gate (non-inverting input) receive the level voltage Vin1 having the value V1 from the input 300a, and the transistor PL4 has its gate (inverting input) receive the output voltage Vout1 having the value V1 from the output 300c. For the pull-low differential amplifier 304, since the voltage value V1 at the non-inverting input is equal to that at the inverting input, the pull-low differential amplifier 304 is not operated such that the voltage value of the output voltage Vout1 at the output 300c is maintained at V1.
Finally, during time t3 to t4, only switches S9 and S10 are turned on and the others are turned off such that the inputs 300a and 300b can be electrically connected to (short to) the outputs 300c and 300d respectively. In this period, the level voltages Vin1 and Vin2 at the inputs 300a and 300b can be directly transmitted to the outputs 300c and 300d such that the values of the output voltages Vout1 and Vout2 can more precisely change to V1 and VDD respectively, which is referred to as gamma short.
Firstly, during time t0 to t1, only switches S11, S12 are turned on. In this period, the data clamping circuit 306 pulls the voltage value of the output voltage Vout2 at output 300d from VDD to VB; in addition, the voltage value of the output voltage Vout1 is maintained at V1 since it has been fallen within the range between VA and VB.
Then, during time t1 to t2, only switches S1, S3, S5, S7 are turned on. In this period, the data clamping circuit 306 is disable from clamping the voltage voltages Vout1, Vout2; the transistor NH3 of the pull-high differential amplifier 302 has its gate (non-inverting input) receive the level voltage Vin1 having the value VA from the input 300a, and the transistor NH4 has its gate (inverting input) receive the output voltage Vout1 having the value V1 from the output 300c. For the pull-high differential amplifier 302, since the voltage value VA at the non-inverting input is smaller than the voltage value V1 at the inverting input, the pull-high differential amplifier 302 is not operated such that the voltage value of the output voltage Vout1 at the output 300c is maintained at V1. Meanwhile, the transistor PL3 of the pull-low differential amplifier 304 has its gate (non-inverting input) receive the level voltage Vin2 having the value V3 from the input 300b, and the transistor PL4 has its gate (inverting input) receive the output voltage Vout2 having the value VB from the output 300d. For the pull-low differential amplifier 304, since the voltage value V3 at the non-inverting input is larger than the voltage value VB at the inverting input, the pull-low differential amplifier 304 is not operated such that the voltage value of the output voltage Vout2 at the output 300d is maintained at VB.
Then, during time t2 to t3, only switches S2, S4, S6, S8 are turned on. In this period, the transistor NH3 of the pull-high differential amplifier 302 has its gate (non-inverting input) receive the level voltage Vin2 having the value V3 from the input 300b and the transistor NH4 has its gate (inverting input) receive the output voltage Vout2 having the value VB from the output 300d. For the pull-high differential amplifier 302, since the voltage value V3 at the non-inverting input is larger than the voltage value VB at the inverting input, the pull-high differential amplifier 302 can increase the output voltage Vout2 of the output 300d from the value VB toward V3 through the transistors PH3, PH5. Meanwhile, the transistor PL3 of the pull-low differential amplifier 304 has its gate (non-inverting input) receive the level voltage Vin1 having the value VA from the input 300a, and the transistor PL4 has its gate (inverting input) receive the output voltage Vout1 having the value V1 from the output 300c. For the pull-low differential amplifier 304, since the voltage value at the non-inverting input is smaller to that at the inverting input, the pull-low differential amplifier 304 can decrease the output voltage Vout1 of the output 300c from the value V1 toward VA through the transistors NL3, NL4.
Finally, during time t3 to t4, only switches S9 and S10 are turned on such that the inputs 300a and 300b can be electrically connected to (short to) the outputs 300c and 300d respectively. In this period, the level voltages Vin1 and Vin2 at the inputs 300a and 300b can be directly transmitted to the outputs 300c and 300d such that the values of the output voltages Vout1 and Vout2 can more precisely change to VA and V3 respectively.
According to the source driver of the present invention, since the voltage range from VB to VDD and the voltage range from VA to VSS provides an enough voltage difference respectively, it becomes easily to drive the output voltage to the voltage level VDD or VSS; therefore, the driving voltage range is not limited as compared to that in prior art.
The transistors NH1, NH2 have their drains respectively and electrically connected to the drains of the transistors PH1, PH2 and their sources commonly and electrically connected to the drain of the transistor NH7. The transistors NH2, NH4 have their gates respectively and electrically connected to the drains of the transistors PH5, PH4. The transistors NH3, NH4 have their sources commonly and electrically connected to the drain of the transistor NH6. The transistors NH6, NH7 have their sources electrically connected to one end of the constant current source CR1, and the other end of the constant current source CR1 is electrically connected to the low supply voltage VSS. Further, the transistors NH6, NH7 have their gates respectively and electrically connected to the controlling signals VENA1 and VENB1. The controlling signals VENA1 and VENB1 are used for selectively enabling or disenabling the pull-high differential amplifier 302 and the pull-low differential amplifier 304.
The transistors PL1, PL2 have their drains respectively and electrically connected to the drains of the transistors NL1, NL2 and their sources commonly and electrically connected to the drain of the transistor PL7. The transistors PL2, PL4 have their gates respectively and electrically connected to the drains of the transistors PL4, PL5. The transistors PL3, PL4 have their sources commonly and electrically connected to the drain of the transistor PL6. The transistors PL6, PL7 have their sources electrically connected to one end of the constant current source CR2, and the other end of the constant current source CR2 is electrically connected to the high supply voltage VDD. Further, the transistors PL6, PL7 have their gates respectively and electrically connected to the controlling signals VENA0 and VENB0. The controlling signals VENA0 and VENB0 are used for selectively enabling or disenabling the pull-high differential amplifier 302 and the pull-low differential amplifier 304.
The transistors NH1 and PL3 have their gates commonly and electrically connected to the input 300a for receiving the level voltage Vin1, and the transistors NH3 and PL1 have their gates commonly and electrically connected to the input 300b for receiving the level voltage Vin2.
The operation of the source driver in
The operation of the source driver in
As illustrated above, the driving voltage range of the source driver 300 according to the present invention would not be limited as that of the conventional driver and can be increased whereby solving the problem existing in the prior art.
Further, since a plurality of data lines can share the pull-high differential amplifier 302 and the pull-low differential amplifier 304, the circuit size and the manufacturing cost of a source driving circuit can be reduced.
In the above-mentioned embodiment of the present invention, the source driver 300 has two inputs 300a, 300b and two outputs 300c, 300d for driving two data lines. However, it should be understood that the source driver 300 could only have one input and one output for driving one data line. In addition, if one scanning line period is long enough, the source driver 300 according to the present invention could have more than two inputs and outputs for driving multiple data lines by controlling the switching circuits.
Although the invention has been explained in relation to its preferred embodiment, it is not used to limit the invention. It is to be understood that many other possible modifications and variations can be made by those skilled in the art without departing from the spirit and scope of the invention as hereinafter claimed.
Number | Date | Country | Kind |
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094102051 | Jan 2005 | TW | national |