Patent Application
20110187757
This application claims the priority benefit of Taiwan application serial no. 99102676, filed on Jan. 29, 2010. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
1. Field of the Invention
The present invention relates to a source driving apparatus for a display.
2. Description of Related Art
Referring to
The display panel 120 (for example, a liquid crystal display panel) can be equivalent to a circuit formed by a resistor Rp and a capacitor Cp. Namely, the conventional source driving apparatus 110 directly provides the output voltage Voutput to the display panel 120. On the other hand, to ensure all of the display signals DATA having the corresponding gamma voltages to serve as the output of the DAC 112, the gamma voltage generator 111 is required to generate enough gamma voltages. Taking the display signal DATA of 8 bits as an example, the gamma voltage generator 111 is required to generate 256 gamma voltages.
The present invention is directed to a source driving apparatus of a display, which can provide gamma voltages to drive different display panels according to different modulation frequencies.
The present invention provides a source driving apparatus of a display. The source driving apparatus includes a digital-to-analog converter (DAC), a selecting signal generator and a voltage selector. The DAC receives a first part display signal of a display signal and a plurality of gamma voltages and selects to output a first selecting gamma voltage and a second selecting gamma voltage within the gamma voltages according to the first part display signal. The selecting signal generator receives a second part display signal of the display signal expect the first part display signal and a plurality of pulse-width-modulation (PWM) signals. The selecting signal generator selects one of the PWM signals to generate a selecting signal according to the second part display signal. The voltage selector is coupled to the selecting signal generator and the DAC, and outputs the first selecting gamma voltage or the second selecting gamma voltage according to a pulse width of the selecting signal.
In an embodiment of the present invention, the display signal has N bits, the first part display signal has M bits, and the second part display signal has N-M bits, wherein N and M are positive integers and N is greater than M.
In an embodiment of the present invention, the voltage selector selects to output the second selecting gamma voltage when the selecting signal has a high voltage level, and selects to output the first selecting gamma voltage when the selecting signal has a low voltage level, wherein the first selecting gamma voltage is smaller than the second selecting gamma voltage.
In an embodiment of the present invention, the source driving apparatus further includes a gamma voltage generator, and the gamma voltage generator is coupled to the DAC for providing the gamma voltages.
In an embodiment of the present invention, the source driving apparatus further includes a selecting signal shielding device. The selecting signal shielding device is coupled between the selecting signal generator and the voltage selector, and receives a shielding signal. The selecting signal shielding device enables the voltage selector to fixedly output one of the first selecting gamma voltage and the second selecting gamma voltage according to the shielding signal.
In an embodiment of the present invention, the selecting signal shielding device is an AND gate. An input terminal of the AND gate is coupled to the selecting signal generator, another input terminal of the AND gate receives the shielding signal, and an output terminal of the AND gate is coupled to the voltage selector.
In an embodiment of the present invention, the source driving apparatus further includes an output buffer module. The output buffer module is coupled to the voltage selector, and receives an output of the voltage selector to generate an output voltage.
In an embodiment of the present invention, the output buffer module is a voltage follower.
In an embodiment of the present invention, the output buffer module includes a first chopper, a first operational amplifier, a bias voltage source, a second chopper and a second operational amplifier. An input terminal of the first chopper receives the output of the voltage selector, and another input terminal receives the output signal. An input terminal of the first operational amplifier is coupled to an output terminal of the first chopper. The bias voltage source is coupled between the first chopper and the first operational amplifier. An input terminal of the second chopper is coupled to an output terminal of the first operational amplifier. An input terminal of the second operational amplifier is coupled to an output terminal of the second chopper, and an output terminal thereof outputs the output signal.
According to the above descriptions, in the present invention, the selecting signal generator outputs PWM signals of different frequencies according to the second part display signal, so as to modulate a frequency suitable for the display panel to be driven by the source driving apparatus. Moreover, an interpolation effect is achieved according PWM signals of different pulse widths.
In order to make the aforementioned and other features and advantages of the present invention comprehensible, several exemplary embodiments accompanied with figures are described in detail below.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
Referring to
For example, if the display signal DATA is consisted of 8 bits from a 7th bit to a 0th bit, and the part display data transmitted to the DAC 220 is the 7th bit to the 2nd bit (total 6 bits) in the display signal DATA, the gamma voltage generator 210 is required to generate 26 (i.e. 64) gamma voltages.
Moreover, a method for the DAC 220 selecting the first selecting gamma voltage V1 and the second gamma voltage V2 is described as follows with reference of the above example. If the part display signal transmitted to the DAC 220 is “101010” (arranged from a high bit to a low bit), the DAC 220 selects a gamma voltage corresponding to “10101000” to serve as the first selecting gamma voltage V1, and selects a gamma voltage corresponding to “10101011” to serve as the second selecting gamma voltage (V2−V1)*0.75+V1.
Another part display signal of the display signal DATA is transmitted to the selecting signal generator 230. The selecting signal generator 230 further receives a plurality of pulse-width-modulation (PWM) signals phi0, phi1, phi2 and phi3. Pulse widths of the PWM signals phi0, phi1, phi2 and phi3 are different. Assuming the other part display signal has two bits, the selecting signal generator 230 selects to output one of the four PWM signals phi0-phi3 to serve as a selecting signal according to the part display signal with two bits.
The voltage selector 240 is coupled to the selecting signal generator 230 and the DAC 220. The voltage selector 240 receives the selecting signal generated by the selecting signal generator 230 and the first selecting gamma voltage V1 and the second selecting gamma voltage V2 generated by the DAC 220. The selecting signal is a PWM signal, and it is known by those skilled in the art that the PWM signal is consisted of a high level voltage and a low level voltage. Therefore, the voltage selector 240 outputs the first selecting gamma voltage V1 or the second selecting gamma voltage V2 according to a high level or a low level of the selecting signal.
For example, if a duty cycle of the PWM signal phi3 is 75%, a duty cycle of the PWM signal phi2 is 50%, a duty cycle of the PWM signal phi1 is 25%, and a duty cycle of the PWM signal phi0 is 0%, and if the selecting signal received by the voltage selector 240 is the PWM signal phi3, 75% of the output of the voltage selector 240 is maintained to the higher second selecting gamma voltage V2, and 25% of the output of the voltage selector 240 is maintained to the lower first selecting gamma voltage V1. In view of an average voltage, the average voltage of the output of the voltage selector 240 can be represented by Vavg=V1+(V2−V1)*75%. In other words, if the selecting signal received by the voltage selector 240 is the PWM signal phi1, 25% of the output of the voltage selector 240 is maintained to the second selecting gamma voltage V2, and 75% of the output of the voltage selector 240 is maintained to the first selecting gamma voltage V1. In this case, the average voltage of the output of the voltage selector 240 can be represented by Vavg=V1+(V2−V1)*25%.
Referring to
It should be noticed that it is only an example for implementing the selecting signal shielding device 250 by the AND gate AND1, and those skilled in the art should understand that the same function probably corresponds to various logic circuit implementations, and logic gates such as an OR gate, an NAND gate or an NOR gate can also be used to implement the selecting signal shielding device 250.
The output buffer module 260 is coupled to the voltage selector 240, and is used for receiving the output of the voltage selector 240 to generate the output signal Voutput. In the present embodiment, the output buffer module 260 is implemented by coupling an operational amplifier OP2 as a voltage follower. Namely, one input terminal of the operational amplifier OP2 receives the output of the voltage selector 240, and another input terminal of the operational amplifier OP2 is coupled to an output terminal thereof, and the output terminal outputs the output signal Voutput.
During a duty cycle T2, when the source driving apparatus 200 detects that the vertical synchronization signal Hsync is enabled, the selecting signal generator 230 selects to output the PWM signal phi1 according to the 0th bit and the 1st bit of the display data DATA (DATA[1:0]=“01”). Before the output signal Voutput is raised to the first selecting gamma voltage V1, the shielding signal INT_ON is set to the logic low level. When the output signal Voutput is raised to the first selecting gamma voltage V1, the shielding signal INT_ON is set to the logic high level, and now the selecting signal phi1 generated by the selecting signal generator 230 is transmitted to the voltage selector 240. In this way, the voltage selector 240 outputs the second selecting gamma voltage V2 when the selecting signal phi 1 has the high level, and outputs the first selecting gamma voltage V1 when the selecting signal phi0 has the high level.
Similar as above, during a duty cycle T3, the selecting signal generator selects to output the PWM signal phi3 according to the 0th bit and the 1st bit of the display data DATA (DATA[1:0]=“11”). The voltage selector 240 generates the output OUT1 maintained to the second selecting gamma voltage V2 for a longer time.
Moreover, a driving voltage VPANEL is a signal actually received by the display panel 290. Since the display panel 290 can be equivalent to a low pass filter, the output signal Voutput transmitted to the display panel 290 can generate the driving voltage VPANEL having a waveform more close to a required waveform used for driving the display panel 290.
Referring to
It should be noticed that regarding the PWM signals phi1-phi3 mentioned in the aforementioned embodiments of the present invention, besides the pulse widths thereof can be set according to the corresponding part display signal, frequencies thereof can also be set according to a capacitance and a resistance of the driven display panel. In brief, the frequencies of the PWM signals phi1-phi3 are required to be higher than a cut-off frequency of an equivalent load (formed by a capacitor and a resistor) of the display panel.
In summary, in the present invention, the display signal is split into a high bit and a low bit part display signals, and the gamma voltage is selected according to the high bit part display signal, and then the PWM signal is generated according to the low bit part display signal. In this way, a number of the gamma voltages required to be generated by the gamma voltage generator is reduced, so that a circuit area is saved. Moreover, a suitable driving voltage can be provided in collaboration with the equivalent circuit formed by the capacitor and the resistor of the display panel, so as to improve a display quality.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 99102676 | Jan 2010 | TW | national |
